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t.p.northover (Tim Northover)
Lord High Supreme Bullshitter

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User Since
Oct 18 2012, 4:53 AM (330 w, 6 d)

Recent Activity

Fri, Feb 8

Herald added a project to D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM: Restricted Project.
Fri, Feb 8, 2:57 AM · Restricted Project

Thu, Feb 7

t.p.northover updated the diff for D57820: [AArch64] Use CAS loops for all atomic operations when available..

I was looking at this again and noticed it didn't handle unordered loads & stores properly. It tried to create unordered atomicrmw/cmpxchg, which are illegal and assert. So I updated it to promote unordered to monotonic.

Thu, Feb 7, 4:16 AM · Restricted Project
t.p.northover committed rG638110a20883: AArch64: implement copy for paired GPR registers. (authored by t.p.northover).
AArch64: implement copy for paired GPR registers.
Thu, Feb 7, 2:36 AM

Wed, Feb 6

t.p.northover committed rG474f5d9b5539: AArch64: enforce even/odd register pairs for CASP instructions. (authored by t.p.northover).
AArch64: enforce even/odd register pairs for CASP instructions.
Wed, Feb 6, 7:27 AM
t.p.northover created D57820: [AArch64] Use CAS loops for all atomic operations when available..
Wed, Feb 6, 7:14 AM · Restricted Project
t.p.northover committed rG71025a2f3e11: AArch64: annotate atomics with dropped acquire semantics when printing. (authored by t.p.northover).
AArch64: annotate atomics with dropped acquire semantics when printing.
Wed, Feb 6, 7:08 AM

Fri, Jan 25

t.p.northover accepted D57125: [HotColdSplit] Introduce a cost model to control splitting behavior.

I think this looks pretty reasonable. The penalties are a bit speculative (fairly inevitably since the instructions haven't been created yet), but look sane. If they turn out to be problematic in future we could add some hooks to customize them.

Fri, Jan 25, 7:06 AM

Thu, Jan 24

t.p.northover added inline comments to D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM.
Thu, Jan 24, 1:58 AM · Restricted Project

Tue, Jan 22

t.p.northover added a comment to D57054: [MachineOutliner][ARM][RFC] Add Machine Outliner support for ARM.

Thanks very much for working on this, those numbers look promising. I had a quick read over, and have a few comments. I haven't looked at the checking logic in detail yet, mostly just the CodeGen part.

Tue, Jan 22, 7:32 AM · Restricted Project

Jan 16 2019

t.p.northover accepted D55572: [AArch64] Add patterns for zext/sext of shift amount..

Thanks! LGTM.

Jan 16 2019, 2:13 AM

Dec 20 2018

t.p.northover added inline comments to D55909: [ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR..
Dec 20 2018, 2:02 AM
t.p.northover added inline comments to D55909: [ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR..
Dec 20 2018, 1:55 AM

Dec 18 2018

t.p.northover accepted D54743: SROA: preserve alignment tags on loads and stores..

Thanks Gerolf. Committed as r349465.

Dec 18 2018, 1:37 AM · Restricted Project

Dec 14 2018

t.p.northover added a comment to D55421: FastISel: take care to update iterators when removing instructions..

Ping.

Dec 14 2018, 3:13 AM
t.p.northover added inline comments to D54743: SROA: preserve alignment tags on loads and stores..
Dec 14 2018, 3:11 AM · Restricted Project

Dec 13 2018

t.p.northover added a comment to D54749: Saturating float to int casts: Basics [1/n].

I think the consistency argument is good, so I'm in favour of the structure you chose now. My main issue at the moment is the tests: hard-coding register usage leads to very fragile tests.

Dec 13 2018, 2:42 AM
t.p.northover accepted D55630: [ARM] Complete the Thumb1 shift+and->shift+shift transforms..

I think this looks fine.

Dec 13 2018, 2:42 AM
t.p.northover added a comment to D55572: [AArch64] Add patterns for zext/sext of shift amount..

update_llc_test_checks is a useful starting point because it generates the right checks to ensure you're checking the whole function, which is inconvenient to do by hand (trying to CHECK-NOT your way to checking the whole function is a bad idea).

Dec 13 2018, 2:39 AM

Dec 12 2018

t.p.northover added inline comments to D55572: [AArch64] Add patterns for zext/sext of shift amount..
Dec 12 2018, 3:06 AM
t.p.northover accepted D55586: Basic: make `int_least64_t` and `int_fast64_t` match on Darwin.

LGTM; well spotted!

Dec 12 2018, 2:58 AM

Dec 11 2018

t.p.northover added a comment to D55562: Atomics: support min/max orthogonally.

What does it do with floating-point inputs?

Dec 11 2018, 1:11 PM · Restricted Project
t.p.northover created D55562: Atomics: support min/max orthogonally.
Dec 11 2018, 9:20 AM · Restricted Project

Dec 7 2018

t.p.northover created D55421: FastISel: take care to update iterators when removing instructions..
Dec 7 2018, 3:00 AM
t.p.northover updated the diff for D54743: SROA: preserve alignment tags on loads and stores..

Separated NFC alias analysis move out into https://reviews.llvm.org/D55420, which this change applies on top of.

Dec 7 2018, 2:56 AM · Restricted Project
t.p.northover created D55420: SROA: move AATags member into base OpSplitter class. NFC..
Dec 7 2018, 2:54 AM

Dec 4 2018

t.p.northover added a comment to D54743: SROA: preserve alignment tags on loads and stores..

Maybe explicitly add reviewers?

Dec 4 2018, 5:41 AM · Restricted Project
t.p.northover added reviewers for D54743: SROA: preserve alignment tags on loads and stores.: bkramer, chandlerc.
Dec 4 2018, 5:41 AM · Restricted Project

Dec 3 2018

t.p.northover closed D53190: ARM: avoid infinite combining loop.

Great to see those other test changes!

Dec 3 2018, 3:19 AM

Nov 28 2018

t.p.northover added a comment to D54743: SROA: preserve alignment tags on loads and stores..

Ping.

Nov 28 2018, 6:03 AM · Restricted Project
t.p.northover updated the diff for D53190: ARM: avoid infinite combining loop.

Ah, I see what you mean. It's not pretty, but this updated patch seems to do the trick.

Nov 28 2018, 5:47 AM

Nov 27 2018

t.p.northover added a comment to D54533: InstCombine: don't assume malloc will never return nullptr.

Good idea. I committed a comment in r347653.

Nov 27 2018, 3:51 AM
t.p.northover added a comment to D53190: ARM: avoid infinite combining loop.

Ping.

Nov 27 2018, 2:27 AM

Nov 20 2018

t.p.northover added a comment to D54749: Saturating float to int casts: Basics [1/n].

The current implementation is the first and is modeled after what sign_extend_inreg does.

Nov 20 2018, 6:02 AM
t.p.northover added inline comments to D54749: Saturating float to int casts: Basics [1/n].
Nov 20 2018, 6:01 AM
t.p.northover abandoned D54533: InstCombine: don't assume malloc will never return nullptr.

Interesting; I (obviously) hadn't considered that interpretation of what's going on, or I'd have mentioned it. I think it just about holds water, so thanks for setting me straight!

Nov 20 2018, 5:26 AM
t.p.northover created D54743: SROA: preserve alignment tags on loads and stores..
Nov 20 2018, 1:45 AM · Restricted Project

Nov 15 2018

t.p.northover added a comment to D54604: Automatic variable initialization.

This isn't meant to change the semantics of C and C++.

Nov 15 2018, 4:13 PM · Restricted Project

Nov 14 2018

t.p.northover created D54533: InstCombine: don't assume malloc will never return nullptr.
Nov 14 2018, 8:49 AM
t.p.northover added a comment to D53190: ARM: avoid infinite combining loop.

Ok, fair point. If we are going to introduce a new node to fix this issue, could we have a SUBS node that can be glued to the CMOV?

Nov 14 2018, 3:22 AM

Nov 1 2018

t.p.northover updated the diff for D53514: os_log: make buffer size an integer constant expression..

Same as previous patch except the OSLog helpers are moved to libclangAST to respect dependencies.

Nov 1 2018, 9:52 AM
t.p.northover reopened D53514: os_log: make buffer size an integer constant expression..

Turns out I neglected the layering between libclangAST and libclangAnalysis so I've reverted for now. For this to work I think we need to move the OSLog helpers into libclangAST. I'll put together a new patch and upload it.

Nov 1 2018, 9:40 AM
t.p.northover closed D53514: os_log: make buffer size an integer constant expression..

Thanks Eli. I committed it as r345828, and then had to fixup some linker dependencies on other platforms, which took me a couple of tries (r345833 and r345835).

Nov 1 2018, 8:38 AM

Oct 29 2018

t.p.northover added a comment to D53190: ARM: avoid infinite combining loop.

It seems unlikely this is the only place where a problem with cycles during DAG combining/lowering pops up.

Oct 29 2018, 6:22 AM
t.p.northover added a comment to D53514: os_log: make buffer size an integer constant expression..

Ping.

Oct 29 2018, 6:14 AM

Oct 24 2018

t.p.northover closed D53658: [DAG] Inspect more store operands for cycle before merging..

Thanks. Committed as r345200.

Oct 24 2018, 2:39 PM
t.p.northover closed D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Thanks. Committed as r345188.

Oct 24 2018, 1:42 PM
t.p.northover accepted D53633: [AArch64] Implement FP16FML intrinsics.

I think this is reasonable.

Oct 24 2018, 10:52 AM · Restricted Project
t.p.northover added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Isn't this change always enabled for -Os? So it should be easy to test it or to enable down to a single function, shouldn't it?

Oct 24 2018, 10:50 AM
t.p.northover added a comment to D53190: ARM: avoid infinite combining loop.

Ping.

Oct 24 2018, 10:45 AM
t.p.northover updated the diff for D53658: [DAG] Inspect more store operands for cycle before merging..

Fixing capitalization of variable. Oops.

Oct 24 2018, 10:19 AM
t.p.northover created D53658: [DAG] Inspect more store operands for cycle before merging..
Oct 24 2018, 10:06 AM

Oct 22 2018

t.p.northover closed D48925: X86: add alias for pushfw/popfw in Intel mode.

Thanks. Finally got round to committing this as r344949.

Oct 22 2018, 1:41 PM
t.p.northover added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Putting it in AArch64Subtarget.cpp also means you can't even in principle set it on a per-function basis without changing your CPU (which is icky).

Oct 22 2018, 10:44 AM
t.p.northover added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Rather than a feature in AArch.td, I'd prefer a line in AArch64Subtarget::initializeProperties().

Oct 22 2018, 10:41 AM
t.p.northover created D53514: os_log: make buffer size an integer constant expression..
Oct 22 2018, 10:37 AM

Oct 16 2018

t.p.northover accepted D53348: [AArch64] Define __ELF__ for aarch64-none-elf and other similar triples..

Looks reasonable.

Oct 16 2018, 7:18 PM

Oct 12 2018

t.p.northover created D53190: ARM: avoid infinite combining loop.
Oct 12 2018, 4:46 AM
t.p.northover updated the diff for D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Sure.

Oct 12 2018, 2:55 AM
t.p.northover updated the diff for D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Fair enough, I've disabled it for Exynos processors except under MinSize conditions. OK to commit?

Oct 12 2018, 12:59 AM

Oct 10 2018

t.p.northover updated the diff for D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Rebase to master

Oct 10 2018, 2:39 AM

Oct 9 2018

t.p.northover added inline comments to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.
Oct 9 2018, 3:23 PM
t.p.northover added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Yes, I do. Exynos limits the size of jump tables, resulting in a daisy chain of smaller jump tables. This patch changes the jump table code, so I'd like to evaluate the performance impact, unless this pass is gated by -Os.

Oct 9 2018, 3:20 PM
t.p.northover added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

As you'd expect, size is pretty good. Over the test-suite (including externals) nothing regresses. The total benefit over all the code is 0.5%, with notable highlights of 25% in 401.bzip2, 7% in 403.gcc, and 4% in 177.mesa.

Oct 9 2018, 6:40 AM

Oct 8 2018

t.p.northover accepted D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.

Thanks. This looks fine now.

Oct 8 2018, 6:57 AM
t.p.northover added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Ping.

Oct 8 2018, 4:46 AM
t.p.northover accepted D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.

Looks fine.

Oct 8 2018, 4:05 AM
t.p.northover added inline comments to D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
Oct 8 2018, 4:04 AM
t.p.northover accepted D52867: [AArch64][v8.5A] Branch Target Identification code-generation pass.

I think this looks reasonable.

Oct 8 2018, 4:01 AM
t.p.northover accepted D52645: [AsmParser] Return an error in the case of empty symbol ref in an expression.

Looks fine to me.

Oct 8 2018, 2:26 AM

Sep 27 2018

t.p.northover accepted D52621: [AArch64] Split zero cycle feature more granularly.

This looks fine to me.

Sep 27 2018, 10:43 AM
t.p.northover accepted D52484: [ARM][v8.5A] Add speculation barriers SSBB and PSSBB.

This looks fine too after the AArch64 clarification.

Sep 27 2018, 10:16 AM
t.p.northover accepted D52483: [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB.

Thanks for the clarification. LGTM.

Sep 27 2018, 8:21 AM
t.p.northover accepted D52477: [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets.

Looks fine.

Sep 27 2018, 6:30 AM
t.p.northover accepted D52489: [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI).

This is fine.

Sep 27 2018, 6:23 AM
t.p.northover accepted D52485: [AArch64][v8.5A] Add Branch Target Identification instructions.

This looks good.

Sep 27 2018, 6:23 AM
t.p.northover accepted D52479: [AArch64][v8.5A] Add prediction invalidation instructions to AArch64.

This looks fine.

Sep 27 2018, 6:17 AM
t.p.northover added inline comments to D52483: [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB.
Sep 27 2018, 6:12 AM
t.p.northover accepted D52487: [AArch64][v8.5A] Add MTE system instructions.

This looks fine.

Sep 27 2018, 6:10 AM
t.p.northover accepted D52480: [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction.

Looks fine to me.

Sep 27 2018, 6:06 AM
t.p.northover accepted D52475: [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions.

Thanks. That makes more sense. LGTM!

Sep 27 2018, 6:03 AM
t.p.northover accepted D52476: [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set.

Thanks. Looks fine now.

Sep 27 2018, 1:32 AM
t.p.northover accepted D52473: [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag.

Thanks. Looks fine now.

Sep 27 2018, 1:31 AM

Sep 26 2018

t.p.northover added inline comments to D52475: [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions.
Sep 26 2018, 8:01 AM
t.p.northover added inline comments to D52473: [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag.
Sep 26 2018, 8:00 AM
t.p.northover requested changes to D52476: [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set.

Actually, sorry. I think this should be marked HasSideEffects.

Sep 26 2018, 8:00 AM
t.p.northover added a comment to D52473: [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag.

So, what's this one actually for? I'm guessing x86 emulation in some manner, but I just couldn't work out how it makes things better.

Sep 26 2018, 7:55 AM
t.p.northover accepted D52476: [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set.

This looks fine.

Sep 26 2018, 7:55 AM
t.p.northover accepted D52474: [AArch64] Extend single-operand FP insns to match Arm ARM (NFCI).

Looks fine to me.

Sep 26 2018, 7:49 AM

Sep 24 2018

t.p.northover updated the diff for D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Tidy-ups suggested by JF, and (also JF's idea) switch to an offset from the lowest-addressed basic-block instead of the actual branch to increase the number of candidates.

Sep 24 2018, 7:20 AM
t.p.northover added inline comments to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.
Sep 24 2018, 7:20 AM

Sep 21 2018

t.p.northover accepted D52335: AArch64FastISel: Abort intrinsic selection if the left operand didn't select.

I've had a go at producing an example too with no luck. The Constant involved on the breaking config is ridiculously complex (even after reduction): i32 or (i32 shl (i32 or (i32 shl (i32 or (i32 shl (i32 and (i32 ptrtoint ([19 x i8]* @0 to i32), i32 63), i32 8), i32 and (i32 lshr (i32 ptrtoint ([19 x i8]* @0 to i32), i32 6), i32 63)), i32 8), i32 and (i32 lshr (i32 lshr (i32 ptrtoint ([19 x i8]* @0 to i32), i32 6), i32 6), i32 63)), i32 8), i32 lshr (i32 lshr (i32 lshr (i32 ptrtoint ([19 x i8]* @0 to i32), i32 6), i32 6), i32 6))

Sep 21 2018, 6:14 AM
t.p.northover updated the diff for D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Thread necromancy! I realised that I got distracted and never finished this discussion.

Sep 21 2018, 4:29 AM

Sep 20 2018

t.p.northover added inline comments to D48131: [RISCV] Implement codegen for cmpxchg on RV32IA.
Sep 20 2018, 4:52 AM

Sep 13 2018

t.p.northover accepted D51780: ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4..

Thanks. Committed as r342127.

Sep 13 2018, 3:56 AM

Sep 12 2018

t.p.northover updated the diff for D51780: ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4..

I think I've implemented the suggested changes, except for the function alignment one.

Sep 12 2018, 4:13 AM

Sep 10 2018

t.p.northover added a comment to D51780: ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4..

We should also be aligning functions?

Sep 10 2018, 5:09 AM

Sep 7 2018

t.p.northover created D51780: ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4..
Sep 7 2018, 5:27 AM
t.p.northover closed D51678: ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.

Thanks. Committed as r341642.

Sep 7 2018, 5:21 AM

Sep 6 2018

t.p.northover added inline comments to D51678: ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.
Sep 6 2018, 2:40 PM
t.p.northover updated the diff for D51678: ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.

Added the addressing-mode to ARMFrameLowering. The only other place that uses them appears to be optional (for an efficiency gain), so I skipped that.

Sep 6 2018, 5:57 AM