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- Apr 21 2014, 4:27 PM (465 w, 3 d)
Fri, Mar 17
Tue, Mar 14
Looks good, thanks!
Thu, Mar 2
Looks good. Thanks for the quick fix @mib!
This broke Lua support:
Feb 21 2023
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Feb 10 2023
Please post an RFC for this. So far it looks to me like something that can be dealt with in AMDGPU codegen.
Feb 8 2023
Feb 7 2023
Feb 6 2023
LGTM, thanks!
Feb 3 2023
LGTM!
Feb 1 2023
Jan 31 2023
The cxx tests passed for me.
Jan 24 2023
Jan 13 2023
I'm not sure how it helps, but this isn't a huge deal anyways.
Jan 11 2023
Jan 10 2023
Jan 6 2023
The DefaultVLIWScheduler class is really a thin wrapper on top of ScheduleDAGInstrs that holds/applies graph mutations. It doesn't really do anything useful on its own, and there isn't much there that you can customize. I'm not sure why you'd want to make it available, could you explain your use case?
Jan 2 2023
All of Hexagon's atomics are implemented using load-locked/store-conditional. If that meets the expectations of these macros, then this is fine with me.
Dec 18 2022
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Dec 5 2022
Thanks Steven. Investigating...
I thought I built everything... Thanks for the fix!
Dec 4 2022
Dec 3 2022
Dec 2 2022
Dec 1 2022
Hi Steven,
Thank you for the testcase, it's important to investigate the differences even if it turns out that they're expected, so this is not a problem at all.
Nov 29 2022
Nov 26 2022
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Nov 18 2022
In Hexagon we try to find a pre-existing register that we can reuse:
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp#L286-L333
The failures were due to the old version of this commit.
Nov 17 2022
Nov 16 2022
Nov 15 2022
I committed a fix for the stack slot issue: https://reviews.llvm.org/rG44bd80751274. This patch should be good to recommit.
Nov 13 2022
Nov 12 2022
The problem is unrelated to this patch.
Nov 11 2022
This is good enough. Thanks!
Do you have a testcase that causes the crash?
Nov 10 2022
LGTM. Thanks!
Nov 9 2022
Added static_assert tests to the unit tests.