kparzysz (Krzysztof Parzyszek)
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User Since
Apr 21 2014, 4:27 PM (213 w, 2 d)

Recent Activity

Tue, May 22

kparzysz committed rL333009: [Hexagon] Add patterns for accumulating HVX compares.
[Hexagon] Add patterns for accumulating HVX compares
Tue, May 22, 11:31 AM
kparzysz added a comment to D47199: [MC] Remove PhysRegSize from MCRegisterClass.

I'm ok with it, but please wait for Quentin's input.

Tue, May 22, 9:50 AM

Mon, May 21

kparzysz added a comment to D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.

Pinging @t.p.northover...

Mon, May 21, 12:50 PM

Fri, May 18

kparzysz added inline comments to D47073: Document and Enforce new Host Compiler Policy.
Fri, May 18, 8:53 AM
kparzysz added inline comments to D47073: Document and Enforce new Host Compiler Policy.
Fri, May 18, 8:38 AM
kparzysz accepted D47036: [Hexagon] Generate post-increment for floating point types.
Fri, May 18, 5:36 AM

Thu, May 17

kparzysz accepted D46999: [Hexagon] Use addAliasForDirective for data directives.

LGTM. Thanks!

Thu, May 17, 5:34 AM

Wed, May 16

kparzysz committed rL332526: [Hexagon] Fix the order of operands when selecting QCAT.
[Hexagon] Fix the order of operands when selecting QCAT
Wed, May 16, 2:06 PM
kparzysz committed rL332525: [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns.
[Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns
Wed, May 16, 2:04 PM
kparzysz added inline comments to rL332379: AMDGPU/GlobalISel: Implement select() for G_FCONSTANT.
Wed, May 16, 5:35 AM

Tue, May 15

kparzysz committed rL332383: [Hexagon] Add driver options for subtarget features.
[Hexagon] Add driver options for subtarget features
Tue, May 15, 11:20 AM
kparzysz committed rC332383: [Hexagon] Add driver options for subtarget features.
[Hexagon] Add driver options for subtarget features
Tue, May 15, 11:19 AM
kparzysz committed rL332369: [Hexagon] Remove unused function from subtarget.
[Hexagon] Remove unused function from subtarget
Tue, May 15, 9:36 AM
kparzysz committed rL332365: [Hexagon] Remove unused flag from subtarget and (non)corresponding test.
[Hexagon] Remove unused flag from subtarget and (non)corresponding test
Tue, May 15, 9:17 AM

Mon, May 14

kparzysz committed rL332292: [Hexagon] Add a target feature to control using small data section.
[Hexagon] Add a target feature to control using small data section
Mon, May 14, 2:05 PM
kparzysz committed rL332290: [Hexagon] Add a target feature for generating new-value stores.
[Hexagon] Add a target feature for generating new-value stores
Mon, May 14, 1:45 PM
kparzysz committed rL332285: [Hexagon] Add a target feature for memop generation.
[Hexagon] Add a target feature for memop generation
Mon, May 14, 1:13 PM
kparzysz committed rL332260: [Hexagon] Avoid predicate copies to integer registers from store-locked.
[Hexagon] Avoid predicate copies to integer registers from store-locked
Mon, May 14, 9:45 AM
kparzysz added a comment to D46324: [BranchFolding] Allow hoisting to block with a single conditional branch..

Alright then. LGTM.

Mon, May 14, 8:46 AM
kparzysz added a comment to D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.

Ping.

Mon, May 14, 8:26 AM

Sat, May 12

kparzysz added a comment to D46324: [BranchFolding] Allow hoisting to block with a single conditional branch..

One thought I had was: if there is a block with only an unconditional branch, should we fold it away first? That is, redirect any branches to that block to the target of the branch?

Sat, May 12, 7:11 AM
kparzysz accepted D46324: [BranchFolding] Allow hoisting to block with a single conditional branch..

Looks ok to me.

Sat, May 12, 7:05 AM

Fri, May 11

kparzysz committed rC332105: [Hexagon] Implement checking arguments of builtin calls.
[Hexagon] Implement checking arguments of builtin calls
Fri, May 11, 9:48 AM
kparzysz committed rL332105: [Hexagon] Implement checking arguments of builtin calls.
[Hexagon] Implement checking arguments of builtin calls
Fri, May 11, 9:48 AM

Thu, May 10

kparzysz added inline comments to D46193: [LSR] Skip LSR if the cost of input is cheaper than LSR's solution.
Thu, May 10, 7:22 AM

Wed, May 9

kparzysz committed rL331918: [Hexagon] Add patterns for vector shift-and-accumulate.
[Hexagon] Add patterns for vector shift-and-accumulate
Wed, May 9, 2:14 PM
kparzysz committed rL331907: [Hexagon] Check the end of the correct container (fix typo).
[Hexagon] Check the end of the correct container (fix typo)
Wed, May 9, 11:37 AM
kparzysz accepted D46649: [AggressiveInstCombine] convert a chain of 'and-shift' bits into masked compare.

With the extra 40-bit testcase.

Wed, May 9, 11:22 AM
kparzysz added a comment to D46649: [AggressiveInstCombine] convert a chain of 'and-shift' bits into masked compare.

This looks good to me, I'm not concerned about the recursion, most of it is tail-recursion anyway.

Wed, May 9, 11:06 AM
kparzysz added a comment to D46193: [LSR] Skip LSR if the cost of input is cheaper than LSR's solution.

Here's the IR immediately before LSR:

Wed, May 9, 10:55 AM
kparzysz added a comment to D46193: [LSR] Skip LSR if the cost of input is cheaper than LSR's solution.

Here's a testcase where LSR generates code that it worse than the original (on Hexagon):

Wed, May 9, 10:50 AM
kparzysz committed rL331887: [Hexagon] Fix sanitizer error about using -1u in variable of enum type.
[Hexagon] Fix sanitizer error about using -1u in variable of enum type
Wed, May 9, 8:51 AM
kparzysz committed rL331885: [LV] Change MaxVectorSize bound to 256 in assertion, NFC otherwise.
[LV] Change MaxVectorSize bound to 256 in assertion, NFC otherwise
Wed, May 9, 8:21 AM
kparzysz committed rL331883: [Hexagon] Simplify MCCodeEmitter, move data to tables.
[Hexagon] Simplify MCCodeEmitter, move data to tables
Wed, May 9, 8:05 AM
kparzysz added a comment to D46620: Fix side effect in debug code.

The whole loop is an assert. The only purpose of it is to verify the ID vs. its position in the loop. Maybe having for (unsigned i = ...; i != e; ++i) instead would be cleaner, but I think it's ok as is. I don't have a problem with changing it either, but I wouldn't say it's necessary.

Wed, May 9, 6:52 AM

Mon, May 7

kparzysz committed rL331653: [Hexagon] Move clamping of extended operands directly to MC code emitter.
[Hexagon] Move clamping of extended operands directly to MC code emitter
Mon, May 7, 10:39 AM

Fri, May 4

kparzysz added inline comments to D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.
Fri, May 4, 12:51 PM
kparzysz added inline comments to D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.
Fri, May 4, 12:02 PM
kparzysz updated the diff for D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.
  1. Removed incorrect (leftover from initial incorrect diff) Hexagon tests.
  2. Enable simplification on AArch64.
  3. Add testcases for AArch64 and Hexagon.
Fri, May 4, 11:24 AM
kparzysz added a comment to D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.

I don't know what AArch64 needs. I can enable it there too.

Fri, May 4, 10:11 AM
kparzysz committed rL331528: [Hexagon] Remove leftover debugging code after r331527.
[Hexagon] Remove leftover debugging code after r331527
Fri, May 4, 8:11 AM
kparzysz committed rL331527: [Hexagon] Handle non-immediate constants in HexagonSplitDouble.
[Hexagon] Handle non-immediate constants in HexagonSplitDouble
Fri, May 4, 8:08 AM
kparzysz committed rL331518: [Hexagon] Skip reserved physical registers when updating liveness.
[Hexagon] Skip reserved physical registers when updating liveness
Fri, May 4, 7:03 AM

Thu, May 3

kparzysz accepted D46364: Add basic compiler-rt builtins support for hexagon.

LGTM

Thu, May 3, 1:36 PM
kparzysz added a comment to D46193: [LSR] Skip LSR if the cost of input is cheaper than LSR's solution.

I have wanted something like this! Thanks for doing it.

Thu, May 3, 1:35 PM
kparzysz requested changes to D46364: Add basic compiler-rt builtins support for hexagon.
Thu, May 3, 12:53 PM
kparzysz added inline comments to D46364: Add basic compiler-rt builtins support for hexagon.
Thu, May 3, 11:52 AM
kparzysz added a reviewer for D46396: Optionally simplify basic blocks introduced by AtomicExpandPass: jfb.
Thu, May 3, 11:46 AM
kparzysz created D46396: Optionally simplify basic blocks introduced by AtomicExpandPass.
Thu, May 3, 10:27 AM

Wed, May 2

kparzysz committed rL331376: Add assertion to padding size calculation, NFC.
Add assertion to padding size calculation, NFC
Wed, May 2, 10:24 AM

Tue, May 1

kparzysz accepted D45986: [AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare.

I think we should recognize as much as we can out of the common idioms, and this is one of them. Looks good to me.

Tue, May 1, 7:05 AM
kparzysz added a comment to D45986: [AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare.

This recognizes something like "bitmask-any", where the code checks if any of the bits of V indicated by the mask C' is set. It looks like by replacing or with and you would get the corresponding "bitmask-all". Would it be worthwhile to add it? I don't have a use case, but the symmetry seems somewhat compelling.

Tue, May 1, 6:01 AM
kparzysz added a comment to D45731: [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case.

I haven't seen anything. For reference, I mentioned ctpop/ctlz in the context of D45986 too, so I think we should do something to organize these optimizations, but I'm not sure what's best.
That said, I think this patch is fine as an enhancement of the existing code, so LGTM.

Tue, May 1, 5:40 AM

Mon, Apr 30

kparzysz committed rL331219: [LivePhysRegs] Remove registers clobbered by regmasks from the live set.
[LivePhysRegs] Remove registers clobbered by regmasks from the live set
Mon, Apr 30, 12:44 PM

Apr 20 2018

kparzysz committed rL330472: [Hexagon] hexagon-autohvx was left on again.
[Hexagon] hexagon-autohvx was left on again
Apr 20 2018, 12:49 PM
kparzysz committed rL330471: [Hexagon] Improve HVX instruction selection (bitcast, vsplat).
[Hexagon] Improve HVX instruction selection (bitcast, vsplat)
Apr 20 2018, 12:43 PM
kparzysz committed rL330468: [Hexagon] Skip fixed-stack indexes in HexagonConstExtenders.
[Hexagon] Skip fixed-stack indexes in HexagonConstExtenders
Apr 20 2018, 12:10 PM

Apr 19 2018

kparzysz added a comment to D45731: [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case.

@opaparo Please commandeer this revision, I only took over to restore the diff that got accidentally overwritten.

Apr 19 2018, 10:50 AM
kparzysz updated the diff for D45731: [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case.

Hopefully the right diff was restored after the commit mismatch fiasco.

Apr 19 2018, 10:50 AM
kparzysz commandeered D45731: [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case.

I screwed it up completely. Let me try to fix it.

Apr 19 2018, 10:41 AM
kparzysz closed D45819: If conversion update.

Committed in https://reviews.llvm.org/rL330345.

Apr 19 2018, 10:36 AM
kparzysz reopened D45731: [InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case.

Sorry, I pasted a wrong revision in a commit message.

Apr 19 2018, 10:35 AM
kparzysz committed rL330345: [if-converter] Handle BBs that terminate in ret during diamond conversion.
[if-converter] Handle BBs that terminate in ret during diamond conversion
Apr 19 2018, 10:30 AM
This revision was not accepted when it landed; it landed in state Needs Review.
Apr 19 2018, 10:29 AM
kparzysz committed rL330344: [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTOR.
[Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTOR
Apr 19 2018, 10:15 AM
kparzysz added a comment to D45218: [if-converter] Handle BB that terminate in ret during diamond conversion.

I encountered a related problem in Hexagon code and I amended the patch to handle that as well. I couldn't upload it to this review, so I created a new one: D45819, but it's really meant to be an extension of this fix.

Apr 19 2018, 8:17 AM
kparzysz created D45819: If conversion update.
Apr 19 2018, 8:15 AM
kparzysz committed rL330333: [Hexagon] Generate code for vector bswap intrinsics.
[Hexagon] Generate code for vector bswap intrinsics
Apr 19 2018, 7:50 AM
kparzysz committed rL330330: [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops.
[Hexagon] Add/fix patterns for 32/64-bit vector compares and logical ops
Apr 19 2018, 7:27 AM

Apr 17 2018

kparzysz added inline comments to D35688: More extendable LaneBitmask.
Apr 17 2018, 11:10 AM
kparzysz committed rL330191: [Hexagon] Do not merge initializers for stack and non-stack expressions.
[Hexagon] Do not merge initializers for stack and non-stack expressions
Apr 17 2018, 8:26 AM

Apr 16 2018

kparzysz committed rC330150: [Hexagon] Emit a warning when -fvectorize is given without -mhvx.
[Hexagon] Emit a warning when -fvectorize is given without -mhvx
Apr 16 2018, 12:14 PM
kparzysz committed rL330150: [Hexagon] Emit a warning when -fvectorize is given without -mhvx.
[Hexagon] Emit a warning when -fvectorize is given without -mhvx
Apr 16 2018, 12:14 PM
kparzysz committed rL330139: [Hexagon] Turn off flag enabling auto-vectorization.
[Hexagon] Turn off flag enabling auto-vectorization
Apr 16 2018, 10:38 AM
kparzysz updated the diff for D35688: More extendable LaneBitmask.
Apr 16 2018, 10:06 AM

Apr 13 2018

kparzysz committed rL330065: [Hexagon] Initial instruction cost model for auto-vectorization.
[Hexagon] Initial instruction cost model for auto-vectorization
Apr 13 2018, 1:51 PM
kparzysz committed rL330062: [LV] Introduce TTI::getMinimumVF.
[LV] Introduce TTI::getMinimumVF
Apr 13 2018, 1:19 PM
This revision was not accepted when it landed; it landed in state Needs Review.
Apr 13 2018, 1:19 PM
kparzysz added a comment to D45271: [LV] Introduce TTI::getMinimumVF.

Since you're ok with the vectorizer change, I'll commit this. If someone has concerns regarding the TTI interface, I'll address it post-commit.

Apr 13 2018, 1:09 PM
kparzysz added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

I've firstly implemented like that but I've got comment that it might be better to implement it through table description instead of using multiple switch-case constructions for every register move instruction.

Apr 13 2018, 6:47 AM
kparzysz added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

There is already such hook for some mips and arm instructions like that.

Apr 13 2018, 6:19 AM

Apr 12 2018

kparzysz added a comment to D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'.

Wouldn't it be better to have this as a TII hook? There are instructions like "or reg, 0" or "add reg, 0" that are effectively copies, but only with specific operands.

Apr 12 2018, 2:27 PM
kparzysz committed rL329923: [Hexagon] Enable auto-vectorization only when -fvectorize was given.
[Hexagon] Enable auto-vectorization only when -fvectorize was given
Apr 12 2018, 9:28 AM
kparzysz committed rC329923: [Hexagon] Enable auto-vectorization only when -fvectorize was given.
[Hexagon] Enable auto-vectorization only when -fvectorize was given
Apr 12 2018, 9:28 AM
kparzysz committed rL329915: [Pipeliner] Use std::stable_sort when ordering NodeSets.
[Pipeliner] Use std::stable_sort when ordering NodeSets
Apr 12 2018, 8:14 AM

Apr 10 2018

kparzysz added a comment to D45271: [LV] Introduce TTI::getMinimumVF.

Ping.

Apr 10 2018, 10:39 AM
kparzysz committed rL329719: [CodeGen] Fix printing bundles in MIR output.
[CodeGen] Fix printing bundles in MIR output
Apr 10 2018, 9:50 AM

Apr 9 2018

kparzysz added a comment to D45173: [InstCombine] Recognize idioms for ctpop and ctlz.

To point the obvious, if one takes one of these tests, runs those through instcombine
and then runs aggressiveinstcombine, chances are they will no longer be matched...
(Well, the main point being, any non-expected, slightly different pattern, that i would normally expected to be slightly canonicalized beforehand),

Apr 9 2018, 5:41 AM
kparzysz added a comment to D45173: [InstCombine] Recognize idioms for ctpop and ctlz.

To add to that, i think you should be able to get rid of at least some of the pain of detection
of when instcombine got smarter and these folds no longer match, by adding kind-of end-to-end optimization tests.

Apr 9 2018, 5:35 AM

Apr 6 2018

kparzysz committed rL329439: [Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions.
[Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions
Apr 6 2018, 11:22 AM
kparzysz committed rL329437: [Hexagon] Prevent a stall across zero-latency instructions in a packet.
[Hexagon] Prevent a stall across zero-latency instructions in a packet
Apr 6 2018, 11:16 AM
kparzysz committed rL329436: [Hexagon] Remove duplicated code, NFC.
[Hexagon] Remove duplicated code, NFC
Apr 6 2018, 11:14 AM
kparzysz committed rL329434: [Hexagon] Handle subregisters when calculating iteration count in HW loops.
[Hexagon] Handle subregisters when calculating iteration count in HW loops
Apr 6 2018, 10:55 AM
kparzysz added a comment to D45173: [InstCombine] Recognize idioms for ctpop and ctlz.

Moving aggressive instcombine pass to before the regular instcombine, just to demonstrate the idea.

I'm curious to know, while this does sidestep the issue of having to adapt to the instcombine/earlier passes being smarter, how does this not either [...]

Apr 6 2018, 10:02 AM
kparzysz added a comment to D45173: [InstCombine] Recognize idioms for ctpop and ctlz.

Would a change like the one in PassManagerBuilder.cpp be acceptable? There may be some work to make sure that the pre-existing components of the aggressive instcombine still apply, but I'm wondering if this direction is something we could agree on.

Apr 6 2018, 9:35 AM
kparzysz updated the diff for D45173: [InstCombine] Recognize idioms for ctpop and ctlz.

Moving aggressive instcombine pass to before the regular instcombine, just to demonstrate the idea.

Apr 6 2018, 9:33 AM
kparzysz added a comment to D45173: [InstCombine] Recognize idioms for ctpop and ctlz.

As you've noted, running "instcombine" before your pattern-recognition code is going to be a constant source of trouble, because it isn't a fixed set of transforms, and it runs very early in the pass pipeline. So either you run your pattern-recognition before instcombine, or you add some tests to the LLVM regression tests which will break if a new transform breaks your pattern-recognition, and hope for the best. I guess it might help a bit if we came up with some restricted criteria for allowed transforms in instcombine, and put the rest into aggressive-instcombine. But we're never going to completely freeze the optimization pipeline, so there's fundamentally some maintenance burden.

Apr 6 2018, 9:31 AM
kparzysz committed rL329394: [Hexagon] Remove default values from lambda parameters.
[Hexagon] Remove default values from lambda parameters
Apr 6 2018, 6:56 AM
kparzysz committed rC329394: [Hexagon] Remove default values from lambda parameters.
[Hexagon] Remove default values from lambda parameters
Apr 6 2018, 6:56 AM

Apr 5 2018

kparzysz added inline comments to D45271: [LV] Introduce TTI::getMinimumVF.
Apr 5 2018, 8:11 AM