kparzysz (Krzysztof Parzyszek)
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Apr 21 2014, 4:27 PM (178 w, 4 d)

Recent Activity

Yesterday

kparzysz committed rL314004: [TableGen] Replace InfoByHwMode::getAsString with writeToStream.
[TableGen] Replace InfoByHwMode::getAsString with writeToStream
Fri, Sep 22, 11:31 AM
kparzysz committed rL313990: Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream".
Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"
Fri, Sep 22, 9:20 AM
kparzysz committed rL313989: [TableGen] Replace InfoByHwMode::getAsString with writeToStream.
[TableGen] Replace InfoByHwMode::getAsString with writeToStream
Fri, Sep 22, 9:08 AM
kparzysz accepted D38174: [TableGen] Return StringRef from ValueTypeByHwMode::getMVTName.

This is good regardless of any future changes to replace getAsString.

Fri, Sep 22, 6:21 AM

Wed, Sep 20

kparzysz accepted D37957: [TableGen] Some simple optimizations to TableGen execution time.

LGTM with a few nitpicks (inline comments). Also, could you commit the DenseSet/tombstone changes in a separate patch?

Wed, Sep 20, 10:41 AM

Tue, Sep 19

kparzysz added inline comments to D37957: [TableGen] Some simple optimizations to TableGen execution time.
Tue, Sep 19, 2:46 PM
kparzysz added a comment to D37957: [TableGen] Some simple optimizations to TableGen execution time.

Can you apply this patch Krzysztof and see if you can figure out what the right thing to do is with the empty StringRef?

Tue, Sep 19, 2:41 PM
kparzysz abandoned D31958: [Hexagon] Switch to parametrized register classes for HVX.

Committed in https://reviews.llvm.org/rL313362.

Tue, Sep 19, 12:58 PM
kparzysz added a comment to D37957: [TableGen] Some simple optimizations to TableGen execution time.

Could you rebase this patch?

Tue, Sep 19, 12:53 PM
kparzysz accepted D37966: [TableGen] Generate formatted DAGISelEmitter without relying on formatted_raw_ostream..

On my machine, in the debug build of TableGen, the time for X86 -gen-dag-isel went down from 61s to 52s.

Tue, Sep 19, 12:29 PM
kparzysz committed rL313660: Recommit r313647 now that GCC seems to accept the offering.
Recommit r313647 now that GCC seems to accept the offering
Tue, Sep 19, 11:44 AM
kparzysz committed rL313651: Revert "Improve TableGen performance of -gen-dag-isel (motivated by X86….
Revert "Improve TableGen performance of -gen-dag-isel (motivated by X86…
Tue, Sep 19, 10:56 AM
kparzysz committed rL313649: Move "(void)variable" closer to the assertion that uses it, NFC.
Move "(void)variable" closer to the assertion that uses it, NFC
Tue, Sep 19, 10:49 AM
kparzysz committed rL313647: Improve TableGen performance of -gen-dag-isel (motivated by X86 backend).
Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)
Tue, Sep 19, 10:34 AM

Fri, Sep 15

kparzysz committed rL313380: Fix selecting legal types in TypeInfer::getLegalTypes.
Fix selecting legal types in TypeInfer::getLegalTypes
Fri, Sep 15, 11:59 AM
kparzysz committed rL313362: [Hexagon] Switch to parameterized register classes for HVX.
[Hexagon] Switch to parameterized register classes for HVX
Fri, Sep 15, 8:47 AM

Thu, Sep 14

kparzysz added inline comments to D37866: [LateJumpThreading] Enable LateJumpThreading right before CGP..
Thu, Sep 14, 2:12 PM
kparzysz committed rL313295: Subtarget support for parameterized register class information.
Subtarget support for parameterized register class information
Thu, Sep 14, 1:45 PM
kparzysz closed D31959: Subtarget support for parametrized register class information by committing rL313295: Subtarget support for parameterized register class information.
Thu, Sep 14, 1:45 PM
kparzysz committed rL313273: Silence warning about unused variable in release build.
Silence warning about unused variable in release build
Thu, Sep 14, 10:09 AM
kparzysz committed rL313271: TableGen support for parameterized register class information.
TableGen support for parameterized register class information
Thu, Sep 14, 9:59 AM
kparzysz closed D31951: TableGen support for parameterized register class information by committing rL313271: TableGen support for parameterized register class information.
Thu, Sep 14, 9:59 AM
kparzysz committed rL313268: [IfConversion] More simple, correct dead/kill liveness handling.
[IfConversion] More simple, correct dead/kill liveness handling
Thu, Sep 14, 8:56 AM
kparzysz closed D37611: [IfConversion] More simple, correct dead/kill liveness handling by committing rL313268: [IfConversion] More simple, correct dead/kill liveness handling.
Thu, Sep 14, 8:56 AM
kparzysz added inline comments to D37816: Experimental late jump threading pass.
Thu, Sep 14, 8:36 AM
kparzysz added a comment to D36404: Disable jump threading into loop headers.

On another note, this patch was meant to prevent adding extra branches to the header from within the loop. Branches to the header that come from outside of the loop should be fine. In other words, it should be ok to refine the check to only disable jump threading when any of the PredBBs is dominated by the header (SuccBB).

Thu, Sep 14, 8:25 AM
kparzysz added inline comments to D37816: Experimental late jump threading pass.
Thu, Sep 14, 8:13 AM
kparzysz added a comment to D37611: [IfConversion] More simple, correct dead/kill liveness handling.

I found and fixed the reason our randomized tests didn't run cleanly. It was essentially that stepBackwards removed defined regs from the set even if the instruction was predicated.

Thu, Sep 14, 7:46 AM
kparzysz updated the diff for D37816: Experimental late jump threading pass.

Reduced code duplication between the legacy (old PM) passes.

Thu, Sep 14, 7:39 AM
kparzysz committed rL313257: [Hexagon] Make getMemAccessSize return size in bytes.
[Hexagon] Make getMemAccessSize return size in bytes
Thu, Sep 14, 5:08 AM

Wed, Sep 13

kparzysz added a comment to D36404: Disable jump threading into loop headers.

Late jump threading is in D37816.

Wed, Sep 13, 10:09 AM
kparzysz created D37816: Experimental late jump threading pass.
Wed, Sep 13, 10:08 AM
kparzysz added a comment to D36404: Disable jump threading into loop headers.

I'll come up with a late jump threading pass that you can try plugging in, in addition to having the existing one.

Wed, Sep 13, 9:08 AM
kparzysz added a comment to D36404: Disable jump threading into loop headers.

Have you tried it? Changing jump threading to have early/late versions is trivial, the question is when should the late one run, and if that would help in the first place.

Wed, Sep 13, 8:18 AM
kparzysz added a comment to D37611: [IfConversion] More simple, correct dead/kill liveness handling.

Good news everyone... The Hexagon test suite passed.

Wed, Sep 13, 7:08 AM
kparzysz added a comment to D37611: [IfConversion] More simple, correct dead/kill liveness handling.

To add to my previous comment---there is a plan to eliminate kill flags in the future (as I was told), so passes the rely on those will eventually need to be modified. If it's the presence of kill flags on predicated instructions (and tied uses) that is causing problems, maybe it would be a good thing to address that in the passes that are exploiting that to generate wrong code. It would imply more work, so I guess the answer depends on how much more work it would be.

Wed, Sep 13, 6:53 AM
kparzysz added a comment to D37611: [IfConversion] More simple, correct dead/kill liveness handling.

I just started a test run on a Hexagon suite, but I wonder if the anti-dependence breaker could be a problem. This is regarding the question of whether the implicit uses on predicated instructions should be killed or not. BTW, the same argument applies to tied uses. Even though the live ranges seem to end/start at that instruction, the register cannot be renamed in only one of them. This differentiates those instructions from a case of unrelated use/def coincidentally using the same register (as was in the example: r0 = add r0, r1).

Wed, Sep 13, 6:48 AM

Tue, Sep 12

kparzysz updated the diff for D31951: TableGen support for parameterized register class information.

Addressed Simon's comments.

Tue, Sep 12, 11:14 AM
kparzysz added inline comments to D31951: TableGen support for parameterized register class information.
Tue, Sep 12, 11:11 AM
kparzysz committed rL313038: Remove ancient, commented out code from TableGen, NFC.
Remove ancient, commented out code from TableGen, NFC
Tue, Sep 12, 8:49 AM
kparzysz committed rL313037: Formatting changes, add LLVM_DUMP_METHOD to a dump function, NFC.
Formatting changes, add LLVM_DUMP_METHOD to a dump function, NFC
Tue, Sep 12, 8:33 AM
kparzysz committed rL313030: Fix a couple of comments, NFC.
Fix a couple of comments, NFC
Tue, Sep 12, 7:12 AM
kparzysz accepted D37556: [ARC] Prepare the implementation of relocation for lld.
Tue, Sep 12, 5:32 AM

Mon, Sep 11

kparzysz added inline comments to D37556: [ARC] Prepare the implementation of relocation for lld.
Mon, Sep 11, 8:05 AM
kparzysz added inline comments to D37611: [IfConversion] More simple, correct dead/kill liveness handling.
Mon, Sep 11, 7:59 AM
kparzysz added inline comments to D29934: [RISCV 12/n] Codegen support for memory operations.
Mon, Sep 11, 7:49 AM
kparzysz accepted D29936: [RISCV 14/n] Support for function calls.
Mon, Sep 11, 7:28 AM
kparzysz added inline comments to D29938: [RISCV 16/n] Support and tests for a variety of additional LLVM IR constructs.
Mon, Sep 11, 7:17 AM

Fri, Sep 8

kparzysz accepted D37556: [ARC] Prepare the implementation of relocation for lld.

If you decide that the YAML file doesn't need to be modified in this patch, the rest LGTM.

Fri, Sep 8, 11:24 AM
kparzysz added a comment to D37556: [ARC] Prepare the implementation of relocation for lld.

Should you also change lib/ObjectYAML/ELFYAML.cpp?

Fri, Sep 8, 10:52 AM
kparzysz committed rL312797: Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits.
Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits
Fri, Sep 8, 9:31 AM
kparzysz closed D37600: Preserve existing registers when adding pristines to LivePhysRegs by committing rL312797: Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits.
Fri, Sep 8, 9:31 AM
kparzysz added a comment to D37611: [IfConversion] More simple, correct dead/kill liveness handling.

This seems like a reasonable way of handling it, but I'd like Matthias and Kyle to comment on this as well.

Fri, Sep 8, 9:30 AM
kparzysz added inline comments to D37611: [IfConversion] More simple, correct dead/kill liveness handling.
Fri, Sep 8, 9:21 AM
kparzysz updated the diff for D37600: Preserve existing registers when adding pristines to LivePhysRegs.
  • Kept the original code for the case of empty set.
  • Added the same fix to LiveRegUnits.
Fri, Sep 8, 7:57 AM

Thu, Sep 7

kparzysz created D37600: Preserve existing registers when adding pristines to LivePhysRegs.
Thu, Sep 7, 4:11 PM
kparzysz abandoned D36415: Insert IMPLICIT_DEFS for undef uses in tail merging.

Replaced by D37034.

Thu, Sep 7, 7:48 AM
kparzysz added inline comments to D29933: [RISCV 11/n] Initial codegen support for ALU operations.
Thu, Sep 7, 7:46 AM
kparzysz added a comment to D37230: Set hasSideEffects=0 for TargetOpcode::BUNDLE.

As a side note, in case anybody is wondering: the differences in the generated code come from the post-RA scheduler, which can do more reordering of instructions relative to bundles.

Thu, Sep 7, 7:14 AM
kparzysz added inline comments to D29933: [RISCV 11/n] Initial codegen support for ALU operations.
Thu, Sep 7, 6:12 AM

Wed, Sep 6

kparzysz committed rL312664: Disable jump threading into loop headers.
Disable jump threading into loop headers
Wed, Sep 6, 12:38 PM
kparzysz closed D36404: Disable jump threading into loop headers by committing rL312664: Disable jump threading into loop headers.
Wed, Sep 6, 12:38 PM
kparzysz updated the diff for D36404: Disable jump threading into loop headers.

Changed the code to simply disable jump threading into loop headers.

Wed, Sep 6, 11:38 AM
kparzysz committed rL312654: [IfConversion] Remove kill flags from common instructions as well.
[IfConversion] Remove kill flags from common instructions as well
Wed, Sep 6, 10:58 AM
kparzysz committed rL312644: [Hexagon] Add option to generate calls to "abort" for "unreachable".
[Hexagon] Add option to generate calls to "abort" for "unreachable"
Wed, Sep 6, 9:24 AM
kparzysz accepted D37034: Insert IMPLICIT_DEFS for undef uses in tail merging.

This is great. Thanks!

Wed, Sep 6, 9:19 AM

Tue, Sep 5

kparzysz accepted D37406: [TailCall] Allow llvm.memcpy/memset/memmove to be tail calls when parent function return the intrinsics's first argument.
Tue, Sep 5, 12:23 PM

Fri, Sep 1

kparzysz accepted D37356: LiveIntervalAnalysis: Fix alias regunit reserved definition.

On a somewhat unrelated note---is it valid on AArch64 to reserve W1_W2 without reserving W1 and W2? If so, it would lead to a situation where a reserved register does not contain any reserved units. If not, it would require one or both of W0_W1 and W2_W3 to also be reserved.

Fri, Sep 1, 10:38 AM

Thu, Aug 31

kparzysz added inline comments to D37356: LiveIntervalAnalysis: Fix alias regunit reserved definition.
Thu, Aug 31, 2:30 PM
kparzysz added a comment to D37034: Insert IMPLICIT_DEFS for undef uses in tail merging.

Are there any new developments?

Thu, Aug 31, 1:28 PM
kparzysz added a comment to D36331: Add ARC backend.

Can this review be closed?

Thu, Aug 31, 12:45 PM

Tue, Aug 29

kparzysz updated the summary of D31951: TableGen support for parameterized register class information.
Tue, Aug 29, 7:18 AM
kparzysz updated the diff for D31951: TableGen support for parameterized register class information.

Rebased.

Tue, Aug 29, 6:11 AM

Mon, Aug 28

kparzysz committed rL311901: [Hexagon] Check for potential bank conflicts in post-RA scheduling.
[Hexagon] Check for potential bank conflicts in post-RA scheduling
Mon, Aug 28, 11:37 AM
kparzysz committed rL311895: [Hexagon] Break up DAG mutations into separate classes, move to subtarget.
[Hexagon] Break up DAG mutations into separate classes, move to subtarget
Mon, Aug 28, 9:25 AM
kparzysz committed rL311894: [Hexagon] Move pre-RA DAG mutations to scheduler constructor.
[Hexagon] Move pre-RA DAG mutations to scheduler constructor
Mon, Aug 28, 8:54 AM

Fri, Aug 25

kparzysz added a comment to D36404: Disable jump threading into loop headers.

Any thoughts on this?

Fri, Aug 25, 8:14 AM

Thu, Aug 24

kparzysz committed rL311690: [Hexagon] Set access size for vector pseudo loads/stores.
[Hexagon] Set access size for vector pseudo loads/stores
Thu, Aug 24, 12:20 PM
kparzysz added inline comments to D37052: Add default address space for functions to the data layout (1/4).
Thu, Aug 24, 9:18 AM
kparzysz added a comment to D37097: Set hasSideEffects=0 for PHI and fix passes relying isSafeToMove/hasUnmodeledSideEffects being true for PHI.

The Hexagon changes look good to me.

Thu, Aug 24, 9:08 AM

Aug 24 2017

kparzysz committed rL311650: [Hexagon] Generate correct runtime check when recognizing memmove.
[Hexagon] Generate correct runtime check when recognizing memmove
Aug 24 2017, 5:02 AM

Aug 23 2017

kparzysz accepted D36331: Add ARC backend.
Aug 23 2017, 1:42 PM
kparzysz added inline comments to D37052: Add default address space for functions to the data layout (1/4).
Aug 23 2017, 10:49 AM
kparzysz added inline comments to D37034: Insert IMPLICIT_DEFS for undef uses in tail merging.
Aug 23 2017, 10:17 AM
kparzysz added inline comments to D37034: Insert IMPLICIT_DEFS for undef uses in tail merging.
Aug 23 2017, 10:02 AM

Aug 22 2017

kparzysz added a comment to D36415: Insert IMPLICIT_DEFS for undef uses in tail merging.

Ping.

Aug 22 2017, 5:41 AM

Aug 21 2017

kparzysz added a comment to D36911: TableGen: Add --gen-register-info-debug-dump.

Looks good to me. One thing I'm wondering about is if this needs to be a separate TableGen "target". Could it be under a debug flag used with -gen-register-info?

Aug 21 2017, 12:27 PM

Aug 18 2017

kparzysz added a comment to D36331: Add ARC backend.

Please make sure that the copyright notices are ok with everyone. Other files don't have them and I don't know whether that works with the current license/legal status.

Aug 18 2017, 10:28 AM
kparzysz accepted D36331: Add ARC backend.
Aug 18 2017, 10:24 AM

Aug 17 2017

kparzysz added a comment to D36331: Add ARC backend.

I found a few minor things, with those changes it looks good to go to me.

Aug 17 2017, 12:11 PM
kparzysz added a comment to D36404: Disable jump threading into loop headers.

Ping.

Aug 17 2017, 10:05 AM

Aug 16 2017

kparzysz added inline comments to D36331: Add ARC backend.
Aug 16 2017, 12:09 PM
kparzysz added a comment to D36712: Emit section information for extern variables.

The problem is that the mismatch between sections does not have to lead to any undesirable behavior. Whether it does or not depends on a particular case. I think we should be consistent though---if we decide that a mismatch between the section for a declaration and the section for a definition leads to an undefined behavior, then it should be so regardless of whether the sections were given explicitly or inferred.

Aug 16 2017, 9:03 AM
kparzysz added a comment to D36712: Emit section information for extern variables.

Does this result in unexpected behavior though? Won't this just result in the global being defined in the specified section?

Aug 16 2017, 8:45 AM

Aug 15 2017

kparzysz added a comment to D36712: Emit section information for extern variables.

I can't see how "undefined behavior" could possibly be the right answer in that case. Every definition has to end up in some section eventually, and in many cases we don't know what section that will be when a global is declared. (For example, we put constants into different sections depending on the contents of the initializer.)

Aug 15 2017, 1:00 PM
kparzysz added inline comments to D36712: Emit section information for extern variables.
Aug 15 2017, 7:24 AM

Aug 14 2017

kparzysz added a comment to D36415: Insert IMPLICIT_DEFS for undef uses in tail merging.

Ping.

Aug 14 2017, 9:36 AM

Aug 11 2017

kparzysz updated the diff for D31951: TableGen support for parameterized register class information.

Changed the type/variable names to something I find more accurate.

Aug 11 2017, 1:55 PM
kparzysz added a comment to D31951: TableGen support for parameterized register class information.

Intrinsics are not handled here because their types are exposed to outside of TableGen, specifically to the front-end. We have two sets of HVX intrinsics on Hexagon, one for 64-byte and one for 128-byte mode, and they are not going away. The rest of clang/LLVM would need to be changed to deal with that. I've tried to handle intrinsics too, but quickly realized that it wouldn't be possible to have that done within the scope of TableGen.

Aug 11 2017, 1:53 PM

Aug 10 2017

kparzysz added a comment to D36160: Add "Restored" flag to CalleeSavedInfo.

Added comments as requested by Matthias.

Aug 10 2017, 9:20 AM