kparzysz (Krzysztof Parzyszek)
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User Since
Apr 21 2014, 4:27 PM (230 w, 6 d)

Recent Activity

Fri, Sep 21

kparzysz committed rL342751: [Hexagon] Avoid functions with exception handling in HexagonConstExtenders.
[Hexagon] Avoid functions with exception handling in HexagonConstExtenders
Fri, Sep 21, 10:44 AM

Thu, Sep 20

kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

I've looked into this and there is no way to distinguish the case of hh (no warning) and ll (emit a warning). They are both equivalent: a user-defined composition vs. pre-existing subreg.

Thu, Sep 20, 8:21 AM

Wed, Sep 19

kparzysz accepted D52237: [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs.
Wed, Sep 19, 10:03 AM

Tue, Sep 18

kparzysz committed rL342492: [PostRASink] Make sure to remove subregisters from live-ins as well.
[PostRASink] Make sure to remove subregisters from live-ins as well
Tue, Sep 18, 9:12 AM
kparzysz added a comment to D52237: [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs.

In general, looking at a single instruction is not sufficient to tell whether a given register becomes dead or not, so I wouldn't worry about the limitation you mentioned. Cases that we can reliably handle are (sub)ranges corresponding to the parts of the register that is given in the operand (i.e. the entire register if there is no subregister).

Tue, Sep 18, 9:04 AM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

The conflict between user-defined and inferred compositions causes a warning in the SystemZ build:

warning: SubRegIndex SystemZ::subreg_h64 and SystemZ::subreg_h32 compose ambiguously as SystemZ::subreg_hh32 or SystemZ::subreg_h32
Tue, Sep 18, 5:33 AM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Ping.

Tue, Sep 18, 5:27 AM

Wed, Sep 12

kparzysz committed rL342091: [Hexagon] Use shuffles when lowering "gather" shufflevectors.
[Hexagon] Use shuffles when lowering "gather" shufflevectors
Wed, Sep 12, 3:16 PM
kparzysz committed rL342090: [Hexagon] Improve the selection algorithm in scalarizeShuffle.
[Hexagon] Improve the selection algorithm in scalarizeShuffle
Wed, Sep 12, 3:12 PM
kparzysz committed rL342079: [Hexagon] Use legalized type for extracted elements in scalarizeShuffle.
[Hexagon] Use legalized type for extracted elements in scalarizeShuffle
Wed, Sep 12, 2:00 PM

Tue, Sep 11

kparzysz added inline comments to D50944: [Hexagon] [Test] Remove undef and infinite loop from test.
Tue, Sep 11, 6:25 AM

Mon, Sep 10

kparzysz committed rL341851: [Hexagon] Split large offsets into properly aligned addends.
[Hexagon] Split large offsets into properly aligned addends
Mon, Sep 10, 11:50 AM

Wed, Sep 5

kparzysz committed rL341478: [Hexagon] Ignore unnamed globals in HexagonConstExtenders.
[Hexagon] Ignore unnamed globals in HexagonConstExtenders
Wed, Sep 5, 8:56 AM
kparzysz added inline comments to D51474: Consider CSRs in computeRegisterLiveness.
Wed, Sep 5, 8:17 AM

Tue, Sep 4

kparzysz committed rL341409: [Hexagon] Don't packetize new-value stores with any other stores.
[Hexagon] Don't packetize new-value stores with any other stores
Tue, Sep 4, 2:09 PM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Ping.

Tue, Sep 4, 9:18 AM

Fri, Aug 31

kparzysz committed rL341264: [Hexagon] Don't access non-existent instructions.
[Hexagon] Don't access non-existent instructions
Fri, Aug 31, 3:11 PM

Thu, Aug 30

kparzysz committed rL341137: [Hexagon] Check validity of register class when generating bitsplit.
[Hexagon] Check validity of register class when generating bitsplit
Thu, Aug 30, 3:27 PM
kparzysz added a comment to D51058: [zorg] Pass environment to getPollyBuildFactory and getAOSPBuildFactory.

Ping.

Thu, Aug 30, 10:48 AM

Tue, Aug 28

kparzysz accepted D51035: [TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching predicates.
Tue, Aug 28, 6:37 AM

Mon, Aug 27

kparzysz added a comment to D51035: [TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching predicates.

It should be possible to move this loop out of the nest and only have it iterate over the preexisting patterns. Could you see if that generates different .inc files (it shouldn't)?

Mon, Aug 27, 1:10 PM

Aug 24 2018

kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Ping.

Aug 24 2018, 10:44 AM
kparzysz committed rC340622: [Hexagon] Remove unneeded strings from builtin definitions, NFC.
[Hexagon] Remove unneeded strings from builtin definitions, NFC
Aug 24 2018, 10:15 AM
kparzysz committed rL340622: [Hexagon] Remove unneeded strings from builtin definitions, NFC.
[Hexagon] Remove unneeded strings from builtin definitions, NFC
Aug 24 2018, 10:14 AM

Aug 23 2018

kparzysz abandoned D24631: [RFC] Implement variable-width register classes, step 1: API changes.

Already implemented.

Aug 23 2018, 9:16 AM
kparzysz abandoned D50648: [SystemZ] Enable trackSubRegLiveness.

The fixes have been committed individually.

Aug 23 2018, 9:15 AM
kparzysz accepted D50637: [CodeGen] Set FrameSetup/FrameDestroy on BUNDLE instructions.
Aug 23 2018, 7:13 AM

Aug 22 2018

kparzysz committed rL340447: [Hexagon] Enable interleaving in loop vectorizer.
[Hexagon] Enable interleaving in loop vectorizer
Aug 22 2018, 1:15 PM

Aug 21 2018

kparzysz created D51058: [zorg] Pass environment to getPollyBuildFactory and getAOSPBuildFactory.
Aug 21 2018, 12:44 PM
kparzysz committed rL340318: [RegisterCoalscer] Manually remove leftover segments when commuting def.
[RegisterCoalscer] Manually remove leftover segments when commuting def
Aug 21 2018, 12:02 PM

Aug 20 2018

kparzysz committed rL340213: [zorg] Update clang on Hexagon builders to 6.0.1.
[zorg] Update clang on Hexagon builders to 6.0.1
Aug 20 2018, 2:03 PM
kparzysz committed rL340208: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.
Consistently use MemoryLocation::UnknownSize to indicate unknown access size
Aug 20 2018, 1:38 PM
kparzysz closed D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.
Aug 20 2018, 1:38 PM
kparzysz added a comment to D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.

The practical application of this is to indicate aliasing with a given memory object, but without specifying exactly which part of the object is accessed (since it may be unknown). Dropping memory operands altogether will alias the operation with all other objects, so it will be correct, but overly conservative.

Aug 20 2018, 10:19 AM
kparzysz created D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.
Aug 20 2018, 10:14 AM
kparzysz accepted D50944: [Hexagon] [Test] Remove undef and infinite loop from test.
Aug 20 2018, 5:38 AM

Aug 17 2018

kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

Yes, I do have one. I'll post it on Monday.

Aug 17 2018, 2:58 PM
kparzysz committed rL340081: [Hexagon] Remove unused functions from HexagonInstPrinter, NFC.
[Hexagon] Remove unused functions from HexagonInstPrinter, NFC
Aug 17 2018, 2:13 PM
kparzysz added a comment to D50903: [TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode.

Thanks for finding all these things!

Aug 17 2018, 8:38 AM
kparzysz accepted D50903: [TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode.
Aug 17 2018, 8:33 AM
kparzysz committed rL340028: [Hexagon] Expand vgather pseudos during packetization.
[Hexagon] Expand vgather pseudos during packetization
Aug 17 2018, 7:25 AM
kparzysz accepted D50842: [RegisterCoalescer] Do not assert when trying to remat dead values.

We should convert the copy to an IMPLICIT_DEF, but this patch is good as is.

Aug 17 2018, 7:06 AM
kparzysz added reviewers for D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size: RKSimon, craig.topper.
Aug 17 2018, 6:46 AM

Aug 16 2018

kparzysz committed rL339931: [SystemZ] Require asserts in subregliveness-06.mir.
[SystemZ] Require asserts in subregliveness-06.mir
Aug 16 2018, 1:13 PM
kparzysz added a comment to D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.

Ping.

Aug 16 2018, 12:47 PM
kparzysz committed rL339924: [MachineVerifier] Check if predecessor is jointly dominated by undefs.
[MachineVerifier] Check if predecessor is jointly dominated by undefs
Aug 16 2018, 12:14 PM
kparzysz committed rL339912: [RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDef.
[RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDef
Aug 16 2018, 11:03 AM
kparzysz accepted D50816: [hexagon] restore -fuse-cxa-atexit by default.
Aug 16 2018, 11:00 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

That warning can be eliminated by resolving such conflicts in favor of user-defined compositions.

Aug 16 2018, 10:44 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

The problem is in how tblgen calculates sub-registers. For a given register R, subreg indices of its sub-registers will be added to R, in other words a super-register "inherits" subreg indices from its subregisters. For example, V0 (from class VR128) has an explicit subreg index subreg_h64. It also has a sub-register F0D, which has a subreg index subreg_h32. As a result, V0 will have two subreg indices: subreg_h64 and subreg_h32. From the register structure (V0 vs F0D vs F0S) it is inferred that the composition V0.subreg_h64.subreg_h32 is same as V0.subreg_h32, a in general that the composition subreg_h64.subreg_h32 is equivalent to subreg_h32. At the same time, repeating this logic for a register F0Q from class FPR128 leads to adding subreg_h32 twice, which tblgen tries to resolve by referring to user-defined compositions. This is how subreg_hh32 shows up. However, now there is another result for composing subreg_h64.subreg_h32, hence the warning.

Aug 16 2018, 10:34 AM
kparzysz accepted D50841: [TableGen] TypeSetByHwMode::operator== optimization.

Looks good to me.

Aug 16 2018, 7:49 AM
kparzysz added a comment to D50841: [TableGen] TypeSetByHwMode::operator== optimization.

A bit of a background for clarity: <Something>ByHwMode represents <Something> parameterized by hardware mode. It's a map that to each hw mode assigns the corresponding value of <Something>. If a value for mode m is missing from the map, the default is used (this is a form of compression).

Aug 16 2018, 7:47 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

Will investigate.

Aug 16 2018, 6:09 AM

Aug 15 2018

kparzysz accepted D50789: [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize.
Aug 15 2018, 10:58 AM
kparzysz committed rL339792: [RegisterCoalescer] Ensure that both registers have subranges if one does.
[RegisterCoalescer] Ensure that both registers have subranges if one does
Aug 15 2018, 10:05 AM
kparzysz committed rL339788: [RegisterCoalescer] Reset VNInfo def when copying segments over.
[RegisterCoalescer] Reset VNInfo def when copying segments over
Aug 15 2018, 9:22 AM
kparzysz committed rL339784: [RegAlloc] Check that subreg liveness tracking applies to given virtual reg.
[RegAlloc] Check that subreg liveness tracking applies to given virtual reg
Aug 15 2018, 9:08 AM
kparzysz committed rL339780: [SystemZ] Add testcase for r339778.
[SystemZ] Add testcase for r339778
Aug 15 2018, 8:44 AM
kparzysz committed rL339778: [SystemZ] Replace subreg_r with subreg_h.
[SystemZ] Replace subreg_r with subreg_h
Aug 15 2018, 8:22 AM
kparzysz closed D50725: [SystemZ] Replace subreg_r with subreg_h.
Aug 15 2018, 8:22 AM
kparzysz added a comment to D50658: Hot cold splitting pass.

This looks good. Do you have a testcase that demonstrates what this pass does?

Aug 15 2018, 7:48 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

Running tblgen with -debug shows

Aug 15 2018, 6:50 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

This situation is the same as the case of RAX vs EAX on X86. EAX is the lower half of RAX, but modifying EAX does not preserve the upper bits of RAX. On the other hand, modifying AX (lower half of EAX) does preserve the upper half of EAX. Originally, the former behavior was modeled for both cases, i.e. overwriting a lone subregister would be considered as overwriting the entire register. I added phony registers to X86 (e.g. HAX covering the upper half of EAX) to model the latter behavior for EAX, EBX, etc.

Aug 15 2018, 6:45 AM
kparzysz added a comment to D50648: [SystemZ] Enable trackSubRegLiveness.

The option would be great. Then I could commit the fixes individually with the corresponding testcases.

Aug 15 2018, 6:20 AM

Aug 14 2018

kparzysz committed rL339718: [ReleaseNotes] Fix a typo.
[ReleaseNotes] Fix a typo
Aug 14 2018, 12:42 PM
kparzysz committed rL339717: [ReleaseNotes] Add release notes for Hexagon.
[ReleaseNotes] Add release notes for Hexagon
Aug 14 2018, 12:41 PM
kparzysz added a comment to D50690: D50648 SystemZ tests updated.

I included the testcase changes into D50648, so this patch is no longer necessary.

Aug 14 2018, 10:29 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

This is just a demonstration of what I meant in the comments for llvm.org/PR38544: getting rid of explicit overlapping subregister indices solves the problem encountered in tc_subregliveness_noliveseg.ll.

Aug 14 2018, 10:28 AM
kparzysz updated the diff for D50648: [SystemZ] Enable trackSubRegLiveness.

Fixes for remaining testcases, except tc_subregliveness_noliveseg.ll. That one requires D50725.

Aug 14 2018, 10:26 AM
kparzysz created D50725: [SystemZ] Replace subreg_r with subreg_h.
Aug 14 2018, 10:25 AM

Aug 13 2018

kparzysz created D50648: [SystemZ] Enable trackSubRegLiveness.
Aug 13 2018, 10:30 AM
kparzysz committed rL339576: [Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC.
[Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC
Aug 13 2018, 8:09 AM
kparzysz closed D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.
Aug 13 2018, 8:09 AM
kparzysz accepted D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.
Aug 13 2018, 7:57 AM
kparzysz added inline comments to D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.
Aug 13 2018, 7:37 AM
kparzysz added inline comments to D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.
Aug 13 2018, 7:18 AM
kparzysz added a comment to D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.

Try this:

Aug 13 2018, 6:02 AM
kparzysz accepted D50592: Add check for tied operands.

In the longer term we should probably make the error messages more self-explanatory.

Aug 13 2018, 5:34 AM
kparzysz added inline comments to D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.
Aug 13 2018, 5:29 AM
kparzysz removed a reviewer for D50623: [NFC] [Hexagon] Simplify int8 truncation and validation: llvm-commits.
Aug 13 2018, 5:24 AM

Aug 10 2018

kparzysz added a comment to D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering.

Btw, I didn't see your update when writing my reply, but it confirms what I thought.

Aug 10 2018, 2:06 PM
kparzysz added a comment to D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering.

I understand your point, which I believe is that the user can always sneak in some invalid code using valid instructions, which then some pass will transform into an invalid instruction. This is actually motivated by such a case (an assert cause by user program). The problem is that the assert also helped find compiler bugs, so in that sense it served its purpose. This patch is meant to address the problem in the user code before it gets to that pass, or essentially to filter out user problems before they can no longer be differentiated from internal compiler errors. It isn't intended to catch all possible forms of invalid input, but I believe it covers the only way that the user's program can trigger that particular assertion.

Aug 10 2018, 2:02 PM
kparzysz added a comment to D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.

Ping.

Aug 10 2018, 8:21 AM
kparzysz added a comment to D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering.

I am much more inclined to detect and handle invalid code early than to teach the whole backend to propagate it to the end. If a user decides to use an external assembler, code like that can trigger an error, while using internal assembler will simply hide it.

Aug 10 2018, 7:19 AM

Aug 9 2018

kparzysz added a comment to D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering.

Fix the pattern to generate a load with the misaligned address? That already happens. The problem is that we have passes that make changes based on the assumption that the instructions are valid. We make no effort to gracefully handle obviously invalid code, and if we detect it, it is usually in an assert. I think that the trap is a compromise where it won't trigger any further problems during compilation and will still fail for the user.

Aug 9 2018, 1:07 PM
kparzysz created D50524: [Hexagon] Replace fatal error with remark in HexagonISelLowering.
Aug 9 2018, 12:02 PM
kparzysz committed rL339365: [Hexagon] Map ISD::TRAP to J2_trap0(#0).
[Hexagon] Map ISD::TRAP to J2_trap0(#0)
Aug 9 2018, 11:04 AM
kparzysz accepted D50091: [SelectionDAG] try harder to convert funnel shift to rotate.
Aug 9 2018, 7:34 AM

Aug 8 2018

kparzysz added a comment to D50405: [Hexagon] Diagnose misaligned absolute loads and stores.

What we can do it convert it to a trap and emit a warning.

Aug 8 2018, 2:23 PM
kparzysz added a comment to D50405: [Hexagon] Diagnose misaligned absolute loads and stores.

This issue was detected in a customer code and it was actually a bug in it. We've decided to go this route to make it easier for customers to see what the problem is (and this scenario is almost guaranteed to be a source code bug).

Aug 8 2018, 1:54 PM
kparzysz committed rL339272: [Hexagon] Diagnose misaligned absolute loads and stores.
[Hexagon] Diagnose misaligned absolute loads and stores
Aug 8 2018, 10:00 AM
kparzysz closed D50405: [Hexagon] Diagnose misaligned absolute loads and stores.
Aug 8 2018, 10:00 AM
kparzysz added a comment to D50285: [MC] Remove MCRegisterClass::getSize.

I agree with Bjorn: both getSize and getPhysRegSize were not meant to be there. They were added because getting rid of them caused some OOT failures. That was a while back, so maybe they are no longer used. I'm all in favor of removing them, maybe we should just go ahead with it and see if anyone complains. I accepted D47199 since it contains the larger change.

Aug 8 2018, 9:12 AM
kparzysz accepted D47199: [MC] Remove PhysRegSize from MCRegisterClass.

Accepting as per comments in D50285.

Aug 8 2018, 9:11 AM
kparzysz added a comment to rL338902: Fix crash in bounds checking..

Could you commit this to the 7.0.0 branch as well, if you haven't done that yet?

Aug 8 2018, 6:04 AM
kparzysz accepted rL337830: Use SCEV to avoid inserting some bounds checks..

The crash seems to be gone. Thanks!

Aug 8 2018, 6:03 AM

Aug 7 2018

kparzysz committed rL339177: [Hexagon] Allow use of gather intrinsics even with no-packets.
[Hexagon] Allow use of gather intrinsics even with no-packets
Aug 7 2018, 1:34 PM
kparzysz created D50405: [Hexagon] Diagnose misaligned absolute loads and stores.
Aug 7 2018, 12:50 PM

Aug 6 2018

kparzysz created D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.
Aug 6 2018, 10:11 AM

Aug 3 2018

kparzysz added inline comments to D50222: [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case).
Aug 3 2018, 12:34 PM