kparzysz (Krzysztof Parzyszek)
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User Since
Apr 21 2014, 4:27 PM (238 w, 4 d)

Recent Activity

Fri, Nov 9

kparzysz committed rL346523: [Hexagon] Place globals with explicit .sdata section in small data.
[Hexagon] Place globals with explicit .sdata section in small data
Fri, Nov 9, 9:34 AM
kparzysz committed rL346494: [Hexagon] Handle Hexagon's SHF_HEX_GPREL section flag.
[Hexagon] Handle Hexagon's SHF_HEX_GPREL section flag
Fri, Nov 9, 6:20 AM

Fri, Nov 2

kparzysz committed rL345975: [Hexagon] Do not reduce load size for globals in small-data.
[Hexagon] Do not reduce load size for globals in small-data
Fri, Nov 2, 7:21 AM

Thu, Nov 1

kparzysz accepted D53991: [Hexagon] Remove unintended fallthrough from MC duplex code.

Thanks!

Thu, Nov 1, 12:46 PM

Wed, Oct 31

kparzysz accepted D53931: TableGen: Fix ASAN error.

Thanks for the investigation. What concerns me a bit is that this isn't the only place where this pattern occurs, but hopefully it will be detected if it causes problems. It would be nice to have enough data to file a bug report against stdc++, but for now we can apply this workaround.

Wed, Oct 31, 10:43 AM
kparzysz committed rL345731: [Hexagon] Make sure not to use GP-relative addressing with PIC.
[Hexagon] Make sure not to use GP-relative addressing with PIC
Wed, Oct 31, 8:56 AM
kparzysz added inline comments to D53931: TableGen: Fix ASAN error.
Wed, Oct 31, 7:16 AM

Fri, Oct 26

kparzysz added a comment to D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor.

Hexagon packets (bundles) have 4 slots, numbered 0..3. Each one of the three instructions (2 x S2_extractu, and PS_call_nr) can only go in slots 2 or 3, so something went horribly wrong.

Fri, Oct 26, 8:25 AM

Wed, Oct 24

kparzysz committed rL345170: [Hexagon] Flip hexagon-autohvx to be true by default.
[Hexagon] Flip hexagon-autohvx to be true by default
Wed, Oct 24, 10:58 AM
kparzysz committed rL345169: [Hexagon] Flip hexagon-autohvx to be true by default.
[Hexagon] Flip hexagon-autohvx to be true by default
Wed, Oct 24, 10:58 AM
kparzysz committed rC345170: [Hexagon] Flip hexagon-autohvx to be true by default.
[Hexagon] Flip hexagon-autohvx to be true by default
Wed, Oct 24, 10:58 AM

Fri, Oct 19

kparzysz added a comment to D52366: [tblgen][disasm] Separate encodings from instructions.

The encoding of an instruction includes encodings of its operands. How are you planning to implement separate encoder/decoder methods? Right now their names are all embedded into operand definitions.

Fri, Oct 19, 2:23 PM
kparzysz committed rL344791: [Hexagon] Remove support for V4.
[Hexagon] Remove support for V4
Fri, Oct 19, 10:33 AM
kparzysz committed rL344786: [Hexagon] Remove support for V4.
[Hexagon] Remove support for V4
Fri, Oct 19, 8:39 AM
kparzysz committed rC344786: [Hexagon] Remove support for V4.
[Hexagon] Remove support for V4
Fri, Oct 19, 8:38 AM

Oct 16 2018

kparzysz accepted D53326: [python] [tests] Disable on known-broken arches.
Oct 16 2018, 2:02 PM
kparzysz added a comment to D52840: Include Python binding tests in CMake rules.

Hexagon clang builder has been failing since around the time of this commit as well:
http://lab.llvm.org:8011/builders/clang-hexagon-elf/builds/20617/steps/ninja%20check%201/logs/stdio

Oct 16 2018, 7:09 AM

Oct 12 2018

kparzysz added a comment to D53184: [LangRef] Clarify semantics of volatile operations..

What thread was that discussion in? Accesses to device-mapped memory can trap, what is the reason for the compiler to assume that they can't?

Oct 12 2018, 10:33 AM

Oct 11 2018

kparzysz accepted D53152: [Hexagon] Restrict compound instructions with constant value..
Oct 11 2018, 12:36 PM
kparzysz added inline comments to D53152: [Hexagon] Restrict compound instructions with constant value..
Oct 11 2018, 11:58 AM
kparzysz committed rL344271: [Hexagon] Eliminate potential sources of non-determinism in HCE.
[Hexagon] Eliminate potential sources of non-determinism in HCE
Oct 11 2018, 11:28 AM

Oct 9 2018

kparzysz accepted D53038: [Hexagon] Use GetLinkerPath method instead of hard-coded linker name..
Oct 9 2018, 1:23 PM

Oct 2 2018

kparzysz committed rL343596: [Hexagon] Fix extracting subvectors of non-HVX vNi1.
[Hexagon] Fix extracting subvectors of non-HVX vNi1
Oct 2 2018, 8:07 AM

Oct 1 2018

kparzysz committed rL343514: [Hexagon] Remove incorrect pattern for swiz.
[Hexagon] Remove incorrect pattern for swiz
Oct 1 2018, 11:26 AM

Sep 26 2018

kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Right at the beginning of CodeGenRegBank::computeComposites, I added

Sep 26 2018, 12:28 PM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

So it should not be possible to do subreg_h32(V0), right?

Sep 26 2018, 11:59 AM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

The warning seem to be plain wrong. The warning claims that

warning: SubRegIndex SystemZ::subreg_h64 and SystemZ::subreg_h32 compose ambiguously as SystemZ::subreg_hh32 or SystemZ::subreg_h32

This is based on V0: subreg_h64(V0) = F0D, subreg_h32(F0D) = F0S. So the composition (and subreg_hh32, user-defined as that composition) maps V0 to F0S. Now subreg_h32(V0) = F0S, so for V0 these two indeed agree. This is the cause for the warning.
However, for F0Q, subreg_h32(subreg_h64(F0Q)) = subreg_h32(F0D) = F0S, while subreg_h32(F0Q) = F2S. So, while these compositions agree on at least one register, they are not equal in general.

Sep 26 2018, 10:32 AM

Sep 21 2018

kparzysz committed rL342751: [Hexagon] Avoid functions with exception handling in HexagonConstExtenders.
[Hexagon] Avoid functions with exception handling in HexagonConstExtenders
Sep 21 2018, 10:44 AM

Sep 20 2018

kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

I've looked into this and there is no way to distinguish the case of hh (no warning) and ll (emit a warning). They are both equivalent: a user-defined composition vs. pre-existing subreg.

Sep 20 2018, 8:21 AM

Sep 19 2018

kparzysz accepted D52237: [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs.
Sep 19 2018, 10:03 AM

Sep 18 2018

kparzysz committed rL342492: [PostRASink] Make sure to remove subregisters from live-ins as well.
[PostRASink] Make sure to remove subregisters from live-ins as well
Sep 18 2018, 9:12 AM
kparzysz added a comment to D52237: [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs.

In general, looking at a single instruction is not sufficient to tell whether a given register becomes dead or not, so I wouldn't worry about the limitation you mentioned. Cases that we can reliably handle are (sub)ranges corresponding to the parts of the register that is given in the operand (i.e. the entire register if there is no subregister).

Sep 18 2018, 9:04 AM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

The conflict between user-defined and inferred compositions causes a warning in the SystemZ build:

warning: SubRegIndex SystemZ::subreg_h64 and SystemZ::subreg_h32 compose ambiguously as SystemZ::subreg_hh32 or SystemZ::subreg_h32
Sep 18 2018, 5:33 AM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Ping.

Sep 18 2018, 5:27 AM

Sep 12 2018

kparzysz committed rL342091: [Hexagon] Use shuffles when lowering "gather" shufflevectors.
[Hexagon] Use shuffles when lowering "gather" shufflevectors
Sep 12 2018, 3:16 PM
kparzysz committed rL342090: [Hexagon] Improve the selection algorithm in scalarizeShuffle.
[Hexagon] Improve the selection algorithm in scalarizeShuffle
Sep 12 2018, 3:12 PM
kparzysz committed rL342079: [Hexagon] Use legalized type for extracted elements in scalarizeShuffle.
[Hexagon] Use legalized type for extracted elements in scalarizeShuffle
Sep 12 2018, 2:00 PM

Sep 11 2018

kparzysz added inline comments to D50944: [Hexagon] [Test] Remove undef and infinite loop from test.
Sep 11 2018, 6:25 AM

Sep 10 2018

kparzysz committed rL341851: [Hexagon] Split large offsets into properly aligned addends.
[Hexagon] Split large offsets into properly aligned addends
Sep 10 2018, 11:50 AM

Sep 5 2018

kparzysz committed rL341478: [Hexagon] Ignore unnamed globals in HexagonConstExtenders.
[Hexagon] Ignore unnamed globals in HexagonConstExtenders
Sep 5 2018, 8:56 AM
kparzysz added inline comments to D51474: Consider CSRs in computeRegisterLiveness.
Sep 5 2018, 8:17 AM

Sep 4 2018

kparzysz committed rL341409: [Hexagon] Don't packetize new-value stores with any other stores.
[Hexagon] Don't packetize new-value stores with any other stores
Sep 4 2018, 2:09 PM
kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Ping.

Sep 4 2018, 9:18 AM

Aug 31 2018

kparzysz committed rL341264: [Hexagon] Don't access non-existent instructions.
[Hexagon] Don't access non-existent instructions
Aug 31 2018, 3:11 PM

Aug 30 2018

kparzysz committed rL341137: [Hexagon] Check validity of register class when generating bitsplit.
[Hexagon] Check validity of register class when generating bitsplit
Aug 30 2018, 3:27 PM
kparzysz added a comment to D51058: [zorg] Pass environment to getPollyBuildFactory and getAOSPBuildFactory.

Ping.

Aug 30 2018, 10:48 AM

Aug 28 2018

kparzysz accepted D51035: [TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching predicates.
Aug 28 2018, 6:37 AM

Aug 27 2018

kparzysz added a comment to D51035: [TableGen] CodeGenDAGPatterns::GenerateVariants - basic caching of matching predicates.

It should be possible to move this loop out of the nest and only have it iterate over the preexisting patterns. Could you see if that generates different .inc files (it shouldn't)?

Aug 27 2018, 1:10 PM

Aug 24 2018

kparzysz added a comment to D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.

Ping.

Aug 24 2018, 10:44 AM
kparzysz committed rC340622: [Hexagon] Remove unneeded strings from builtin definitions, NFC.
[Hexagon] Remove unneeded strings from builtin definitions, NFC
Aug 24 2018, 10:15 AM
kparzysz committed rL340622: [Hexagon] Remove unneeded strings from builtin definitions, NFC.
[Hexagon] Remove unneeded strings from builtin definitions, NFC
Aug 24 2018, 10:14 AM

Aug 23 2018

kparzysz abandoned D24631: [RFC] Implement variable-width register classes, step 1: API changes.

Already implemented.

Aug 23 2018, 9:16 AM
kparzysz abandoned D50648: [SystemZ] Enable trackSubRegLiveness.

The fixes have been committed individually.

Aug 23 2018, 9:15 AM
kparzysz accepted D50637: [CodeGen] Set FrameSetup/FrameDestroy on BUNDLE instructions.
Aug 23 2018, 7:13 AM

Aug 22 2018

kparzysz committed rL340447: [Hexagon] Enable interleaving in loop vectorizer.
[Hexagon] Enable interleaving in loop vectorizer
Aug 22 2018, 1:15 PM

Aug 21 2018

kparzysz created D51058: [zorg] Pass environment to getPollyBuildFactory and getAOSPBuildFactory.
Aug 21 2018, 12:44 PM
kparzysz committed rL340318: [RegisterCoalscer] Manually remove leftover segments when commuting def.
[RegisterCoalscer] Manually remove leftover segments when commuting def
Aug 21 2018, 12:02 PM

Aug 20 2018

kparzysz committed rL340213: [zorg] Update clang on Hexagon builders to 6.0.1.
[zorg] Update clang on Hexagon builders to 6.0.1
Aug 20 2018, 2:03 PM
kparzysz committed rL340208: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.
Consistently use MemoryLocation::UnknownSize to indicate unknown access size
Aug 20 2018, 1:38 PM
kparzysz closed D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.
Aug 20 2018, 1:38 PM
kparzysz added a comment to D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.

The practical application of this is to indicate aliasing with a given memory object, but without specifying exactly which part of the object is accessed (since it may be unknown). Dropping memory operands altogether will alias the operation with all other objects, so it will be correct, but overly conservative.

Aug 20 2018, 10:19 AM
kparzysz created D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones.
Aug 20 2018, 10:14 AM
kparzysz accepted D50944: [Hexagon] [Test] Remove undef and infinite loop from test.
Aug 20 2018, 5:38 AM

Aug 17 2018

kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

Yes, I do have one. I'll post it on Monday.

Aug 17 2018, 2:58 PM
kparzysz committed rL340081: [Hexagon] Remove unused functions from HexagonInstPrinter, NFC.
[Hexagon] Remove unused functions from HexagonInstPrinter, NFC
Aug 17 2018, 2:13 PM
kparzysz added a comment to D50903: [TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode.

Thanks for finding all these things!

Aug 17 2018, 8:38 AM
kparzysz accepted D50903: [TableGen] TypeInfer - Cache the legal types as TypeSetByHwMode.
Aug 17 2018, 8:33 AM
kparzysz committed rL340028: [Hexagon] Expand vgather pseudos during packetization.
[Hexagon] Expand vgather pseudos during packetization
Aug 17 2018, 7:25 AM
kparzysz accepted D50842: [RegisterCoalescer] Do not assert when trying to remat dead values.

We should convert the copy to an IMPLICIT_DEF, but this patch is good as is.

Aug 17 2018, 7:06 AM
kparzysz added reviewers for D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size: RKSimon, craig.topper.
Aug 17 2018, 6:46 AM

Aug 16 2018

kparzysz committed rL339931: [SystemZ] Require asserts in subregliveness-06.mir.
[SystemZ] Require asserts in subregliveness-06.mir
Aug 16 2018, 1:13 PM
kparzysz added a comment to D50339: Consistently use MemoryLocation::UnknownSize to indicate unknown access size.

Ping.

Aug 16 2018, 12:47 PM
kparzysz committed rL339924: [MachineVerifier] Check if predecessor is jointly dominated by undefs.
[MachineVerifier] Check if predecessor is jointly dominated by undefs
Aug 16 2018, 12:14 PM
kparzysz committed rL339912: [RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDef.
[RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDef
Aug 16 2018, 11:03 AM
kparzysz accepted D50816: [hexagon] restore -fuse-cxa-atexit by default.
Aug 16 2018, 11:00 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

That warning can be eliminated by resolving such conflicts in favor of user-defined compositions.

Aug 16 2018, 10:44 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

The problem is in how tblgen calculates sub-registers. For a given register R, subreg indices of its sub-registers will be added to R, in other words a super-register "inherits" subreg indices from its subregisters. For example, V0 (from class VR128) has an explicit subreg index subreg_h64. It also has a sub-register F0D, which has a subreg index subreg_h32. As a result, V0 will have two subreg indices: subreg_h64 and subreg_h32. From the register structure (V0 vs F0D vs F0S) it is inferred that the composition V0.subreg_h64.subreg_h32 is same as V0.subreg_h32, a in general that the composition subreg_h64.subreg_h32 is equivalent to subreg_h32. At the same time, repeating this logic for a register F0Q from class FPR128 leads to adding subreg_h32 twice, which tblgen tries to resolve by referring to user-defined compositions. This is how subreg_hh32 shows up. However, now there is another result for composing subreg_h64.subreg_h32, hence the warning.

Aug 16 2018, 10:34 AM
kparzysz accepted D50841: [TableGen] TypeSetByHwMode::operator== optimization.

Looks good to me.

Aug 16 2018, 7:49 AM
kparzysz added a comment to D50841: [TableGen] TypeSetByHwMode::operator== optimization.

A bit of a background for clarity: <Something>ByHwMode represents <Something> parameterized by hardware mode. It's a map that to each hw mode assigns the corresponding value of <Something>. If a value for mode m is missing from the map, the default is used (this is a form of compression).

Aug 16 2018, 7:47 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

Will investigate.

Aug 16 2018, 6:09 AM

Aug 15 2018

kparzysz accepted D50789: [TableGen] Remove unnecessary TypeSetByHwMode -> ValueTypeByHwMode -> TypeSetByHwMode conversions in getPatternSize.
Aug 15 2018, 10:58 AM
kparzysz committed rL339792: [RegisterCoalescer] Ensure that both registers have subranges if one does.
[RegisterCoalescer] Ensure that both registers have subranges if one does
Aug 15 2018, 10:05 AM
kparzysz committed rL339788: [RegisterCoalescer] Reset VNInfo def when copying segments over.
[RegisterCoalescer] Reset VNInfo def when copying segments over
Aug 15 2018, 9:22 AM
kparzysz committed rL339784: [RegAlloc] Check that subreg liveness tracking applies to given virtual reg.
[RegAlloc] Check that subreg liveness tracking applies to given virtual reg
Aug 15 2018, 9:08 AM
kparzysz committed rL339780: [SystemZ] Add testcase for r339778.
[SystemZ] Add testcase for r339778
Aug 15 2018, 8:44 AM
kparzysz committed rL339778: [SystemZ] Replace subreg_r with subreg_h.
[SystemZ] Replace subreg_r with subreg_h
Aug 15 2018, 8:22 AM
kparzysz closed D50725: [SystemZ] Replace subreg_r with subreg_h.
Aug 15 2018, 8:22 AM
kparzysz added a comment to D50658: Hot cold splitting pass.

This looks good. Do you have a testcase that demonstrates what this pass does?

Aug 15 2018, 7:48 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

Running tblgen with -debug shows

Aug 15 2018, 6:50 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

This situation is the same as the case of RAX vs EAX on X86. EAX is the lower half of RAX, but modifying EAX does not preserve the upper bits of RAX. On the other hand, modifying AX (lower half of EAX) does preserve the upper half of EAX. Originally, the former behavior was modeled for both cases, i.e. overwriting a lone subregister would be considered as overwriting the entire register. I added phony registers to X86 (e.g. HAX covering the upper half of EAX) to model the latter behavior for EAX, EBX, etc.

Aug 15 2018, 6:45 AM
kparzysz added a comment to D50648: [SystemZ] Enable trackSubRegLiveness.

The option would be great. Then I could commit the fixes individually with the corresponding testcases.

Aug 15 2018, 6:20 AM

Aug 14 2018

kparzysz committed rL339718: [ReleaseNotes] Fix a typo.
[ReleaseNotes] Fix a typo
Aug 14 2018, 12:42 PM
kparzysz committed rL339717: [ReleaseNotes] Add release notes for Hexagon.
[ReleaseNotes] Add release notes for Hexagon
Aug 14 2018, 12:41 PM
kparzysz added a comment to D50690: D50648 SystemZ tests updated.

I included the testcase changes into D50648, so this patch is no longer necessary.

Aug 14 2018, 10:29 AM
kparzysz added a comment to D50725: [SystemZ] Replace subreg_r with subreg_h.

This is just a demonstration of what I meant in the comments for llvm.org/PR38544: getting rid of explicit overlapping subregister indices solves the problem encountered in tc_subregliveness_noliveseg.ll.

Aug 14 2018, 10:28 AM
kparzysz updated the diff for D50648: [SystemZ] Enable trackSubRegLiveness.

Fixes for remaining testcases, except tc_subregliveness_noliveseg.ll. That one requires D50725.

Aug 14 2018, 10:26 AM
kparzysz created D50725: [SystemZ] Replace subreg_r with subreg_h.
Aug 14 2018, 10:25 AM

Aug 13 2018

kparzysz created D50648: [SystemZ] Enable trackSubRegLiveness.
Aug 13 2018, 10:30 AM
kparzysz committed rL339576: [Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC.
[Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFC
Aug 13 2018, 8:09 AM
kparzysz closed D50623: [NFC] [Hexagon] Simplify int8 truncation and validation.
Aug 13 2018, 8:09 AM