♟ jpienaar

Change to Lanai seems fine. The model for Lanai execution/usage means atomics aren't important, but treating them conservatively is better. Thanks!

[lanai] Handle atomic load of i8 like regular load.

Looks good and as discussed the regression will be addressed by using carry.

[Lanai] Code model dictates section selection.

Removed some unrelated renames.

Didn't mean to have this send out emails yet, some spurious changes that I want to revert still.

@MatzeB I'll take a swing at updating those later and sending you a review (traveling, so response time variable).

[lanai] Add getIntImmCost in LanaiTargetTransformInfo.

Looks good for Lanai changes

[lanai] Add computeKnownBitsForTargetNode for Lanai.

In D29605#668363, @majnemer wrote:

In D29605#668334, @majnemer wrote:

Hmm, this is the sort of thing I'd expect SelectionDAG to "just do"... Do other backends achieve the same end by similar means?

Add computeKnownBitsForTargetNode for Lanai.

clean Lanai namespace

Thanks. Could you run this through clang/tools/clang-format-diff.py before committing?

[lanai] Simplify small section check in LowerGlobalAddress and treat ldata…

[lanai] Custom lowering of SHL_PARTS

Expand test to test lowering of ashldi.

Updated the pseudo code variable names to correspond better with actual variable names used.

[lanai] Manually match 0/-1 with R0/R1.

Updated to test the type before matching R0 and R1.

[NVPTX] Check if callsite is defined when computing argument allignment

Looks good to me, do you need help submitting?

Cool. I didn't know the review system allows having the patch updated like this :) It still reports me as the author and you as a subscriber. I don't think that matters.

Oh, sorry, I didn't see your response before I clicked abandoned. It has been a while, so this patch is pretty stale.

[lanai] Use const instead of constexpr

[lanai] Make Lanai backend non-experimental

[lanai] Exit early in Mem Alu combiner if sentinel reach.

Fix link quotes on AArch64's CompilerWriterInfo section.

[lanai] Add ISA document to CompilerWritersInfo

SG, will do cleanup separately.

[lanai] Update for Target API (TargetRegistry::RegisterMCAsmBackend) change

[lanai] Small cleanup: remove/comment out unused args

[lanai] Fix build by updating calls to getLoad & getStore.

Rename AnalyzeBranch* to analyzeBranch*.

[lanai] Add more tests for assembly of conditional ALU ops

[lanai] Treat .t as optional in assembly parser for RR operands and add…

[lanai] Update test to use peephole-opt and not peephole-opts

[lanai] Use peephole optimizer to generate more conditional ALU operations.

Comments addressed, thanks.

[lanai] Update ELF number to correspond to the assigned number.

In D21726#467239, @ab wrote:

In D21726#467230, @ab wrote:

Also, I see BPF doesn't need any changes; can you confirm?

Looks like Lanai will though; I suppose that can be done separately.

[lanai] Change reloc to use PIC_ by default and cleanup.

[lanai] Use Optional<Reloc> in LanaiTargetMachine.

[lanai] Change the way flag setting instructions are checked.

[lanai] Update handling of structs in arguments to be passed in registers.

[lanai] Expand findClosestSuitableAluInstr check to consider offset register.

[lanai] Add subword scheduling itineraries.

[lanai] Add lowering for SETCCE i32.

[lanai] Set boolean contentss to ZeroOrOneBooleanContent.

[lanai] Add custom lowering for SRL_PARTS i32.

[lanai] Add areMemAccessesTriviallyDisjoint, getMemOpBaseRegImmOfs and…

Updated to address comments.

@mcrosier: Yes indeed, funny things can happen if these are wrong :). Added a IR test to test some of the different code paths in areMemAccessesTriviallyDisjoint.

Adding simple test case to verify effect on scheduling DAG due to areMemAccessesTriviallyDisjoint change.

[lanai] LanaiSetflagAluCombiner more conservative

[lanai] Fix for LanaiDelaySlotFiller and LanaiMCInstLower.cpp

[lanai] isBrImm should accept any non-constant immediate.

Changing to test that uses llvm-mc directly instead of llc.

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