rengolin (Renato Golin)
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User Since
Oct 19 2012, 12:57 AM (316 w, 5 d)

Recent Activity

Yesterday

rengolin accepted D54378: Add Hurd triplet to LLVMSupport.
Tue, Nov 13, 11:26 PM
rengolin accepted D49489: [VPlan] VPlan version of InterleavedAccessInfo..

Perfect, LGTM. Thanks!

Tue, Nov 13, 6:46 AM
rengolin added a comment to D49489: [VPlan] VPlan version of InterleavedAccessInfo..

So, IIUC, the way you only get the interleave info on instructions and map to VPlan is because we don't yet have scalar evolution in VPlan, so we need to do that in Instruction and then map to VPInstruction.

Tue, Nov 13, 5:04 AM

Mon, Nov 12

rengolin accepted D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

Just had a look again and it's looking great, thanks Florian!

Mon, Nov 12, 12:53 PM

Sat, Nov 10

rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I really do find the break with convention here somewhat deeply unfortunate. It makes parsing and recognizing triples reliably much harder IMO. This really should be 'hurd-gnu' or 'mach-gnu' (or however you want to spell the 'OS' here).

Sat, Nov 10, 9:09 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

That's not to say I'm against adding support for GNU Hurd, I'm moreso implying that regardless of what GNU Hurd guidelines say, if they may cause problems in LLVM ecosystem, especially as far as core targets (or rather platforms) go, you have to consider the large ecosystems that use Clang and LLVM and sometimes adapt to avoid causing issues downstream (for example with distro vendors with Glibc/GNU Linux being the core of main variations of server and desktop Linux distros).

Sat, Nov 10, 8:56 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

To be honest, I hadn't even imagined that the patch could have consequences on non-Hurd systems.

Sat, Nov 10, 8:54 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

Is that really supposed to work? I thought the rules was that the cpu parts and the vendor parts mustn't contain '-', and thus the splitting is never ambiguous, and the os part can contain '-' (heavily used by GNU/Linux, GNU/kFreeBSD, etc.)

Sat, Nov 10, 8:24 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

Well, it definitely is for GNU/Hurd, now that very basic software pieces such as librsvg start _depending_ on rust, which is available only through llvm.

Sat, Nov 10, 8:12 AM
rengolin requested changes to D54378: Add Hurd triplet to LLVMSupport.

Yes but my concern comes from possible confusion with Glibc based Linux targets which are one of the "main" targets supported by LLVM. Either adding hurd or mach somewhere would be sufficient to disambiguate it from others, and yes I'm aware that they have a somewhat free format but they convey some sort of information, ie. with Linux targets gnu implies GNU/Glibc-based userland, so going by that convention one could easily assume that said triple simply implies GNU/Glibc/ELF userland. I think simply using gnu is too ambiguous, especially considering this is being added as an experimental target.

Sat, Nov 10, 7:49 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I understand your concerns, but that's really not something that we can change at this point, there is far too much software which has written i386-pc-gnu in their source code for us to change all that.

Sat, Nov 10, 7:46 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I'm not sure how GCC does it but this seems pretty out of line in comparison to all other targets, GNU makes sense to indicate that the target uses a GNU (usually with Glibc) userland but there's no indication of the kernel, which would be something like mk or mach. In which case I think i386-pc-mach-gnu or something along the lines would make sense, unless this is absolutely needed for compatibility reasons?

Sat, Nov 10, 6:21 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

(I can not commit this myself)

Sat, Nov 10, 5:57 AM
rengolin accepted D54378: Add Hurd triplet to LLVMSupport.

The GNU/Hurd triple is target-gnu, simply.

Sat, Nov 10, 5:46 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I had no idea Hurd was still alive, but hey!

Sat, Nov 10, 5:38 AM

Thu, Nov 8

rengolin committed rL346396: Adding Yvan as release test backup for Diana.
Adding Yvan as release test backup for Diana
Thu, Nov 8, 3:53 AM

Sat, Nov 3

rengolin added a comment to D53137: Scalable type size queries (llvm).

This looks ok to me, but I'd rather more people look at it before approving.

Sat, Nov 3, 6:46 AM

Wed, Oct 31

rengolin added inline comments to D53695: Scalable VectorType RFC.
Wed, Oct 31, 6:49 AM

Tue, Oct 30

rengolin added reviewers for D53816: [TableGen:AsmWriter] Cope with consecutive tied operands.: atanasyan, asb, jholewinski, t.p.northover, kparzysz, craig.topper, stoklund.

Right, I don't see anything wrong with it, but I'm adding other back-end maintainers and Jakob, TableGen's maintainer, so we're sure this is as harmless as I seem to think it is. :)

Tue, Oct 30, 4:48 AM
rengolin added a comment to D53816: [TableGen:AsmWriter] Cope with consecutive tied operands..

Hi Simon,

Tue, Oct 30, 2:54 AM

Sat, Oct 27

rengolin added a comment to D49168: [LV] Add a new reduction pattern match.

Reverted in r345465. Will take a look and land again when fixed. Thanks!

Sat, Oct 27, 3:16 PM
rengolin committed rL345465: Revert r344172: [LV] Add a new reduction pattern match.
Revert r344172: [LV] Add a new reduction pattern match
Sat, Oct 27, 3:16 PM

Fri, Oct 26

rengolin added a comment to D49168: [LV] Add a new reduction pattern match.

This patch doesn't correctly handle isFast(). By default isRecurrenceInstr() should check I->isFast(), but for this pattern I is Select, isFast() doesn't apply to it, it should be checked against FAdd/FMul inside isConditionalRdxPattern().

Fri, Oct 26, 3:54 PM
rengolin added a comment to D53695: Scalable VectorType RFC.

This is looking good to me, thanks!

Fri, Oct 26, 4:12 AM

Tue, Oct 23

rengolin accepted D46714: [test-suite] Add list of programs we might add..

I also have a list somewhere, that I will add once I find it.

Tue, Oct 23, 12:24 PM

Sat, Oct 20

rengolin added a comment to D53355: Introducing VPPHINode .

Hi Nikolay,

Sat, Oct 20, 8:17 AM

Tue, Oct 16

rengolin committed rL344599: [VPlan] Script to extract VPlan digraphs from log.
[VPlan] Script to extract VPlan digraphs from log
Tue, Oct 16, 2:40 AM
rengolin closed D53142: [VPlan] Script to extract VPlan digraphs from log.
Tue, Oct 16, 2:40 AM

Mon, Oct 15

rengolin added a comment to D53142: [VPlan] Script to extract VPlan digraphs from log.

(very gentle ping) :)

Mon, Oct 15, 10:45 AM

Oct 12 2018

rengolin updated the diff for D53142: [VPlan] Script to extract VPlan digraphs from log.

Consistent messages.

Oct 12 2018, 3:20 AM
rengolin added inline comments to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.
Oct 12 2018, 1:34 AM

Oct 11 2018

rengolin added a comment to D53146: [MC][ELF] fix newly added test.

Oh, you've done that. The diff isn't clear.

Oct 11 2018, 11:04 AM
rengolin added a comment to D53146: [MC][ELF] fix newly added test.

The failure in Arm had nothing to do with not being ELF, but the asm syntax was different.

Oct 11 2018, 11:04 AM
rengolin added a comment to D53142: [VPlan] Script to extract VPlan digraphs from log.

I'm wondering... should we choose between dot and png? Or should we always print the dot file and, upon --png flag, also the png file?

Oct 11 2018, 10:25 AM
rengolin updated the diff for D53142: [VPlan] Script to extract VPlan digraphs from log.

Thanks Florian, your regex version is still easy to use and much cleaner.

Oct 11 2018, 10:16 AM
rengolin updated the diff for D53142: [VPlan] Script to extract VPlan digraphs from log.

Hi Florian,

Oct 11 2018, 10:07 AM
rengolin created D53142: [VPlan] Script to extract VPlan digraphs from log.
Oct 11 2018, 9:30 AM

Oct 10 2018

rengolin committed rL344172: [LV] Add a new reduction pattern match.
[LV] Add a new reduction pattern match
Oct 10 2018, 11:51 AM
rengolin closed D49168: [LV] Add a new reduction pattern match.
Oct 10 2018, 11:51 AM
rengolin committed rL344161: [VPlan] Fix CondBit quoting in dumpBasicBlock.
[VPlan] Fix CondBit quoting in dumpBasicBlock
Oct 10 2018, 10:57 AM
rengolin accepted D53091: [LV] Ignore more debug info..

Seems trivial. instructionsWithoutDebug is just an iterator filter and there are no early continues in the body of the outer loop, so this actually saves time.

Oct 10 2018, 10:21 AM
rengolin accepted D53089: [LV] Use SmallVector instead of DenseMap in calculateRegisterUsage (NFC)..

Good catch! LGTM, thanks!

Oct 10 2018, 10:18 AM

Oct 9 2018

rengolin added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Could also be an architectural flag, giving this is a particular behaviour from Exynos. Then a simple splitsJumpTables() or whatever check would be enough.

Oct 9 2018, 10:04 PM
rengolin added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

As you'd expect, size is pretty good. Over the test-suite (including externals) nothing regresses. The total benefit over all the code is 0.5%, with notable highlights of 25% in 401.bzip2, 7% in 403.gcc, and 4% in 177.mesa.

Oct 9 2018, 6:49 AM
rengolin updated the diff for D49168: [LV] Add a new reduction pattern match.

Changes to comment:

  • Improved comments on isConditionalRdxPattern
  • Removed instcombine pass from test
  • Added write negative test
  • Fix typo in CHECK line
Oct 9 2018, 3:08 AM

Oct 8 2018

rengolin added a comment to D49168: [LV] Add a new reduction pattern match.

LGTM. Please wait for a few days to give others time to respond if they'd like to.

Oct 8 2018, 2:40 PM
rengolin added inline comments to D49168: [LV] Add a new reduction pattern match.
Oct 8 2018, 2:05 PM
rengolin updated the summary of D49168: [LV] Add a new reduction pattern match.
Oct 8 2018, 10:16 AM
rengolin updated the diff for D49168: [LV] Add a new reduction pattern match.
Oct 8 2018, 10:16 AM
rengolin commandeered D49168: [LV] Add a new reduction pattern match.

Hi Hideki,

Oct 8 2018, 10:15 AM

Oct 4 2018

rengolin added a comment to D52829: [AArch64] Fix verifier error when outlining indirect calls.

OTOH, having a function flag or something like @rengolin suggested is probably a bit cleaner in the long term. I slightly prefer this position since it seems like it should be the verifier's responsibility to understand what to do with an outlined function. Also, if it does turn out that there are other weird cases, it'd be kind of overkill to add special outlining instructions everywhere just to appease the verifier.

Oct 4 2018, 10:23 AM
rengolin added a comment to D52829: [AArch64] Fix verifier error when outlining indirect calls.

Are there no other ways to identify an outliner function, say a function flag or a needed pattern, so we can change the verifier instead, and not fail when called-saved regs are used?

Oct 4 2018, 2:08 AM

Oct 2 2018

rengolin added a comment to D52784: [ARM][AArch64] Pass through endianness flags to the GNU assembler and linker.

Hi Peter,

Oct 2 2018, 8:15 AM

Oct 1 2018

rengolin added a comment to D52149: add support functions for hard/soft float multilib distinction.

There's no intent to revert

Oct 1 2018, 4:40 AM
rengolin added a comment to D52149: add support functions for hard/soft float multilib distinction.

I think it's okay to land this for convenience for now (once the issues are addressed) and if the Clang differential does not get approved revert this, which is not especially difficult since the support lib is quite isolated.

Oct 1 2018, 4:09 AM
rengolin added reviewers for D52149: add support functions for hard/soft float multilib distinction: olista01, echristo, raj.khem, sdardis.

Adding more people that work around triples...

Oct 1 2018, 3:38 AM
rengolin added a comment to D52149: add support functions for hard/soft float multilib distinction.

This is a slight duplication of what we already have in ARMSubtarget.h, and given that this is *only* relevant for AArch32, I see no point in this being in the Triple.

Oct 1 2018, 3:36 AM
rengolin requested changes to D52149: add support functions for hard/soft float multilib distinction.
Oct 1 2018, 3:36 AM

Sep 27 2018

rengolin added a comment to D18086: Fix default processor name for armv6k..

The other two reviews were approved. This one can now be closed. Thanks!

Sep 27 2018, 8:53 AM
rengolin accepted D52595: [ARM] Alter test to account for change to armv6k default CPU.

Thanks Peter. LGTM!

Sep 27 2018, 8:52 AM
rengolin accepted D52594: [ARM] Remove non-existent cpu arm1176j-s and use mpcore for v6k.

Thanks Peter! LGTM.

Sep 27 2018, 8:51 AM

Sep 14 2018

rengolin added a comment to D18086: Fix default processor name for armv6k..

Corrections are always welcome. Please submit an update to this thread (or a new patch) to fix the changes you propose.

Sep 14 2018, 6:07 AM
rengolin added a comment to D18086: Fix default processor name for armv6k..

If j-s doesn't exists (remember, most of that list came from the ancient days of llvm, so could very easily be completely wrong, but "works"), I all for removing it and making a new (correct) CPU name as the default for armv6k.

Sep 14 2018, 4:45 AM

Sep 13 2018

rengolin added inline comments to D18086: Fix default processor name for armv6k..
Sep 13 2018, 12:50 PM
rengolin added a comment to D18086: Fix default processor name for armv6k..

I seem to have a related issue: I am using -march=armv6k and -no-integrated-as, this generates the following output:
/tmp/empty-bc2ea3.s:4: Error: unknown cpu `arm1176j-s'

Sep 13 2018, 11:40 AM

Sep 11 2018

rengolin accepted D49488: [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC).

Thanks Florian! LGTM too.

Sep 11 2018, 9:02 AM

Aug 30 2018

rengolin added a comment to D51465: Revamp test-suite documentation.

Very detailed, using the modern infrastructure and helpful even to those not using clang or wanting to run external benchmarks.

Aug 30 2018, 2:59 AM

Jul 19 2018

rengolin added reviewers for D49563: [ARM] Add new target feature to fuse literal generation: efriedma, SjoerdMeijer, peter.smith, thopre, kristof.beyls, aadg.

I shall, at least for Exynos, but I'd like to hear from our friends at ARM too.

Jul 19 2018, 1:22 PM
rengolin added reviewers for D49168: [LV] Add a new reduction pattern match: fhahn, RKSimon, dcaballe, hsaito.

Hi Takahiro,

Jul 19 2018, 1:13 PM
rengolin added a comment to D49563: [ARM] Add new target feature to fuse literal generation.

Hi Evandro, looks great, short and simple!

Jul 19 2018, 1:11 PM
rengolin added a comment to D49488: [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC).

Moved getMemInstAlignment and getMemInstAddressSpace to IR/Instructions.h which already contains similar helpers. Should I rename them to getLoadStoreAlignment and getLoadStoreAddressSpace to be more in line with the existing getLoadStorePointerOperand?

Jul 19 2018, 12:38 PM
rengolin added a comment to D49488: [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC).

Thanks for having a look so quickly! Maybe there is a better place to put it, maybe we should keep it local to lib/Transforms/Vectorize/? I initially put it in VectorUtils.h, because I wanted to avoid creating unnecessary new files (and splitting things up unnecessarily), but given that VectorUtils.h is used in quite a few places, I am happy to put it wherever it would fit best :)

Jul 19 2018, 6:27 AM
rengolin added a comment to D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

I'll let Florian/Hideki reply about timeframes and strategies, and will just focus on specific items you list.

Jul 19 2018, 5:17 AM

Jul 18 2018

rengolin added a comment to D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

The fact of the matter is that the loop vectorization has a need to understand SLP and SLP vectorizer needs to understand Loop. As such, unless we want to build/maintain separate LoopVectorize+SLP and SLPVectorize+Loop, consolidation of LoopVectorization and SLPVectorization will inevitably happen sooner or later. From that perspective, ensuring that VPlan is the right infrastructure for such consolidation is a very important thing for us to do.

Jul 18 2018, 12:57 PM
rengolin added a comment to D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

My tuppence...

Jul 18 2018, 11:58 AM
rengolin added a comment to D49488: [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC).

I like the idea of the interleave analysis to be at a higher ground, but we have to be careful with LV-specific logic and only hoist what it truly generic.

Jul 18 2018, 8:41 AM

Jun 21 2018

rengolin added a comment to D48332: [AArch64] Add custom lowering for v4i8 trunc store.

Thanks! I'm happy with Eli is happy. :)

Jun 21 2018, 6:12 AM

Jun 20 2018

rengolin added inline comments to D48332: [AArch64] Add custom lowering for v4i8 trunc store.
Jun 20 2018, 1:11 PM

Jun 19 2018

rengolin added inline comments to D48332: [AArch64] Add custom lowering for v4i8 trunc store.
Jun 19 2018, 1:34 PM

Jun 8 2018

rengolin added reviewers for D47943: Sample code for porting MachinePipeliner to AArch64+SVE: rengolin, t.p.northover, huntergr, sdesmalen, fhahn, qcolombet, MatzeB, sebpop.

Adding some reviewers + folks on the original review:

Jun 8 2018, 7:26 AM

Jun 1 2018

rengolin added a comment to D46283: [AArch64] Set vectorizer-maximize-bandwidth as default true.
401.bzip2-2.04

I will check if 401.bzip2 slight drop is just noise or something related to this patch, but regardless I do think this change should yield better performance in most scenarios.

Jun 1 2018, 6:53 AM

May 31 2018

rengolin added a comment to D47575: [ASAN] Sanitize testsuite for ARM..

I'm guessing this is a fix for: http://lab.llvm.org:8011/builders/clang-cmake-thumbv8-full-sh/builds/185

May 31 2018, 1:58 AM

May 23 2018

rengolin added a comment to D46283: [AArch64] Set vectorizer-maximize-bandwidth as default true.

SPEC06 results look too noisy to conclude anything, especially bzip, xalan and povray. Can you find a more stable machine?

May 23 2018, 6:45 AM

May 18 2018

rengolin added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 18 2018, 7:52 AM
rengolin added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 18 2018, 6:59 AM
rengolin added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 18 2018, 5:25 AM

May 15 2018

rengolin added a comment to D46714: [test-suite] Add list of programs we might add..

It does seem like a wiki would be nice to maintain this kind of information. In the absence of that, I think that a file in the test-suite repository, or a page in www are about equally easy/hard to maintain: it requires commit access to make any changes.
A file in www in theory could be more visible as it becomes part of the llvm.org web pages. That being said, source code is also viewable online, so it's easy to browse this text too.

May 15 2018, 2:20 AM

May 10 2018

rengolin added a comment to D46714: [test-suite] Add list of programs we might add..

I should have clarified: Regarding SPEC, I meant adding CMakeLists in the External directory.

May 10 2018, 1:06 PM
rengolin added a comment to D46714: [test-suite] Add list of programs we might add..

It's odd to have this in the repository, but admittedly we don't really have a wiki or similar in LLVM so I may be ok.

May 10 2018, 1:04 PM
rengolin added a reviewer for D46714: [test-suite] Add list of programs we might add.: maxim-kuvyrkov.

We can't add SPEC, as it's commercial. I'm not sure about others, but please make sure they are open source.

May 10 2018, 12:54 PM

May 4 2018

rengolin accepted D46010: [AArch64] Improve cost of vector division by constant.

LGTM with the line removed. :)

May 4 2018, 11:39 AM
rengolin added a comment to D46010: [AArch64] Improve cost of vector division by constant.

I should not change other architectures than AArch64 because 'isArithmeticDivFast' is a new method (only used by this patch).

May 4 2018, 8:17 AM
rengolin accepted D46302: [LV] Fix for PR37248, Broadcast codegen incorrectly assumed vector loop body is single basic block.

Nice catch! Sorry for the delay, LGTM.

May 4 2018, 1:42 AM

May 1 2018

rengolin accepted D45875: [zorg] Throttle down parallelism of AArch64 and AArch32 libcxx bots.
May 1 2018, 3:25 AM

Apr 30 2018

rengolin added a comment to D46278: [AArch64] Fold B = csel A, A into B = COPY A.

It's not really csel vs. mov; the COPY likely gets coalesced away, and it might allow erasing the condition which feeds the select, which might allow erasing more code, etc.

Apr 30 2018, 2:22 PM
rengolin requested changes to D46283: [AArch64] Set vectorizer-maximize-bandwidth as default true.

[1] [llvm] r305960 - Enable vectorizer-maximize-bandwidth by default. (Dehao)
[llvm] r305990 - Revert "Enable vectorizer-maximize-bandwidth by default." (Diana Picus)
[llvm] r306336 - Enable vectorizer-maximize-bandwidth by default. (Dehao)
[llvm] r306344 - revert r306336 for breaking ppc test. (Dehao)
[llvm] r306473 - re-commit r306336: Enable vectorizer-maximize-bandwidth by default. (Dehao)
[llvm] r306792 - Revert "r306473 - re-commit r306336: Enable vectorizer-maximize-bandwidth by default." (Daniel)
[llvm] r306933 - Enable vectorizer-maximize-bandwidth by default.
[llvm] r306934 - revert r306336 for breaking ppc test.
[llvm] r306935 - re-commit r306336: Enable vectorizer-maximize-bandwidth by default.
[llvm] r306936 - Revert "r306473 - re-commit r306336: Enable vectorizer-maximize-bandwidth by default."

Apr 30 2018, 2:17 PM
rengolin added a comment to D46278: [AArch64] Fold B = csel A, A into B = COPY A.

This does look like a heavy hammer for a small fix. From the optimisation guides, CSEL and MOV have the same latency/bandwidth and the condition is probably pipelined in anyway.

Apr 30 2018, 1:50 PM
rengolin added a reviewer for D46283: [AArch64] Set vectorizer-maximize-bandwidth as default true: mcrosier.

This seems like an improvement, but we have to be careful with wide variations and little gain. The geomean is almost null but the standard deviation is higher than 75% of the results.

Apr 30 2018, 1:47 PM
rengolin added a comment to D45552: [NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file.

There seems like a disconnect.

Apr 30 2018, 1:27 PM
rengolin added a comment to D46254: [LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC)..

We need to consciously try using (or even creating) generically reusable code like this, instead of each file having it's own "skip this, skip that".

Apr 30 2018, 1:13 PM · debug-info