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rengolin (Renato Golin)
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User Since
Oct 19 2012, 12:57 AM (325 w, 5 d)

Recent Activity

Thu, Jan 10

rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

Perhaps best to ping Clang's commit, as that's the review that is blocking this one.

Thu, Jan 10, 2:07 AM

Wed, Dec 19

rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

Thanks! I've updated the reviewers on the Clang review (D53928).

Wed, Dec 19, 7:26 AM
rengolin added reviewers for D53928: Enable builtins necessary for SLEEF [AArch64] vectorized trigonometry libm functions: rsmith, chandlerc, rnk, ABataev.

Adding clang/omp developers for proper review. Please feel free to add more.

Wed, Dec 19, 7:16 AM

Mon, Dec 17

rengolin requested changes to D55445: [cmake] Update config.guess to gnuconfig git 2018-12-07.

If you git log cmake/config.guess you'll see that all the past changes either remove functionality or add obvious parts that shouldn't inflict on copyright.

Mon, Dec 17, 5:06 AM

Dec 14 2018

rengolin accepted D53816: [TableGen:AsmWriter] Cope with consecutive tied operands..

Right, that's all very hypothetical, but the change is harmless otherwise and generally an improvement of the code. I can't see any impact this would have in code generation or compilation time, so LGTM.

Dec 14 2018, 3:39 AM
rengolin updated subscribers of D55427: [libcxx] Call __count_bool_true for bitset count.

Getting a bit late in this discussion, as we had an internal one just recently.

Dec 14 2018, 3:16 AM

Dec 13 2018

rengolin added a comment to D53349: [VPlan] Changes to implement VPlan based predication for VPlan-native path..

Right, I'm happy with the patch and will let @fhahn do the final review and approval. Thanks!

Dec 13 2018, 3:21 AM

Dec 12 2018

rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

Where, when, how and by whom are these #pragmas inserted? Are they silently inserted by clang? Do they have to be manually inserted in existing code?
What is the effect of these #pragmas? The ARM closed-source commercial compiler requires OpenMP. How will these #pragmas be implemented in the open-source clang? Will they import OpenMP interfaces in the open-source clang as well?
If importing OpenMP interfaces is not triggered by the insertion of these #pragmas, why is the argument to -fveclib called 'openmp'? I would find it baffling to have to type -fveclib=openmp on compile-line, but ending up not using OpenMP.

I think you should post these questions as a reply to the RFC.

Dec 12 2018, 2:03 AM
rengolin added a comment to D53349: [VPlan] Changes to implement VPlan based predication for VPlan-native path..

As a starting point, this sure looks good to me. Thanks!

Dec 12 2018, 1:54 AM

Dec 11 2018

rengolin added inline comments to D53927: [AArch64] Enable libm vectorized functions via SLEEF.
Dec 11 2018, 2:15 PM
rengolin added inline comments to D53927: [AArch64] Enable libm vectorized functions via SLEEF.
Dec 11 2018, 1:55 PM
rengolin added a comment to D54412: [RFC] Re-implementing -fveclib with OpenMP.

Is there a document that explains how to submit an RFC?

Dec 11 2018, 1:34 PM
rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

Then they are in trouble with a hypothetical distro SLEEF.

That's because no commercial distro - if they ever decide to include SLEEF - will compile SLEEF for the maximum CPU feature-set possible. They do the exact opposite - they compile it for the lowest possible common denominator.

For example, on AArch64, you won't get distro libraries compiled specifically for -mcpu=thunderx2t99. Or on x86_64 you'll never get -mavx512ifma, for example.

Dec 11 2018, 10:01 AM
rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

I am taking it on faith that SLEEF won't keep changing their mangling and ABI.
AFAICS, SLEEF isn't included in any Linux distro. I can't find any reference to it in RH/CentOS/Fedora, or at rpmfind. Or Ubuntu or SuSE.

Dec 11 2018, 8:39 AM
rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

Today, we don't have SVE, so we don't generate SVE bindings, all fine. Say, next year you upstream SVE bindings in SLEEF and then change LLVM to emit those too.

SLEEF already has support for SVE.

Dec 11 2018, 7:06 AM
rengolin added reviewers for D54412: [RFC] Re-implementing -fveclib with OpenMP: hfinkel, rengolin, hsaito.
Dec 11 2018, 7:05 AM
rengolin added a comment to D53927: [AArch64] Enable libm vectorized functions via SLEEF.

Overall, this change looks ok to me. The tests look good, too.

Dec 11 2018, 4:29 AM

Dec 7 2018

rengolin added a comment to D55445: [cmake] Update config.guess to gnuconfig git 2018-12-07.

One would hope someone would have done similar work on a compatible license, after all these years...

I don't think that's likely to happen, given the very narrow use of this script and how complex it logic is. I think it would take tremendous effort to reinvent all those hacks from scratch, and it would be hard to prove the work was done independently without violating copyright.

Dec 7 2018, 11:45 AM
rengolin added reviewers for D55445: [cmake] Update config.guess to gnuconfig git 2018-12-07: lattner, chandlerc, echristo.

Adding more folks due to the license issue.

Dec 7 2018, 9:57 AM

Dec 5 2018

rengolin committed rL348364: Revert: Honor -fdebug-prefix-map when creating function names for the debug….
Revert: Honor -fdebug-prefix-map when creating function names for the debug…
Dec 5 2018, 6:00 AM
rengolin committed rC348364: Revert: Honor -fdebug-prefix-map when creating function names for the debug….
Revert: Honor -fdebug-prefix-map when creating function names for the debug…
Dec 5 2018, 6:00 AM

Dec 3 2018

rengolin accepted D54853: [ARM][MC] Move information about variadic register defs into tablegen.

Right, that one is a hairy test, and I can see how this would break that test if not right. :)

Dec 3 2018, 2:07 AM

Dec 1 2018

rengolin accepted D54852: [ARM][Asm] Debug trace for the processInstruction loop.

That's very useful, thanks! LGTM.

Dec 1 2018, 12:01 PM
rengolin added a comment to D54853: [ARM][MC] Move information about variadic register defs into tablegen.

Nice clean solution, thanks!

Dec 1 2018, 11:59 AM

Nov 30 2018

rengolin committed rL347990: Fix parenthesis warning in IVDescriptors.
Fix parenthesis warning in IVDescriptors
Nov 30 2018, 5:57 AM
rengolin committed rL347989: Add a new reduction pattern match.
Add a new reduction pattern match
Nov 30 2018, 5:43 AM
rengolin closed D54464: Add a new reduction pattern match.
Nov 30 2018, 5:43 AM
rengolin accepted D54464: Add a new reduction pattern match.

Accepting as this seems to fix the fast-math issue that was the reason why we reverted. Let me know if this still breaks things.

Nov 30 2018, 5:42 AM

Nov 25 2018

rengolin added reviewers for D54386: Disable for new Linux OS runs: upload test traces: labath, omjavaid.

This makes sense to me, but I'm not well versed in LLDB testing. Adding Pavel and Omair to approve it.

Nov 25 2018, 9:54 AM · Restricted Project

Nov 23 2018

rengolin added a comment to D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.

LGTM, do we have any tests for llvm-mc output?

Nov 23 2018, 6:17 AM

Nov 21 2018

rengolin added a reviewer for D54791: [AArch64] Fix disassembly of SXTL and UXTL aliases: t.p.northover.

I'm not sure what's the supposed behaviour on Apple syntax, but the tests show both apple and eabi syntax changing to the recommended encoding, so this LGTM.

Nov 21 2018, 6:27 AM

Nov 14 2018

rengolin updated subscribers of D54464: Add a new reduction pattern match.

@Carrot, can you check if this fixes the fast math issues on your side, please?

Nov 14 2018, 6:53 AM

Nov 13 2018

rengolin accepted D54378: Add Hurd triplet to LLVMSupport.
Nov 13 2018, 11:26 PM
rengolin accepted D49489: [VPlan] VPlan version of InterleavedAccessInfo..

Perfect, LGTM. Thanks!

Nov 13 2018, 6:46 AM
rengolin added a comment to D49489: [VPlan] VPlan version of InterleavedAccessInfo..

So, IIUC, the way you only get the interleave info on instructions and map to VPlan is because we don't yet have scalar evolution in VPlan, so we need to do that in Instruction and then map to VPInstruction.

Nov 13 2018, 5:04 AM

Nov 12 2018

rengolin accepted D49491: [RFC][VPlan, SLP] Add simple SLP analysis on top of VPlan..

Just had a look again and it's looking great, thanks Florian!

Nov 12 2018, 12:53 PM

Nov 10 2018

rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I really do find the break with convention here somewhat deeply unfortunate. It makes parsing and recognizing triples reliably much harder IMO. This really should be 'hurd-gnu' or 'mach-gnu' (or however you want to spell the 'OS' here).

Nov 10 2018, 9:09 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

That's not to say I'm against adding support for GNU Hurd, I'm moreso implying that regardless of what GNU Hurd guidelines say, if they may cause problems in LLVM ecosystem, especially as far as core targets (or rather platforms) go, you have to consider the large ecosystems that use Clang and LLVM and sometimes adapt to avoid causing issues downstream (for example with distro vendors with Glibc/GNU Linux being the core of main variations of server and desktop Linux distros).

Nov 10 2018, 8:56 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

To be honest, I hadn't even imagined that the patch could have consequences on non-Hurd systems.

Nov 10 2018, 8:54 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

Is that really supposed to work? I thought the rules was that the cpu parts and the vendor parts mustn't contain '-', and thus the splitting is never ambiguous, and the os part can contain '-' (heavily used by GNU/Linux, GNU/kFreeBSD, etc.)

Nov 10 2018, 8:24 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

Well, it definitely is for GNU/Hurd, now that very basic software pieces such as librsvg start _depending_ on rust, which is available only through llvm.

Nov 10 2018, 8:12 AM
rengolin requested changes to D54378: Add Hurd triplet to LLVMSupport.

Yes but my concern comes from possible confusion with Glibc based Linux targets which are one of the "main" targets supported by LLVM. Either adding hurd or mach somewhere would be sufficient to disambiguate it from others, and yes I'm aware that they have a somewhat free format but they convey some sort of information, ie. with Linux targets gnu implies GNU/Glibc-based userland, so going by that convention one could easily assume that said triple simply implies GNU/Glibc/ELF userland. I think simply using gnu is too ambiguous, especially considering this is being added as an experimental target.

Nov 10 2018, 7:49 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I understand your concerns, but that's really not something that we can change at this point, there is far too much software which has written i386-pc-gnu in their source code for us to change all that.

Nov 10 2018, 7:46 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I'm not sure how GCC does it but this seems pretty out of line in comparison to all other targets, GNU makes sense to indicate that the target uses a GNU (usually with Glibc) userland but there's no indication of the kernel, which would be something like mk or mach. In which case I think i386-pc-mach-gnu or something along the lines would make sense, unless this is absolutely needed for compatibility reasons?

Nov 10 2018, 6:21 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

(I can not commit this myself)

Nov 10 2018, 5:57 AM
rengolin accepted D54378: Add Hurd triplet to LLVMSupport.

The GNU/Hurd triple is target-gnu, simply.

Nov 10 2018, 5:46 AM
rengolin added a comment to D54378: Add Hurd triplet to LLVMSupport.

I had no idea Hurd was still alive, but hey!

Nov 10 2018, 5:38 AM

Nov 8 2018

rengolin committed rL346396: Adding Yvan as release test backup for Diana.
Adding Yvan as release test backup for Diana
Nov 8 2018, 3:53 AM

Nov 3 2018

rengolin added a comment to D53137: Scalable type size queries (llvm).

This looks ok to me, but I'd rather more people look at it before approving.

Nov 3 2018, 6:46 AM

Oct 31 2018

rengolin added inline comments to D53695: Scalable VectorType RFC.
Oct 31 2018, 6:49 AM

Oct 30 2018

rengolin added reviewers for D53816: [TableGen:AsmWriter] Cope with consecutive tied operands.: atanasyan, asb, jholewinski, t.p.northover, kparzysz, craig.topper, stoklund.

Right, I don't see anything wrong with it, but I'm adding other back-end maintainers and Jakob, TableGen's maintainer, so we're sure this is as harmless as I seem to think it is. :)

Oct 30 2018, 4:48 AM
rengolin added a comment to D53816: [TableGen:AsmWriter] Cope with consecutive tied operands..

Hi Simon,

Oct 30 2018, 2:54 AM

Oct 27 2018

rengolin added a comment to D49168: [LV] Add a new reduction pattern match.

Reverted in r345465. Will take a look and land again when fixed. Thanks!

Oct 27 2018, 3:16 PM
rengolin committed rL345465: Revert r344172: [LV] Add a new reduction pattern match.
Revert r344172: [LV] Add a new reduction pattern match
Oct 27 2018, 3:16 PM

Oct 26 2018

rengolin added a comment to D49168: [LV] Add a new reduction pattern match.

This patch doesn't correctly handle isFast(). By default isRecurrenceInstr() should check I->isFast(), but for this pattern I is Select, isFast() doesn't apply to it, it should be checked against FAdd/FMul inside isConditionalRdxPattern().

Oct 26 2018, 3:54 PM
rengolin added a comment to D53695: Scalable VectorType RFC.

This is looking good to me, thanks!

Oct 26 2018, 4:12 AM

Oct 23 2018

rengolin accepted D46714: [test-suite] Add list of programs we might add..

I also have a list somewhere, that I will add once I find it.

Oct 23 2018, 12:24 PM

Oct 20 2018

rengolin added a comment to D53355: Introducing VPPHINode .

Hi Nikolay,

Oct 20 2018, 8:17 AM

Oct 16 2018

rengolin committed rL344599: [VPlan] Script to extract VPlan digraphs from log.
[VPlan] Script to extract VPlan digraphs from log
Oct 16 2018, 2:40 AM
rengolin closed D53142: [VPlan] Script to extract VPlan digraphs from log.
Oct 16 2018, 2:40 AM

Oct 15 2018

rengolin added a comment to D53142: [VPlan] Script to extract VPlan digraphs from log.

(very gentle ping) :)

Oct 15 2018, 10:45 AM

Oct 12 2018

rengolin updated the diff for D53142: [VPlan] Script to extract VPlan digraphs from log.

Consistent messages.

Oct 12 2018, 3:20 AM
rengolin added inline comments to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.
Oct 12 2018, 1:34 AM

Oct 11 2018

rengolin added a comment to D53146: [MC][ELF] fix newly added test.

Oh, you've done that. The diff isn't clear.

Oct 11 2018, 11:04 AM
rengolin added a comment to D53146: [MC][ELF] fix newly added test.

The failure in Arm had nothing to do with not being ELF, but the asm syntax was different.

Oct 11 2018, 11:04 AM
rengolin added a comment to D53142: [VPlan] Script to extract VPlan digraphs from log.

I'm wondering... should we choose between dot and png? Or should we always print the dot file and, upon --png flag, also the png file?

Oct 11 2018, 10:25 AM
rengolin updated the diff for D53142: [VPlan] Script to extract VPlan digraphs from log.

Thanks Florian, your regex version is still easy to use and much cleaner.

Oct 11 2018, 10:16 AM
rengolin updated the diff for D53142: [VPlan] Script to extract VPlan digraphs from log.

Hi Florian,

Oct 11 2018, 10:07 AM
rengolin created D53142: [VPlan] Script to extract VPlan digraphs from log.
Oct 11 2018, 9:30 AM

Oct 10 2018

rengolin committed rL344172: [LV] Add a new reduction pattern match.
[LV] Add a new reduction pattern match
Oct 10 2018, 11:51 AM
rengolin closed D49168: [LV] Add a new reduction pattern match.
Oct 10 2018, 11:51 AM
rengolin committed rL344161: [VPlan] Fix CondBit quoting in dumpBasicBlock.
[VPlan] Fix CondBit quoting in dumpBasicBlock
Oct 10 2018, 10:57 AM
rengolin accepted D53091: [LV] Ignore more debug info..

Seems trivial. instructionsWithoutDebug is just an iterator filter and there are no early continues in the body of the outer loop, so this actually saves time.

Oct 10 2018, 10:21 AM
rengolin accepted D53089: [LV] Use SmallVector instead of DenseMap in calculateRegisterUsage (NFC)..

Good catch! LGTM, thanks!

Oct 10 2018, 10:18 AM

Oct 9 2018

rengolin added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

Could also be an architectural flag, giving this is a particular behaviour from Exynos. Then a simple splitsJumpTables() or whatever check would be enough.

Oct 9 2018, 10:04 PM
rengolin added a comment to D32564: AArch64: compress jump tables to minimum size needed to reach destinations.

As you'd expect, size is pretty good. Over the test-suite (including externals) nothing regresses. The total benefit over all the code is 0.5%, with notable highlights of 25% in 401.bzip2, 7% in 403.gcc, and 4% in 177.mesa.

Oct 9 2018, 6:49 AM
rengolin updated the diff for D49168: [LV] Add a new reduction pattern match.

Changes to comment:

  • Improved comments on isConditionalRdxPattern
  • Removed instcombine pass from test
  • Added write negative test
  • Fix typo in CHECK line
Oct 9 2018, 3:08 AM

Oct 8 2018

rengolin added a comment to D49168: [LV] Add a new reduction pattern match.

LGTM. Please wait for a few days to give others time to respond if they'd like to.

Oct 8 2018, 2:40 PM
rengolin added inline comments to D49168: [LV] Add a new reduction pattern match.
Oct 8 2018, 2:05 PM
rengolin updated the summary of D49168: [LV] Add a new reduction pattern match.
Oct 8 2018, 10:16 AM
rengolin updated the diff for D49168: [LV] Add a new reduction pattern match.
Oct 8 2018, 10:16 AM
rengolin commandeered D49168: [LV] Add a new reduction pattern match.

Hi Hideki,

Oct 8 2018, 10:15 AM

Oct 4 2018

rengolin added a comment to D52829: [AArch64] Fix verifier error when outlining indirect calls.

OTOH, having a function flag or something like @rengolin suggested is probably a bit cleaner in the long term. I slightly prefer this position since it seems like it should be the verifier's responsibility to understand what to do with an outlined function. Also, if it does turn out that there are other weird cases, it'd be kind of overkill to add special outlining instructions everywhere just to appease the verifier.

Oct 4 2018, 10:23 AM
rengolin added a comment to D52829: [AArch64] Fix verifier error when outlining indirect calls.

Are there no other ways to identify an outliner function, say a function flag or a needed pattern, so we can change the verifier instead, and not fail when called-saved regs are used?

Oct 4 2018, 2:08 AM

Oct 2 2018

rengolin added a comment to D52784: [ARM][AArch64] Pass through endianness flags to the GNU assembler and linker.

Hi Peter,

Oct 2 2018, 8:15 AM

Oct 1 2018

rengolin added a comment to D52149: add support functions for hard/soft float multilib distinction.

There's no intent to revert

Oct 1 2018, 4:40 AM
rengolin added a comment to D52149: add support functions for hard/soft float multilib distinction.

I think it's okay to land this for convenience for now (once the issues are addressed) and if the Clang differential does not get approved revert this, which is not especially difficult since the support lib is quite isolated.

Oct 1 2018, 4:09 AM
rengolin added reviewers for D52149: add support functions for hard/soft float multilib distinction: olista01, echristo, raj.khem, sdardis.

Adding more people that work around triples...

Oct 1 2018, 3:38 AM
rengolin added a comment to D52149: add support functions for hard/soft float multilib distinction.

This is a slight duplication of what we already have in ARMSubtarget.h, and given that this is *only* relevant for AArch32, I see no point in this being in the Triple.

Oct 1 2018, 3:36 AM
rengolin requested changes to D52149: add support functions for hard/soft float multilib distinction.
Oct 1 2018, 3:36 AM

Sep 27 2018

rengolin added a comment to D18086: Fix default processor name for armv6k..

The other two reviews were approved. This one can now be closed. Thanks!

Sep 27 2018, 8:53 AM
rengolin accepted D52595: [ARM] Alter test to account for change to armv6k default CPU.

Thanks Peter. LGTM!

Sep 27 2018, 8:52 AM
rengolin accepted D52594: [ARM] Remove non-existent cpu arm1176j-s and use mpcore for v6k.

Thanks Peter! LGTM.

Sep 27 2018, 8:51 AM

Sep 14 2018

rengolin added a comment to D18086: Fix default processor name for armv6k..

Corrections are always welcome. Please submit an update to this thread (or a new patch) to fix the changes you propose.

Sep 14 2018, 6:07 AM
rengolin added a comment to D18086: Fix default processor name for armv6k..

If j-s doesn't exists (remember, most of that list came from the ancient days of llvm, so could very easily be completely wrong, but "works"), I all for removing it and making a new (correct) CPU name as the default for armv6k.

Sep 14 2018, 4:45 AM

Sep 13 2018

rengolin added inline comments to D18086: Fix default processor name for armv6k..
Sep 13 2018, 12:50 PM
rengolin added a comment to D18086: Fix default processor name for armv6k..

I seem to have a related issue: I am using -march=armv6k and -no-integrated-as, this generates the following output:
/tmp/empty-bc2ea3.s:4: Error: unknown cpu `arm1176j-s'

Sep 13 2018, 11:40 AM

Sep 11 2018

rengolin accepted D49488: [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC).

Thanks Florian! LGTM too.

Sep 11 2018, 9:02 AM

Aug 30 2018

rengolin added a comment to D51465: Revamp test-suite documentation.

Very detailed, using the modern infrastructure and helpful even to those not using clang or wanting to run external benchmarks.

Aug 30 2018, 2:59 AM

Jul 19 2018

rengolin added reviewers for D49563: [ARM] Add new target feature to fuse literal generation: efriedma, SjoerdMeijer, peter.smith, thopre, kristof.beyls, aadg.

I shall, at least for Exynos, but I'd like to hear from our friends at ARM too.

Jul 19 2018, 1:22 PM