[RISCV] Add vadd with mask and without mask builtin.

[HsiangKai]

Summary

Demonstrate how to add RISC-V V builtins and lower them to IR intrinsics for V extension.

Authored-by: Roger Ferrer Ibanez <[e-mail]>
Co-Authored-by: Hsiangkai Wang <[e-mail]>

[HsiangKai]

Update test cases to include rv32 target.

[craig.topper]

clang/lib/CodeGen/CGBuiltin.cpp

17940

I think this whole sequence is equivalent to

std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);

[HsiangKai]

Address @craig.topper's comments.

[khchen]

clang/lib/Basic/Targets/RISCV.cpp

283

HasRISCVVTypes is an undefined variable?

[HsiangKai]

clang/lib/Basic/Targets/RISCV.cpp

283

I should move the snippet to D92715.

[HsiangKai]

Address @khchen's comments.

[HsiangKai]

D95016 focuses on the Clang RVV builtin generator and it depends on this commit. I know it is clumsy to list the combinations for vadd plainly, but it is a simple way to demonstrate how to add RVV builtins in Clang. Could we accept this patch and D92715 first if there is no concern about these two patches?

[HsiangKai]

Rebase.

[Jim]

clang/test/CodeGen/RISCV/vadd.c

23

Is it necessary with prefix "__builtin_"?
Refer to https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv_intrinsic_funcs_vl/06_vector_integer_arithmetic_functions.md.

[jrtc27]

clang/test/CodeGen/RISCV/vadd.c

23

rvvintrin.h or whatever it's called will define wrappers. Providing things under a name that's not prefixed by __ can cause collisions with existing code that's not trying to use these intrinsics, since the names are technically available for it to use, though in practice that seems extremely unlikely for these names. However, using proper __-prefixed names is convention, as is using __builtin_ for anything that's a compiler builtin. This is purely an implementation detail that the user should not need to care about unless they want to not include the header they're meant to include, at which point we provide no guarantees.

[Jim]

clang/include/clang/Basic/DiagnosticSemaKinds.td

11139

Add blank line.
Is it "err_riscvv_builtin_not_enabled"?

clang/lib/Basic/Targets/RISCV.cpp

89

Builtins for other extension don't have "__builtin_rvv_" prefix.

[khchen]

clang/lib/Basic/Targets/RISCV.cpp

89

maybe we could rename BuiltinsRISCV.def as BuiltinsRVV.def, and other extension defines their own .def file?

@Jim do you have any suggestion?

[craig.topper]

clang/lib/Basic/Targets/RISCV.cpp

89

Don't most targets pass the full name with the prefix to the BUILTIN macro?

[Jim]

clang/lib/Basic/Targets/RISCV.cpp

89

Most of targets pass the full name with the prefix to the BUILTIN macro.
It can define the full name with the prefix in BuiltinsRISCV.def

[HsiangKai]

Address @Jim's comments.

[HsiangKai]

clang/include/clang/Basic/DiagnosticSemaKinds.td

11139

I use the name that is defined in BSC version. It makes sense to me that it means "the risc-v V builtins are not useable."

@rogfer01, do you have any opinion on it?

[Jim]

clang/lib/Basic/Targets/RISCV.cpp

89

Should it put together with getTargetBuiltins function?

[HsiangKai]

Move BuiltinInfo closed to getTargetBuiltins.

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

2

Need copyright header

clang/include/clang/Basic/DiagnosticSemaKinds.td

11139

I'm not sure that's the right spelling of useable. It can also be spelled usable. But it doesn't appear in the message so maybe the name should be closer to wording of the message? Maybe err_riscv_builtin_requires_v. That makes it like err_mips_builtin_requires_dsp

[HsiangKai]

Address @craig.topper's comments.

[craig.topper]

LGTM

clang/include/clang/Basic/BuiltinsRISCV.def

+//==- BuiltinsRISCV.def - RISC-V Builtin function database -------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the RISC-V-specific builtin function database.  Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+#if defined(BUILTIN) && !defined(RISCVV_BUILTIN)
+#define RISCVV_BUILTIN(ID, TYPE, ATTRS) BUILTIN(ID, TYPE, ATTRS)
+#endif
+
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m1_vl, "q8Scq8Scq8Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m1_m_vl, "q8Scq8bq8Scq8Scq8Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m1_vl, "q4Ssq4Ssq4Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m1_m_vl, "q4Ssq4bq4Ssq4Ssq4Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m1_vl, "q2Siq2Siq2Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m1_m_vl, "q2Siq2bq2Siq2Siq2Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m1_vl, "q1SWiq1SWiq1SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiq1SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m2_vl, "q16Scq16Scq16Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m2_m_vl, "q16Scq16bq16Scq16Scq16Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m2_vl, "q8Ssq8Ssq8Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m2_m_vl, "q8Ssq8bq8Ssq8Ssq8Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m2_vl, "q4Siq4Siq4Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m2_m_vl, "q4Siq4bq4Siq4Siq4Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m2_vl, "q2SWiq2SWiq2SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiq2SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m4_vl, "q32Scq32Scq32Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m4_m_vl, "q32Scq32bq32Scq32Scq32Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m4_vl, "q16Ssq16Ssq16Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m4_m_vl, "q16Ssq16bq16Ssq16Ssq16Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m4_vl, "q8Siq8Siq8Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m4_m_vl, "q8Siq8bq8Siq8Siq8Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m4_vl, "q4SWiq4SWiq4SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiq4SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m8_vl, "q64Scq64Scq64Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8m8_m_vl, "q64Scq64bq64Scq64Scq64Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m8_vl, "q32Ssq32Ssq32Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16m8_m_vl, "q32Ssq32bq32Ssq32Ssq32Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m8_vl, "q16Siq16Siq16Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32m8_m_vl, "q16Siq16bq16Siq16Siq16Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m8_vl, "q8SWiq8SWiq8SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiq8SWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8mf2_vl, "q4Scq4Scq4Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8mf2_m_vl, "q4Scq4bq4Scq4Scq4Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16mf2_vl, "q2Ssq2Ssq2Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16mf2_m_vl, "q2Ssq2bq2Ssq2Ssq2Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32mf2_vl, "q1Siq1Siq1Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i32mf2_m_vl, "q1Siq1bq1Siq1Siq1Siz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8mf4_vl, "q2Scq2Scq2Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8mf4_m_vl, "q2Scq2bq2Scq2Scq2Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16mf4_vl, "q1Ssq1Ssq1Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i16mf4_m_vl, "q1Ssq1bq1Ssq1Ssq1Ssz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8mf8_vl, "q1Scq1Scq1Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_i8mf8_m_vl, "q1Scq1bq1Scq1Scq1Scz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m1_vl, "q8Scq8ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m1_m_vl, "q8Scq8bq8Scq8ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m1_vl, "q4Ssq4SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m1_m_vl, "q4Ssq4bq4Ssq4SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m1_vl, "q2Siq2SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m1_m_vl, "q2Siq2bq2Siq2SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m1_vl, "q1SWiq1SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m1_m_vl, "q1SWiq1bq1SWiq1SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m2_vl, "q16Scq16ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m2_m_vl, "q16Scq16bq16Scq16ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m2_vl, "q8Ssq8SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m2_m_vl, "q8Ssq8bq8Ssq8SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m2_vl, "q4Siq4SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m2_m_vl, "q4Siq4bq4Siq4SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m2_vl, "q2SWiq2SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m2_m_vl, "q2SWiq2bq2SWiq2SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m4_vl, "q32Scq32ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m4_m_vl, "q32Scq32bq32Scq32ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m4_vl, "q16Ssq16SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m4_m_vl, "q16Ssq16bq16Ssq16SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m4_vl, "q8Siq8SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m4_m_vl, "q8Siq8bq8Siq8SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m4_vl, "q4SWiq4SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m4_m_vl, "q4SWiq4bq4SWiq4SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m8_vl, "q64Scq64ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8m8_m_vl, "q64Scq64bq64Scq64ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m8_vl, "q32Ssq32SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16m8_m_vl, "q32Ssq32bq32Ssq32SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m8_vl, "q16Siq16SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32m8_m_vl, "q16Siq16bq16Siq16SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m8_vl, "q8SWiq8SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i64m8_m_vl, "q8SWiq8bq8SWiq8SWiSWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8mf2_vl, "q4Scq4ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8mf2_m_vl, "q4Scq4bq4Scq4ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16mf2_vl, "q2Ssq2SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16mf2_m_vl, "q2Ssq2bq2Ssq2SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32mf2_vl, "q1Siq1SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i32mf2_m_vl, "q1Siq1bq1Siq1SiSiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8mf4_vl, "q2Scq2ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8mf4_m_vl, "q2Scq2bq2Scq2ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16mf4_vl, "q1Ssq1SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i16mf4_m_vl, "q1Ssq1bq1Ssq1SsSsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8mf8_vl, "q1Scq1ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_i8mf8_m_vl, "q1Scq1bq1Scq1ScScz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m1_vl, "q8Ucq8Ucq8Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m1_m_vl, "q8Ucq8bq8Ucq8Ucq8Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m1_vl, "q4Usq4Usq4Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m1_m_vl, "q4Usq4bq4Usq4Usq4Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m1_vl, "q2Uiq2Uiq2Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m1_m_vl, "q2Uiq2bq2Uiq2Uiq2Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m1_vl, "q1UWiq1UWiq1UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m1_m_vl, "q1UWiq1bq1UWiq1UWiq1UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m2_vl, "q16Ucq16Ucq16Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m2_m_vl, "q16Ucq16bq16Ucq16Ucq16Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m2_vl, "q8Usq8Usq8Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m2_m_vl, "q8Usq8bq8Usq8Usq8Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m2_vl, "q4Uiq4Uiq4Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m2_m_vl, "q4Uiq4bq4Uiq4Uiq4Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m2_vl, "q2UWiq2UWiq2UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m2_m_vl, "q2UWiq2bq2UWiq2UWiq2UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m4_vl, "q32Ucq32Ucq32Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m4_m_vl, "q32Ucq32bq32Ucq32Ucq32Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m4_vl, "q16Usq16Usq16Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m4_m_vl, "q16Usq16bq16Usq16Usq16Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m4_vl, "q8Uiq8Uiq8Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m4_m_vl, "q8Uiq8bq8Uiq8Uiq8Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m4_vl, "q4UWiq4UWiq4UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m4_m_vl, "q4UWiq4bq4UWiq4UWiq4UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m8_vl, "q64Ucq64Ucq64Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8m8_m_vl, "q64Ucq64bq64Ucq64Ucq64Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m8_vl, "q32Usq32Usq32Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16m8_m_vl, "q32Usq32bq32Usq32Usq32Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m8_vl, "q16Uiq16Uiq16Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32m8_m_vl, "q16Uiq16bq16Uiq16Uiq16Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m8_vl, "q8UWiq8UWiq8UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u64m8_m_vl, "q8UWiq8bq8UWiq8UWiq8UWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8mf2_vl, "q4Ucq4Ucq4Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8mf2_m_vl, "q4Ucq4bq4Ucq4Ucq4Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16mf2_vl, "q2Usq2Usq2Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16mf2_m_vl, "q2Usq2bq2Usq2Usq2Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32mf2_vl, "q1Uiq1Uiq1Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u32mf2_m_vl, "q1Uiq1bq1Uiq1Uiq1Uiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8mf4_vl, "q2Ucq2Ucq2Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8mf4_m_vl, "q2Ucq2bq2Ucq2Ucq2Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16mf4_vl, "q1Usq1Usq1Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u16mf4_m_vl, "q1Usq1bq1Usq1Usq1Usz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8mf8_vl, "q1Ucq1Ucq1Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vv_u8mf8_m_vl, "q1Ucq1bq1Ucq1Ucq1Ucz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m1_vl, "q8Ucq8UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m1_m_vl, "q8Ucq8bq8Ucq8UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m1_vl, "q4Usq4UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m1_m_vl, "q4Usq4bq4Usq4UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m1_vl, "q2Uiq2UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m1_m_vl, "q2Uiq2bq2Uiq2UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m1_vl, "q1UWiq1UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m1_m_vl, "q1UWiq1bq1UWiq1UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m2_vl, "q16Ucq16UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m2_m_vl, "q16Ucq16bq16Ucq16UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m2_vl, "q8Usq8UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m2_m_vl, "q8Usq8bq8Usq8UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m2_vl, "q4Uiq4UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m2_m_vl, "q4Uiq4bq4Uiq4UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m2_vl, "q2UWiq2UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m2_m_vl, "q2UWiq2bq2UWiq2UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m4_vl, "q32Ucq32UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m4_m_vl, "q32Ucq32bq32Ucq32UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m4_vl, "q16Usq16UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m4_m_vl, "q16Usq16bq16Usq16UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m4_vl, "q8Uiq8UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m4_m_vl, "q8Uiq8bq8Uiq8UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m4_vl, "q4UWiq4UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m4_m_vl, "q4UWiq4bq4UWiq4UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m8_vl, "q64Ucq64UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8m8_m_vl, "q64Ucq64bq64Ucq64UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m8_vl, "q32Usq32UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16m8_m_vl, "q32Usq32bq32Usq32UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m8_vl, "q16Uiq16UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32m8_m_vl, "q16Uiq16bq16Uiq16UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m8_vl, "q8UWiq8UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u64m8_m_vl, "q8UWiq8bq8UWiq8UWiUWiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8mf2_vl, "q4Ucq4UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8mf2_m_vl, "q4Ucq4bq4Ucq4UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16mf2_vl, "q2Usq2UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16mf2_m_vl, "q2Usq2bq2Usq2UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32mf2_vl, "q1Uiq1UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u32mf2_m_vl, "q1Uiq1bq1Uiq1UiUiz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8mf4_vl, "q2Ucq2UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8mf4_m_vl, "q2Ucq2bq2Ucq2UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16mf4_vl, "q1Usq1UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u16mf4_m_vl, "q1Usq1bq1Usq1UsUsz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8mf8_vl, "q1Ucq1UcUcz", "n")
+RISCVV_BUILTIN(__builtin_rvv_vadd_vx_u8mf8_m_vl, "q1Ucq1bq1Ucq1UcUcz", "n")
+
+#undef BUILTIN
+#undef RISCVV_BUILTIN

clang/include/clang/Basic/DiagnosticSemaKinds.td

def err_probability_out_of_range : Error<
    "range [0.0, 1.0]">;
 
 // TCB warnings
 def err_tcb_conflicting_attributes : Error<
   "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
 def warn_tcb_enforcement_violation : Warning<
   "calling %0 is a violation of trusted computing base '%1'">,
   InGroup<DiagGroup<"tcb-enforcement">>;
+
+// RISC-V V-extension
+def err_riscvv_builtin_requires_v : Error<
+   "builtin requires 'V' extension support to be enabled">;
 } // end of sema component.

clang/include/clang/Basic/TargetBuiltins.h

#include "clang/Basic/BuiltinsX86_64.def"
   };
   }
 
   /// VE builtins
   namespace VE {
   enum { LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, LastTSBuiltin };
   }
 
+  /// RISCV builtins
+  namespace RISCV {
+  enum {
+    LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
+#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
+#include "clang/Basic/BuiltinsRISCV.def"
+    LastTSBuiltin
+  };
+  } // namespace RISCV
+
   /// Flags to identify the types for overloaded Neon builtins.
   ///
   /// These must be kept in sync with the flags in utils/TableGen/NeonEmitter.h.
   class NeonTypeFlags {
     enum {
       EltTypeMask = 0xf,
       UnsignedFlag = 0x10,
       QuadFlag = 0x20

clang/include/clang/Sema/Sema.h

private:
   bool CheckX86BuiltinTileDuplicate(CallExpr *TheCall, ArrayRef<int> ArgNums);
   bool CheckX86BuiltinTileRangeAndDuplicate(CallExpr *TheCall,
                                             ArrayRef<int> ArgNums);
   bool CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
                                    CallExpr *TheCall);
   bool CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
                                    CallExpr *TheCall);
   bool CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall);
+  bool CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
+                                     CallExpr *TheCall);
 
   bool SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall);
   bool SemaBuiltinVAStartARMMicrosoft(CallExpr *Call);
   bool SemaBuiltinUnorderedCompare(CallExpr *TheCall);
   bool SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs);
   bool SemaBuiltinComplex(CallExpr *TheCall);
   bool SemaBuiltinVSX(CallExpr *TheCall);
   bool SemaBuiltinOSLogFormat(CallExpr *TheCall);

clang/include/clang/module.modulemap

module Clang_Basic {
   textual header "Basic/BuiltinsHexagon.def"
   textual header "Basic/BuiltinsHexagonDep.def"
   textual header "Basic/BuiltinsHexagonMapCustomDep.def"
   textual header "Basic/BuiltinsLe64.def"
   textual header "Basic/BuiltinsMips.def"
   textual header "Basic/BuiltinsNEON.def"
   textual header "Basic/BuiltinsNVPTX.def"
   textual header "Basic/BuiltinsPPC.def"
+  textual header "Basic/BuiltinsRISCV.def"
   textual header "Basic/BuiltinsSVE.def"
   textual header "Basic/BuiltinsSystemZ.def"
   textual header "Basic/BuiltinsWebAssembly.def"
   textual header "Basic/BuiltinsX86.def"
   textual header "Basic/BuiltinsX86_64.def"
   textual header "Basic/BuiltinsXCore.def"
   textual header "Basic/CodeGenOptions.def"
   textual header "Basic/DiagnosticOptions.def"

clang/lib/Basic/Targets/RISCV.h

protected:
   bool HasZbproposedc = false;
   bool HasZbr = false;
   bool HasZbs = false;
   bool HasZbt = false;
   bool HasZfh = false;
   bool HasZvamo = false;
   bool HasZvlsseg = false;
 
+  static const Builtin::Info BuiltinInfo[];
+
 public:
   RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
     SuitableAlign = 128;
     WCharType = SignedInt;
     WIntType = UnsignedInt;
     HasRISCVVTypes = true;
   }
 
   bool setCPU(const std::string &Name) override {
     if (!isValidCPUName(Name))
       return false;
     CPU = Name;
     return true;
   }
 
   StringRef getABI() const override { return ABI; }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
 
-  ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
+  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::VoidPtrBuiltinVaList;
   }
 
   const char *getClobbers() const override { return ""; }
 
   ArrayRef<const char *> getGCCRegNames() const override;

clang/lib/Basic/Targets/RISCV.cpp

 //===--- RISCV.cpp - Implement RISCV target feature support ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements RISCV TargetInfo objects.
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCV.h"
 #include "clang/Basic/MacroBuilder.h"
+#include "clang/Basic/TargetBuiltins.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/TargetParser.h"
 
 using namespace clang;
 using namespace clang::targets;
 
 ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
   static const char *const GCCRegNames[] = {
case 'A':
     // An address that is held in a general-purpose register.
     Info.setAllowsMemory();
     return true;
   }
 }
 
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
   Builder.defineMacro("__riscv");
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
   StringRef CodeModel = getTargetOpts().CodeModel;
   if (CodeModel == "default")
     CodeModel = "small";
 
   if (CodeModel == "small")
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 
   if (HasZvamo)
     Builder.defineMacro("__riscv_zvamo", "10000");
 
   if (HasZvlsseg)
     Builder.defineMacro("__riscv_zvlsseg", "10000");
 }
 
+const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)                                               \
+  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
+#include "clang/Basic/BuiltinsRISCV.def"
+};
+
+ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
+  return llvm::makeArrayRef(BuiltinInfo, clang::RISCV::LastTSBuiltin -
+                                             Builtin::FirstTSBuiltin);
+}
+
 /// Return true if has this feature, need to sync with handleTargetFeatures.
 bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   return llvm::StringSwitch<bool>(Feature)
       .Case("riscv", true)
       .Case("riscv32", !Is64Bit)
       .Case("riscv64", Is64Bit)
       .Case("m", HasM)
for (const auto &Feature : Features) {
     else if (Feature == "+experimental-zbproposedc")
       HasZbproposedc = true;
     else if (Feature == "+experimental-zbr")
       HasZbr = true;
     else if (Feature == "+experimental-zbs")
       HasZbs = true;
     else if (Feature == "+experimental-zbt")
       HasZbt = true;
     else if (Feature == "+experimental-zfh")
       HasZfh = true;
     else if (Feature == "+experimental-zvamo")
       HasZvamo = true;
     else if (Feature == "+experimental-zvlsseg")
       HasZvlsseg = true;
   }
 
   return true;

clang/lib/CodeGen/CGBuiltin.cpp

 #include "llvm/IR/IntrinsicsAArch64.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsARM.h"
 #include "llvm/IR/IntrinsicsBPF.h"
 #include "llvm/IR/IntrinsicsHexagon.h"
 #include "llvm/IR/IntrinsicsNVPTX.h"
 #include "llvm/IR/IntrinsicsPowerPC.h"
 #include "llvm/IR/IntrinsicsR600.h"
+#include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/IR/IntrinsicsS390.h"
 #include "llvm/IR/IntrinsicsWebAssembly.h"
 #include "llvm/IR/IntrinsicsX86.h"
 #include "llvm/IR/MDBuilder.h"
 #include "llvm/IR/MatrixBuilder.h"
 #include "llvm/Support/ConvertUTF.h"
 #include "llvm/Support/ScopedPrinter.h"
 #include "llvm/Support/X86TargetParser.h"
static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF,
   case llvm::Triple::nvptx:
   case llvm::Triple::nvptx64:
     return CGF->EmitNVPTXBuiltinExpr(BuiltinID, E);
   case llvm::Triple::wasm32:
   case llvm::Triple::wasm64:
     return CGF->EmitWebAssemblyBuiltinExpr(BuiltinID, E);
   case llvm::Triple::hexagon:
     return CGF->EmitHexagonBuiltinExpr(BuiltinID, E);
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue);
   default:
     return nullptr;
   }
 }
 
 Value *CodeGenFunction::EmitTargetBuiltinExpr(unsigned BuiltinID,
                                               const CallExpr *E,
                                               ReturnValueSlot ReturnValue) {
if (IsVectorPredTy(IntrTy->getReturnType()))
       Call = Q2V(Call);
 
     return Call;
   } // default
   } // switch
 
   return nullptr;
 }
+
+Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
+                                             const CallExpr *E,
+                                             ReturnValueSlot ReturnValue) {
+  SmallVector<Value *, 4> Ops;
+  llvm::Type *ResultType = ConvertType(E->getType());
+
+  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
+    Ops.push_back(EmitScalarExpr(E->getArg(i)));
+
+  Intrinsic::ID ID = Intrinsic::not_intrinsic;
+
+  // Required for overloaded intrinsics.
+  llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
+  switch (BuiltinID) {
+  // We could generate all the possible combinations and handling code in
+  // a file and include it here, instead of listing all the builtins plainly.
+  // Something like
+  // #include clang/Basic/RISCVVBuiltinCodeGen.inc
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8mf8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8mf8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8mf8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m1_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m8_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32mf2_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16mf4_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8mf8_vl:
+    // The order of operands is (op1, op2, vl).
+    ID = Intrinsic::riscv_vadd;
+    IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
+    break;
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i64m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i32mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i16mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_i8mf8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i64m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i32mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i16mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_i8mf8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u64m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u32mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u16mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vv_u8mf8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m1_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u64m8_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u32mf2_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u16mf4_m_vl:
+  case RISCV::BI__builtin_rvv_vadd_vx_u8mf8_m_vl:
+    ID = Intrinsic::riscv_vadd_mask;
+    // The order of operands is (mask, maskedoff, op1, op2, vl).
+    IntrinsicTypes = {ResultType, Ops[3]->getType(), Ops[4]->getType()};
+    // The order of intrinsic operands is (maskedoff, op1, op2, mask, vl).
+    std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
+    break;
+  }
+
+  assert(ID != Intrinsic::not_intrinsic);
+
+  llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+  return Builder.CreateCall(F, Ops, "");
+}

clang/lib/CodeGen/CodeGenFunction.h

public:
   llvm::Value *EmitX86BuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitPPCBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitAMDGPUBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitSystemZBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitNVPTXBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
   llvm::Value *EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
                                           const CallExpr *E);
   llvm::Value *EmitHexagonBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
+  llvm::Value *EmitRISCVBuiltinExpr(unsigned BuiltinID, const CallExpr *E,
+                                    ReturnValueSlot ReturnValue);
   bool ProcessOrderScopeAMDGCN(llvm::Value *Order, llvm::Value *Scope,
                                llvm::AtomicOrdering &AO,
                                llvm::SyncScope::ID &SSID);
 
   enum class MSVCIntrin;
   llvm::Value *EmitMSVCBuiltinExpr(MSVCIntrin BuiltinID, const CallExpr *E);
 
   llvm::Value *EmitBuiltinAvailable(const VersionTuple &Version);

clang/lib/Sema/SemaChecking.cpp

case llvm::Triple::x86_64:
     return CheckX86BuiltinFunctionCall(TI, BuiltinID, TheCall);
   case llvm::Triple::ppc:
   case llvm::Triple::ppcle:
   case llvm::Triple::ppc64:
   case llvm::Triple::ppc64le:
     return CheckPPCBuiltinFunctionCall(TI, BuiltinID, TheCall);
   case llvm::Triple::amdgcn:
     return CheckAMDGCNBuiltinFunctionCall(BuiltinID, TheCall);
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    return CheckRISCVBuiltinFunctionCall(TI, BuiltinID, TheCall);
   }
 }
 
 ExprResult
 Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
                                CallExpr *TheCall) {
   ExprResult TheCallResult(TheCall);
 
bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
   // Check that sync scope is a constant literal
   if (!ArgExpr->EvaluateAsConstantExpr(ArgResult1, Context))
     return Diag(ArgExpr->getExprLoc(), diag::err_expr_not_string_literal)
            << ArgExpr->getType();
 
   return false;
 }
 
+bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
+                                         unsigned BuiltinID,
+                                         CallExpr *TheCall) {
+  switch (BuiltinID) {
+  default:
+    break;
+#define BUILTIN(ID, TYPE, ATTRS) case RISCV::BI##ID:
+#include "clang/Basic/BuiltinsRISCV.def"
+    if (!TI.hasFeature("experimental-v"))
+      return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
+             << TheCall->getSourceRange();
+    break;
+  }
+
+  return false;
+}
+
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
                                            CallExpr *TheCall) {
   if (BuiltinID == SystemZ::BI__builtin_tabort) {
     Expr *Arg = TheCall->getArg(0);
     if (Optional<llvm::APSInt> AbortCode = Arg->getIntegerConstantExpr(Context))
       if (AbortCode->getSExtValue() >= 0 && AbortCode->getSExtValue() < 256)
         return Diag(Arg->getBeginLoc(), diag::err_systemz_invalid_tabort_code)
                << Arg->getSourceRange();

clang/test/CodeGen/RISCV/vadd.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:   -O2 -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-RV64-O2 %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \
+// RUN:   -O2 -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-RV32-O2 %s
+
+#include <stddef.h>
+#include <stdint.h>
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ARG_0:%.*]], <vscale x 8 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i32(<vscale x 8 x i8> [[ARG_0:%.*]], <vscale x 8 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_int8m1_t test_vadd_vv_i8m1_vl(__rvv_int8m1_t arg_0, __rvv_int8m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], <vscale x 8 x i8> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i32(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], <vscale x 8 x i8> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_int8m1_t test_vadd_vv_i8m1_m_vl(__rvv_bool8_t arg_0, __rvv_int8m1_t arg_1, __rvv_int8m1_t arg_2, __rvv_int8m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ARG_0:%.*]], <vscale x 4 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i32(<vscale x 4 x i16> [[ARG_0:%.*]], <vscale x 4 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_int16m1_t test_vadd_vv_i16m1_vl(__rvv_int16m1_t arg_0, __rvv_int16m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i16m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], <vscale x 4 x i16> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i32(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], <vscale x 4 x i16> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_int16m1_t test_vadd_vv_i16m1_m_vl(__rvv_bool16_t arg_0, __rvv_int16m1_t arg_1, __rvv_int16m1_t arg_2, __rvv_int16m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i16m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ARG_0:%.*]], <vscale x 2 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i32(<vscale x 2 x i32> [[ARG_0:%.*]], <vscale x 2 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_int32m1_t test_vadd_vv_i32m1_vl(__rvv_int32m1_t arg_0, __rvv_int32m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i32m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], <vscale x 2 x i32> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i32(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], <vscale x 2 x i32> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_int32m1_t test_vadd_vv_i32m1_m_vl(__rvv_bool32_t arg_0, __rvv_int32m1_t arg_1, __rvv_int32m1_t arg_2, __rvv_int32m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i32m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ARG_0:%.*]], <vscale x 1 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i32(<vscale x 1 x i64> [[ARG_0:%.*]], <vscale x 1 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_int64m1_t test_vadd_vv_i64m1_vl(__rvv_int64m1_t arg_0, __rvv_int64m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i64m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], <vscale x 1 x i64> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i32(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], <vscale x 1 x i64> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_int64m1_t test_vadd_vv_i64m1_m_vl(__rvv_bool64_t arg_0, __rvv_int64m1_t arg_1, __rvv_int64m1_t arg_2, __rvv_int64m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i64m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ARG_0:%.*]], <vscale x 16 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i32(<vscale x 16 x i8> [[ARG_0:%.*]], <vscale x 16 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_int8m2_t test_vadd_vv_i8m2_vl(__rvv_int8m2_t arg_0, __rvv_int8m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], <vscale x 16 x i8> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i32(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], <vscale x 16 x i8> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_int8m2_t test_vadd_vv_i8m2_m_vl(__rvv_bool4_t arg_0, __rvv_int8m2_t arg_1, __rvv_int8m2_t arg_2, __rvv_int8m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ARG_0:%.*]], <vscale x 8 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i32(<vscale x 8 x i16> [[ARG_0:%.*]], <vscale x 8 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_int16m2_t test_vadd_vv_i16m2_vl(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i16m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], <vscale x 8 x i16> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i32(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], <vscale x 8 x i16> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_int16m2_t test_vadd_vv_i16m2_m_vl(__rvv_bool8_t arg_0, __rvv_int16m2_t arg_1, __rvv_int16m2_t arg_2, __rvv_int16m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i16m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ARG_0:%.*]], <vscale x 4 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i32(<vscale x 4 x i32> [[ARG_0:%.*]], <vscale x 4 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_int32m2_t test_vadd_vv_i32m2_vl(__rvv_int32m2_t arg_0, __rvv_int32m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i32m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], <vscale x 4 x i32> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i32(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], <vscale x 4 x i32> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_int32m2_t test_vadd_vv_i32m2_m_vl(__rvv_bool16_t arg_0, __rvv_int32m2_t arg_1, __rvv_int32m2_t arg_2, __rvv_int32m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i32m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ARG_0:%.*]], <vscale x 2 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i32(<vscale x 2 x i64> [[ARG_0:%.*]], <vscale x 2 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_int64m2_t test_vadd_vv_i64m2_vl(__rvv_int64m2_t arg_0, __rvv_int64m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i64m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], <vscale x 2 x i64> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i32(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], <vscale x 2 x i64> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_int64m2_t test_vadd_vv_i64m2_m_vl(__rvv_bool32_t arg_0, __rvv_int64m2_t arg_1, __rvv_int64m2_t arg_2, __rvv_int64m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i64m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ARG_0:%.*]], <vscale x 32 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i32(<vscale x 32 x i8> [[ARG_0:%.*]], <vscale x 32 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_int8m4_t test_vadd_vv_i8m4_vl(__rvv_int8m4_t arg_0, __rvv_int8m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], <vscale x 32 x i8> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i32(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], <vscale x 32 x i8> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_int8m4_t test_vadd_vv_i8m4_m_vl(__rvv_bool2_t arg_0, __rvv_int8m4_t arg_1, __rvv_int8m4_t arg_2, __rvv_int8m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ARG_0:%.*]], <vscale x 16 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i32(<vscale x 16 x i16> [[ARG_0:%.*]], <vscale x 16 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_int16m4_t test_vadd_vv_i16m4_vl(__rvv_int16m4_t arg_0, __rvv_int16m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i16m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], <vscale x 16 x i16> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i32(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], <vscale x 16 x i16> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_int16m4_t test_vadd_vv_i16m4_m_vl(__rvv_bool4_t arg_0, __rvv_int16m4_t arg_1, __rvv_int16m4_t arg_2, __rvv_int16m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i16m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ARG_0:%.*]], <vscale x 8 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i32(<vscale x 8 x i32> [[ARG_0:%.*]], <vscale x 8 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_int32m4_t test_vadd_vv_i32m4_vl(__rvv_int32m4_t arg_0, __rvv_int32m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i32m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], <vscale x 8 x i32> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i32(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], <vscale x 8 x i32> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_int32m4_t test_vadd_vv_i32m4_m_vl(__rvv_bool8_t arg_0, __rvv_int32m4_t arg_1, __rvv_int32m4_t arg_2, __rvv_int32m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i32m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ARG_0:%.*]], <vscale x 4 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i32(<vscale x 4 x i64> [[ARG_0:%.*]], <vscale x 4 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_int64m4_t test_vadd_vv_i64m4_vl(__rvv_int64m4_t arg_0, __rvv_int64m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i64m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], <vscale x 4 x i64> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i32(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], <vscale x 4 x i64> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_int64m4_t test_vadd_vv_i64m4_m_vl(__rvv_bool16_t arg_0, __rvv_int64m4_t arg_1, __rvv_int64m4_t arg_2, __rvv_int64m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i64m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ARG_0:%.*]], <vscale x 64 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i32(<vscale x 64 x i8> [[ARG_0:%.*]], <vscale x 64 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_int8m8_t test_vadd_vv_i8m8_vl(__rvv_int8m8_t arg_0, __rvv_int8m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], <vscale x 64 x i8> [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i32(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], <vscale x 64 x i8> [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_int8m8_t test_vadd_vv_i8m8_m_vl(__rvv_bool1_t arg_0, __rvv_int8m8_t arg_1, __rvv_int8m8_t arg_2, __rvv_int8m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ARG_0:%.*]], <vscale x 32 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i32(<vscale x 32 x i16> [[ARG_0:%.*]], <vscale x 32 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_int16m8_t test_vadd_vv_i16m8_vl(__rvv_int16m8_t arg_0, __rvv_int16m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i16m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], <vscale x 32 x i16> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i32(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], <vscale x 32 x i16> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_int16m8_t test_vadd_vv_i16m8_m_vl(__rvv_bool2_t arg_0, __rvv_int16m8_t arg_1, __rvv_int16m8_t arg_2, __rvv_int16m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i16m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ARG_0:%.*]], <vscale x 16 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i32(<vscale x 16 x i32> [[ARG_0:%.*]], <vscale x 16 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_int32m8_t test_vadd_vv_i32m8_vl(__rvv_int32m8_t arg_0, __rvv_int32m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i32m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], <vscale x 16 x i32> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i32(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], <vscale x 16 x i32> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_int32m8_t test_vadd_vv_i32m8_m_vl(__rvv_bool4_t arg_0, __rvv_int32m8_t arg_1, __rvv_int32m8_t arg_2, __rvv_int32m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i32m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ARG_0:%.*]], <vscale x 8 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i32(<vscale x 8 x i64> [[ARG_0:%.*]], <vscale x 8 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_int64m8_t test_vadd_vv_i64m8_vl(__rvv_int64m8_t arg_0, __rvv_int64m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i64m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i64m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], <vscale x 8 x i64> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i64m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i32(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], <vscale x 8 x i64> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_int64m8_t test_vadd_vv_i64m8_m_vl(__rvv_bool8_t arg_0, __rvv_int64m8_t arg_1, __rvv_int64m8_t arg_2, __rvv_int64m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i64m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ARG_0:%.*]], <vscale x 4 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i32(<vscale x 4 x i8> [[ARG_0:%.*]], <vscale x 4 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_int8mf2_t test_vadd_vv_i8mf2_vl(__rvv_int8mf2_t arg_0, __rvv_int8mf2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], <vscale x 4 x i8> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i32(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], <vscale x 4 x i8> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_int8mf2_t test_vadd_vv_i8mf2_m_vl(__rvv_bool16_t arg_0, __rvv_int8mf2_t arg_1, __rvv_int8mf2_t arg_2, __rvv_int8mf2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ARG_0:%.*]], <vscale x 2 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i32(<vscale x 2 x i16> [[ARG_0:%.*]], <vscale x 2 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_int16mf2_t test_vadd_vv_i16mf2_vl(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i16mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], <vscale x 2 x i16> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i32(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], <vscale x 2 x i16> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_int16mf2_t test_vadd_vv_i16mf2_m_vl(__rvv_bool32_t arg_0, __rvv_int16mf2_t arg_1, __rvv_int16mf2_t arg_2, __rvv_int16mf2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i16mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ARG_0:%.*]], <vscale x 1 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i32(<vscale x 1 x i32> [[ARG_0:%.*]], <vscale x 1 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_int32mf2_t test_vadd_vv_i32mf2_vl(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i32mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i32mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], <vscale x 1 x i32> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i32mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i32(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], <vscale x 1 x i32> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_int32mf2_t test_vadd_vv_i32mf2_m_vl(__rvv_bool64_t arg_0, __rvv_int32mf2_t arg_1, __rvv_int32mf2_t arg_2, __rvv_int32mf2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i32mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ARG_0:%.*]], <vscale x 2 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i32(<vscale x 2 x i8> [[ARG_0:%.*]], <vscale x 2 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_int8mf4_t test_vadd_vv_i8mf4_vl(__rvv_int8mf4_t arg_0, __rvv_int8mf4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], <vscale x 2 x i8> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i32(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], <vscale x 2 x i8> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_int8mf4_t test_vadd_vv_i8mf4_m_vl(__rvv_bool32_t arg_0, __rvv_int8mf4_t arg_1, __rvv_int8mf4_t arg_2, __rvv_int8mf4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ARG_0:%.*]], <vscale x 1 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i32(<vscale x 1 x i16> [[ARG_0:%.*]], <vscale x 1 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_int16mf4_t test_vadd_vv_i16mf4_vl(__rvv_int16mf4_t arg_0, __rvv_int16mf4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i16mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i16mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], <vscale x 1 x i16> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i16mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i32(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], <vscale x 1 x i16> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_int16mf4_t test_vadd_vv_i16mf4_m_vl(__rvv_bool64_t arg_0, __rvv_int16mf4_t arg_1, __rvv_int16mf4_t arg_2, __rvv_int16mf4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i16mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8mf8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ARG_0:%.*]], <vscale x 1 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8mf8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i32(<vscale x 1 x i8> [[ARG_0:%.*]], <vscale x 1 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_int8mf8_t test_vadd_vv_i8mf8_vl(__rvv_int8mf8_t arg_0, __rvv_int8mf8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_i8mf8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_i8mf8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], <vscale x 1 x i8> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_i8mf8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i32(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], <vscale x 1 x i8> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_int8mf8_t test_vadd_vv_i8mf8_m_vl(__rvv_bool64_t arg_0, __rvv_int8mf8_t arg_1, __rvv_int8mf8_t arg_2, __rvv_int8mf8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_i8mf8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i32(<vscale x 8 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_int8m1_t test_vadd_vx_i8m1_vl(__rvv_int8m1_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_int8m1_t test_vadd_vx_i8m1_m_vl(__rvv_bool8_t arg_0, __rvv_int8m1_t arg_1, __rvv_int8m1_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i32(<vscale x 4 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_int16m1_t test_vadd_vx_i16m1_vl(__rvv_int16m1_t arg_0, int16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i16m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_int16m1_t test_vadd_vx_i16m1_m_vl(__rvv_bool16_t arg_0, __rvv_int16m1_t arg_1, __rvv_int16m1_t arg_2, int16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i16m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i32(<vscale x 2 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_int32m1_t test_vadd_vx_i32m1_vl(__rvv_int32m1_t arg_0, int32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i32m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_int32m1_t test_vadd_vx_i32m1_m_vl(__rvv_bool32_t arg_0, __rvv_int32m1_t arg_1, __rvv_int32m1_t arg_2, int32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i32m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i32(<vscale x 1 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_int64m1_t test_vadd_vx_i64m1_vl(__rvv_int64m1_t arg_0, int64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i64m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_int64m1_t test_vadd_vx_i64m1_m_vl(__rvv_bool64_t arg_0, __rvv_int64m1_t arg_1, __rvv_int64m1_t arg_2, int64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i64m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i32(<vscale x 16 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_int8m2_t test_vadd_vx_i8m2_vl(__rvv_int8m2_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_int8m2_t test_vadd_vx_i8m2_m_vl(__rvv_bool4_t arg_0, __rvv_int8m2_t arg_1, __rvv_int8m2_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i32(<vscale x 8 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_int16m2_t test_vadd_vx_i16m2_vl(__rvv_int16m2_t arg_0, int16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i16m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_int16m2_t test_vadd_vx_i16m2_m_vl(__rvv_bool8_t arg_0, __rvv_int16m2_t arg_1, __rvv_int16m2_t arg_2, int16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i16m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i32(<vscale x 4 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_int32m2_t test_vadd_vx_i32m2_vl(__rvv_int32m2_t arg_0, int32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i32m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_int32m2_t test_vadd_vx_i32m2_m_vl(__rvv_bool16_t arg_0, __rvv_int32m2_t arg_1, __rvv_int32m2_t arg_2, int32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i32m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i32(<vscale x 2 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_int64m2_t test_vadd_vx_i64m2_vl(__rvv_int64m2_t arg_0, int64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i64m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_int64m2_t test_vadd_vx_i64m2_m_vl(__rvv_bool32_t arg_0, __rvv_int64m2_t arg_1, __rvv_int64m2_t arg_2, int64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i64m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i32(<vscale x 32 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_int8m4_t test_vadd_vx_i8m4_vl(__rvv_int8m4_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_int8m4_t test_vadd_vx_i8m4_m_vl(__rvv_bool2_t arg_0, __rvv_int8m4_t arg_1, __rvv_int8m4_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i32(<vscale x 16 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_int16m4_t test_vadd_vx_i16m4_vl(__rvv_int16m4_t arg_0, int16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i16m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_int16m4_t test_vadd_vx_i16m4_m_vl(__rvv_bool4_t arg_0, __rvv_int16m4_t arg_1, __rvv_int16m4_t arg_2, int16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i16m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i32(<vscale x 8 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_int32m4_t test_vadd_vx_i32m4_vl(__rvv_int32m4_t arg_0, int32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i32m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_int32m4_t test_vadd_vx_i32m4_m_vl(__rvv_bool8_t arg_0, __rvv_int32m4_t arg_1, __rvv_int32m4_t arg_2, int32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i32m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i32(<vscale x 4 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_int64m4_t test_vadd_vx_i64m4_vl(__rvv_int64m4_t arg_0, int64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i64m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_int64m4_t test_vadd_vx_i64m4_m_vl(__rvv_bool16_t arg_0, __rvv_int64m4_t arg_1, __rvv_int64m4_t arg_2, int64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i64m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i32(<vscale x 64 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_int8m8_t test_vadd_vx_i8m8_vl(__rvv_int8m8_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_int8m8_t test_vadd_vx_i8m8_m_vl(__rvv_bool1_t arg_0, __rvv_int8m8_t arg_1, __rvv_int8m8_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i32(<vscale x 32 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_int16m8_t test_vadd_vx_i16m8_vl(__rvv_int16m8_t arg_0, int16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i16m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_int16m8_t test_vadd_vx_i16m8_m_vl(__rvv_bool2_t arg_0, __rvv_int16m8_t arg_1, __rvv_int16m8_t arg_2, int16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i16m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i32(<vscale x 16 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_int32m8_t test_vadd_vx_i32m8_vl(__rvv_int32m8_t arg_0, int32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i32m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_int32m8_t test_vadd_vx_i32m8_m_vl(__rvv_bool4_t arg_0, __rvv_int32m8_t arg_1, __rvv_int32m8_t arg_2, int32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i32m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i32(<vscale x 8 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_int64m8_t test_vadd_vx_i64m8_vl(__rvv_int64m8_t arg_0, int64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i64m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i64m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i64m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_int64m8_t test_vadd_vx_i64m8_m_vl(__rvv_bool8_t arg_0, __rvv_int64m8_t arg_1, __rvv_int64m8_t arg_2, int64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i64m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i32(<vscale x 4 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_int8mf2_t test_vadd_vx_i8mf2_vl(__rvv_int8mf2_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_int8mf2_t test_vadd_vx_i8mf2_m_vl(__rvv_bool16_t arg_0, __rvv_int8mf2_t arg_1, __rvv_int8mf2_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i32(<vscale x 2 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_int16mf2_t test_vadd_vx_i16mf2_vl(__rvv_int16mf2_t arg_0, int16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i16mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_int16mf2_t test_vadd_vx_i16mf2_m_vl(__rvv_bool32_t arg_0, __rvv_int16mf2_t arg_1, __rvv_int16mf2_t arg_2, int16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i16mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i32(<vscale x 1 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_int32mf2_t test_vadd_vx_i32mf2_vl(__rvv_int32mf2_t arg_0, int32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i32mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i32mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i32mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_int32mf2_t test_vadd_vx_i32mf2_m_vl(__rvv_bool64_t arg_0, __rvv_int32mf2_t arg_1, __rvv_int32mf2_t arg_2, int32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i32mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i32(<vscale x 2 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_int8mf4_t test_vadd_vx_i8mf4_vl(__rvv_int8mf4_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_int8mf4_t test_vadd_vx_i8mf4_m_vl(__rvv_bool32_t arg_0, __rvv_int8mf4_t arg_1, __rvv_int8mf4_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i32(<vscale x 1 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_int16mf4_t test_vadd_vx_i16mf4_vl(__rvv_int16mf4_t arg_0, int16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i16mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i16mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i16mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_int16mf4_t test_vadd_vx_i16mf4_m_vl(__rvv_bool64_t arg_0, __rvv_int16mf4_t arg_1, __rvv_int16mf4_t arg_2, int16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i16mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8mf8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8mf8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i32(<vscale x 1 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_int8mf8_t test_vadd_vx_i8mf8_vl(__rvv_int8mf8_t arg_0, int8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_i8mf8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_i8mf8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_i8mf8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_int8mf8_t test_vadd_vx_i8mf8_m_vl(__rvv_bool64_t arg_0, __rvv_int8mf8_t arg_1, __rvv_int8mf8_t arg_2, int8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_i8mf8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ARG_0:%.*]], <vscale x 8 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8.i32(<vscale x 8 x i8> [[ARG_0:%.*]], <vscale x 8 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_uint8m1_t test_vadd_vv_u8m1_vl(__rvv_uint8m1_t arg_0, __rvv_uint8m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], <vscale x 8 x i8> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8.i32(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], <vscale x 8 x i8> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_uint8m1_t test_vadd_vv_u8m1_m_vl(__rvv_bool8_t arg_0, __rvv_uint8m1_t arg_1, __rvv_uint8m1_t arg_2, __rvv_uint8m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ARG_0:%.*]], <vscale x 4 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.nxv4i16.i32(<vscale x 4 x i16> [[ARG_0:%.*]], <vscale x 4 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_uint16m1_t test_vadd_vv_u16m1_vl(__rvv_uint16m1_t arg_0, __rvv_uint16m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u16m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], <vscale x 4 x i16> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.nxv4i16.i32(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], <vscale x 4 x i16> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_uint16m1_t test_vadd_vv_u16m1_m_vl(__rvv_bool16_t arg_0, __rvv_uint16m1_t arg_1, __rvv_uint16m1_t arg_2, __rvv_uint16m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u16m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ARG_0:%.*]], <vscale x 2 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i32(<vscale x 2 x i32> [[ARG_0:%.*]], <vscale x 2 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_uint32m1_t test_vadd_vv_u32m1_vl(__rvv_uint32m1_t arg_0, __rvv_uint32m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u32m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], <vscale x 2 x i32> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32.i32(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], <vscale x 2 x i32> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_uint32m1_t test_vadd_vv_u32m1_m_vl(__rvv_bool32_t arg_0, __rvv_uint32m1_t arg_1, __rvv_uint32m1_t arg_2, __rvv_uint32m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u32m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ARG_0:%.*]], <vscale x 1 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i32(<vscale x 1 x i64> [[ARG_0:%.*]], <vscale x 1 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_uint64m1_t test_vadd_vv_u64m1_vl(__rvv_uint64m1_t arg_0, __rvv_uint64m1_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u64m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], <vscale x 1 x i64> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64.i32(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], <vscale x 1 x i64> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_uint64m1_t test_vadd_vv_u64m1_m_vl(__rvv_bool64_t arg_0, __rvv_uint64m1_t arg_1, __rvv_uint64m1_t arg_2, __rvv_uint64m1_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u64m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ARG_0:%.*]], <vscale x 16 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8.i32(<vscale x 16 x i8> [[ARG_0:%.*]], <vscale x 16 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_uint8m2_t test_vadd_vv_u8m2_vl(__rvv_uint8m2_t arg_0, __rvv_uint8m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], <vscale x 16 x i8> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8.i32(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], <vscale x 16 x i8> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_uint8m2_t test_vadd_vv_u8m2_m_vl(__rvv_bool4_t arg_0, __rvv_uint8m2_t arg_1, __rvv_uint8m2_t arg_2, __rvv_uint8m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ARG_0:%.*]], <vscale x 8 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.nxv8i16.i32(<vscale x 8 x i16> [[ARG_0:%.*]], <vscale x 8 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_uint16m2_t test_vadd_vv_u16m2_vl(__rvv_uint16m2_t arg_0, __rvv_uint16m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u16m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], <vscale x 8 x i16> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.nxv8i16.i32(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], <vscale x 8 x i16> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_uint16m2_t test_vadd_vv_u16m2_m_vl(__rvv_bool8_t arg_0, __rvv_uint16m2_t arg_1, __rvv_uint16m2_t arg_2, __rvv_uint16m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u16m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ARG_0:%.*]], <vscale x 4 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32.i32(<vscale x 4 x i32> [[ARG_0:%.*]], <vscale x 4 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_uint32m2_t test_vadd_vv_u32m2_vl(__rvv_uint32m2_t arg_0, __rvv_uint32m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u32m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], <vscale x 4 x i32> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.nxv4i32.i32(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], <vscale x 4 x i32> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_uint32m2_t test_vadd_vv_u32m2_m_vl(__rvv_bool16_t arg_0, __rvv_uint32m2_t arg_1, __rvv_uint32m2_t arg_2, __rvv_uint32m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u32m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ARG_0:%.*]], <vscale x 2 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.nxv2i64.i32(<vscale x 2 x i64> [[ARG_0:%.*]], <vscale x 2 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_uint64m2_t test_vadd_vv_u64m2_vl(__rvv_uint64m2_t arg_0, __rvv_uint64m2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u64m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], <vscale x 2 x i64> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.nxv2i64.i32(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], <vscale x 2 x i64> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_uint64m2_t test_vadd_vv_u64m2_m_vl(__rvv_bool32_t arg_0, __rvv_uint64m2_t arg_1, __rvv_uint64m2_t arg_2, __rvv_uint64m2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u64m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ARG_0:%.*]], <vscale x 32 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.nxv32i8.i32(<vscale x 32 x i8> [[ARG_0:%.*]], <vscale x 32 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_uint8m4_t test_vadd_vv_u8m4_vl(__rvv_uint8m4_t arg_0, __rvv_uint8m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], <vscale x 32 x i8> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.nxv32i8.i32(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], <vscale x 32 x i8> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_uint8m4_t test_vadd_vv_u8m4_m_vl(__rvv_bool2_t arg_0, __rvv_uint8m4_t arg_1, __rvv_uint8m4_t arg_2, __rvv_uint8m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ARG_0:%.*]], <vscale x 16 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.nxv16i16.i32(<vscale x 16 x i16> [[ARG_0:%.*]], <vscale x 16 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_uint16m4_t test_vadd_vv_u16m4_vl(__rvv_uint16m4_t arg_0, __rvv_uint16m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u16m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], <vscale x 16 x i16> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.nxv16i16.i32(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], <vscale x 16 x i16> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_uint16m4_t test_vadd_vv_u16m4_m_vl(__rvv_bool4_t arg_0, __rvv_uint16m4_t arg_1, __rvv_uint16m4_t arg_2, __rvv_uint16m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u16m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ARG_0:%.*]], <vscale x 8 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.nxv8i32.i32(<vscale x 8 x i32> [[ARG_0:%.*]], <vscale x 8 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_uint32m4_t test_vadd_vv_u32m4_vl(__rvv_uint32m4_t arg_0, __rvv_uint32m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u32m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], <vscale x 8 x i32> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.nxv8i32.i32(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], <vscale x 8 x i32> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_uint32m4_t test_vadd_vv_u32m4_m_vl(__rvv_bool8_t arg_0, __rvv_uint32m4_t arg_1, __rvv_uint32m4_t arg_2, __rvv_uint32m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u32m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ARG_0:%.*]], <vscale x 4 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.nxv4i64.i32(<vscale x 4 x i64> [[ARG_0:%.*]], <vscale x 4 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_uint64m4_t test_vadd_vv_u64m4_vl(__rvv_uint64m4_t arg_0, __rvv_uint64m4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u64m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], <vscale x 4 x i64> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.nxv4i64.i32(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], <vscale x 4 x i64> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_uint64m4_t test_vadd_vv_u64m4_m_vl(__rvv_bool16_t arg_0, __rvv_uint64m4_t arg_1, __rvv_uint64m4_t arg_2, __rvv_uint64m4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u64m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ARG_0:%.*]], <vscale x 64 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i32(<vscale x 64 x i8> [[ARG_0:%.*]], <vscale x 64 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_uint8m8_t test_vadd_vv_u8m8_vl(__rvv_uint8m8_t arg_0, __rvv_uint8m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], <vscale x 64 x i8> [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.nxv64i8.i32(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], <vscale x 64 x i8> [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_uint8m8_t test_vadd_vv_u8m8_m_vl(__rvv_bool1_t arg_0, __rvv_uint8m8_t arg_1, __rvv_uint8m8_t arg_2, __rvv_uint8m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ARG_0:%.*]], <vscale x 32 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.nxv32i16.i32(<vscale x 32 x i16> [[ARG_0:%.*]], <vscale x 32 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_uint16m8_t test_vadd_vv_u16m8_vl(__rvv_uint16m8_t arg_0, __rvv_uint16m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u16m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], <vscale x 32 x i16> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.nxv32i16.i32(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], <vscale x 32 x i16> [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_uint16m8_t test_vadd_vv_u16m8_m_vl(__rvv_bool2_t arg_0, __rvv_uint16m8_t arg_1, __rvv_uint16m8_t arg_2, __rvv_uint16m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u16m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ARG_0:%.*]], <vscale x 16 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.nxv16i32.i32(<vscale x 16 x i32> [[ARG_0:%.*]], <vscale x 16 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_uint32m8_t test_vadd_vv_u32m8_vl(__rvv_uint32m8_t arg_0, __rvv_uint32m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u32m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], <vscale x 16 x i32> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.nxv16i32.i32(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], <vscale x 16 x i32> [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_uint32m8_t test_vadd_vv_u32m8_m_vl(__rvv_bool4_t arg_0, __rvv_uint32m8_t arg_1, __rvv_uint32m8_t arg_2, __rvv_uint32m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u32m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ARG_0:%.*]], <vscale x 8 x i64> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.nxv8i64.i32(<vscale x 8 x i64> [[ARG_0:%.*]], <vscale x 8 x i64> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_uint64m8_t test_vadd_vv_u64m8_vl(__rvv_uint64m8_t arg_0, __rvv_uint64m8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u64m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u64m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], <vscale x 8 x i64> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u64m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.nxv8i64.i32(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], <vscale x 8 x i64> [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_uint64m8_t test_vadd_vv_u64m8_m_vl(__rvv_bool8_t arg_0, __rvv_uint64m8_t arg_1, __rvv_uint64m8_t arg_2, __rvv_uint64m8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u64m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ARG_0:%.*]], <vscale x 4 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8.i32(<vscale x 4 x i8> [[ARG_0:%.*]], <vscale x 4 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_uint8mf2_t test_vadd_vv_u8mf2_vl(__rvv_uint8mf2_t arg_0, __rvv_uint8mf2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], <vscale x 4 x i8> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8.i32(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], <vscale x 4 x i8> [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_uint8mf2_t test_vadd_vv_u8mf2_m_vl(__rvv_bool16_t arg_0, __rvv_uint8mf2_t arg_1, __rvv_uint8mf2_t arg_2, __rvv_uint8mf2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ARG_0:%.*]], <vscale x 2 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.nxv2i16.i32(<vscale x 2 x i16> [[ARG_0:%.*]], <vscale x 2 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_uint16mf2_t test_vadd_vv_u16mf2_vl(__rvv_uint16mf2_t arg_0, __rvv_uint16mf2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u16mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], <vscale x 2 x i16> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.nxv2i16.i32(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], <vscale x 2 x i16> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_uint16mf2_t test_vadd_vv_u16mf2_m_vl(__rvv_bool32_t arg_0, __rvv_uint16mf2_t arg_1, __rvv_uint16mf2_t arg_2, __rvv_uint16mf2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u16mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ARG_0:%.*]], <vscale x 1 x i32> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.nxv1i32.i32(<vscale x 1 x i32> [[ARG_0:%.*]], <vscale x 1 x i32> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_uint32mf2_t test_vadd_vv_u32mf2_vl(__rvv_uint32mf2_t arg_0, __rvv_uint32mf2_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u32mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u32mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], <vscale x 1 x i32> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u32mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.nxv1i32.i32(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], <vscale x 1 x i32> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_uint32mf2_t test_vadd_vv_u32mf2_m_vl(__rvv_bool64_t arg_0, __rvv_uint32mf2_t arg_1, __rvv_uint32mf2_t arg_2, __rvv_uint32mf2_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u32mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ARG_0:%.*]], <vscale x 2 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8.i32(<vscale x 2 x i8> [[ARG_0:%.*]], <vscale x 2 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_uint8mf4_t test_vadd_vv_u8mf4_vl(__rvv_uint8mf4_t arg_0, __rvv_uint8mf4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], <vscale x 2 x i8> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8.i32(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], <vscale x 2 x i8> [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_uint8mf4_t test_vadd_vv_u8mf4_m_vl(__rvv_bool32_t arg_0, __rvv_uint8mf4_t arg_1, __rvv_uint8mf4_t arg_2, __rvv_uint8mf4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ARG_0:%.*]], <vscale x 1 x i16> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.nxv1i16.i32(<vscale x 1 x i16> [[ARG_0:%.*]], <vscale x 1 x i16> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_uint16mf4_t test_vadd_vv_u16mf4_vl(__rvv_uint16mf4_t arg_0, __rvv_uint16mf4_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u16mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u16mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], <vscale x 1 x i16> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u16mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.nxv1i16.i32(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], <vscale x 1 x i16> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_uint16mf4_t test_vadd_vv_u16mf4_m_vl(__rvv_bool64_t arg_0, __rvv_uint16mf4_t arg_1, __rvv_uint16mf4_t arg_2, __rvv_uint16mf4_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u16mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8mf8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ARG_0:%.*]], <vscale x 1 x i8> [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8mf8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8.i32(<vscale x 1 x i8> [[ARG_0:%.*]], <vscale x 1 x i8> [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_uint8mf8_t test_vadd_vv_u8mf8_vl(__rvv_uint8mf8_t arg_0, __rvv_uint8mf8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vv_u8mf8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vv_u8mf8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], <vscale x 1 x i8> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vv_u8mf8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8.i32(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], <vscale x 1 x i8> [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_uint8mf8_t test_vadd_vv_u8mf8_m_vl(__rvv_bool64_t arg_0, __rvv_uint8mf8_t arg_1, __rvv_uint8mf8_t arg_2, __rvv_uint8mf8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vv_u8mf8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i64(<vscale x 8 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.i8.i32(<vscale x 8 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_uint8m1_t test_vadd_vx_u8m1_vl(__rvv_uint8m1_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i64(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.i8.i32(<vscale x 8 x i8> [[ARG_1:%.*]], <vscale x 8 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+__rvv_uint8m1_t test_vadd_vx_u8m1_m_vl(__rvv_bool8_t arg_0, __rvv_uint8m1_t arg_1, __rvv_uint8m1_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i64(<vscale x 4 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.nxv4i16.i16.i32(<vscale x 4 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_uint16m1_t test_vadd_vx_u16m1_vl(__rvv_uint16m1_t arg_0, uint16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u16m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i64(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i16> @llvm.riscv.vadd.mask.nxv4i16.i16.i32(<vscale x 4 x i16> [[ARG_1:%.*]], <vscale x 4 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+__rvv_uint16m1_t test_vadd_vx_u16m1_m_vl(__rvv_bool16_t arg_0, __rvv_uint16m1_t arg_1, __rvv_uint16m1_t arg_2, uint16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u16m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i64(<vscale x 2 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.i32.i32(<vscale x 2 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_uint32m1_t test_vadd_vx_u32m1_vl(__rvv_uint32m1_t arg_0, uint32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u32m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i64(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.i32.i32(<vscale x 2 x i32> [[ARG_1:%.*]], <vscale x 2 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+__rvv_uint32m1_t test_vadd_vx_u32m1_m_vl(__rvv_bool32_t arg_0, __rvv_uint32m1_t arg_1, __rvv_uint32m1_t arg_2, uint32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u32m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m1_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i64(<vscale x 1 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m1_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.i64.i32(<vscale x 1 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_uint64m1_t test_vadd_vx_u64m1_vl(__rvv_uint64m1_t arg_0, uint64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u64m1_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m1_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i64(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m1_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.i64.i32(<vscale x 1 x i64> [[ARG_1:%.*]], <vscale x 1 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+__rvv_uint64m1_t test_vadd_vx_u64m1_m_vl(__rvv_bool64_t arg_0, __rvv_uint64m1_t arg_1, __rvv_uint64m1_t arg_2, uint64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u64m1_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i64(<vscale x 16 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.i8.i32(<vscale x 16 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_uint8m2_t test_vadd_vx_u8m2_vl(__rvv_uint8m2_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i64(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.i8.i32(<vscale x 16 x i8> [[ARG_1:%.*]], <vscale x 16 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
+//
+__rvv_uint8m2_t test_vadd_vx_u8m2_m_vl(__rvv_bool4_t arg_0, __rvv_uint8m2_t arg_1, __rvv_uint8m2_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i64(<vscale x 8 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.nxv8i16.i16.i32(<vscale x 8 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_uint16m2_t test_vadd_vx_u16m2_vl(__rvv_uint16m2_t arg_0, uint16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u16m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i64(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.riscv.vadd.mask.nxv8i16.i16.i32(<vscale x 8 x i16> [[ARG_1:%.*]], <vscale x 8 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
+//
+__rvv_uint16m2_t test_vadd_vx_u16m2_m_vl(__rvv_bool8_t arg_0, __rvv_uint16m2_t arg_1, __rvv_uint16m2_t arg_2, uint16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u16m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i64(<vscale x 4 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.i32.i32(<vscale x 4 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_uint32m2_t test_vadd_vx_u32m2_vl(__rvv_uint32m2_t arg_0, uint32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u32m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i64(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.riscv.vadd.mask.nxv4i32.i32.i32(<vscale x 4 x i32> [[ARG_1:%.*]], <vscale x 4 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
+//
+__rvv_uint32m2_t test_vadd_vx_u32m2_m_vl(__rvv_bool16_t arg_0, __rvv_uint32m2_t arg_1, __rvv_uint32m2_t arg_2, uint32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u32m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i64(<vscale x 2 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.nxv2i64.i64.i32(<vscale x 2 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_uint64m2_t test_vadd_vx_u64m2_vl(__rvv_uint64m2_t arg_0, uint64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u64m2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i64(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.riscv.vadd.mask.nxv2i64.i64.i32(<vscale x 2 x i64> [[ARG_1:%.*]], <vscale x 2 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
+//
+__rvv_uint64m2_t test_vadd_vx_u64m2_m_vl(__rvv_bool32_t arg_0, __rvv_uint64m2_t arg_1, __rvv_uint64m2_t arg_2, uint64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u64m2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i64(<vscale x 32 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.nxv32i8.i8.i32(<vscale x 32 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_uint8m4_t test_vadd_vx_u8m4_vl(__rvv_uint8m4_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i64(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i8> @llvm.riscv.vadd.mask.nxv32i8.i8.i32(<vscale x 32 x i8> [[ARG_1:%.*]], <vscale x 32 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
+//
+__rvv_uint8m4_t test_vadd_vx_u8m4_m_vl(__rvv_bool2_t arg_0, __rvv_uint8m4_t arg_1, __rvv_uint8m4_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i64(<vscale x 16 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.nxv16i16.i16.i32(<vscale x 16 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_uint16m4_t test_vadd_vx_u16m4_vl(__rvv_uint16m4_t arg_0, uint16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u16m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i64(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i16> @llvm.riscv.vadd.mask.nxv16i16.i16.i32(<vscale x 16 x i16> [[ARG_1:%.*]], <vscale x 16 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
+//
+__rvv_uint16m4_t test_vadd_vx_u16m4_m_vl(__rvv_bool4_t arg_0, __rvv_uint16m4_t arg_1, __rvv_uint16m4_t arg_2, uint16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u16m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i64(<vscale x 8 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.nxv8i32.i32.i32(<vscale x 8 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_uint32m4_t test_vadd_vx_u32m4_vl(__rvv_uint32m4_t arg_0, uint32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u32m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i64(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i32> @llvm.riscv.vadd.mask.nxv8i32.i32.i32(<vscale x 8 x i32> [[ARG_1:%.*]], <vscale x 8 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
+//
+__rvv_uint32m4_t test_vadd_vx_u32m4_m_vl(__rvv_bool8_t arg_0, __rvv_uint32m4_t arg_1, __rvv_uint32m4_t arg_2, uint32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u32m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i64(<vscale x 4 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.nxv4i64.i64.i32(<vscale x 4 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_uint64m4_t test_vadd_vx_u64m4_vl(__rvv_uint64m4_t arg_0, uint64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u64m4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i64(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i64> @llvm.riscv.vadd.mask.nxv4i64.i64.i32(<vscale x 4 x i64> [[ARG_1:%.*]], <vscale x 4 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
+//
+__rvv_uint64m4_t test_vadd_vx_u64m4_m_vl(__rvv_bool16_t arg_0, __rvv_uint64m4_t arg_1, __rvv_uint64m4_t arg_2, uint64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u64m4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i64(<vscale x 64 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.i8.i32(<vscale x 64 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_uint8m8_t test_vadd_vx_u8m8_vl(__rvv_uint8m8_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i64(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 64 x i8> @llvm.riscv.vadd.mask.nxv64i8.i8.i32(<vscale x 64 x i8> [[ARG_1:%.*]], <vscale x 64 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 64 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
+//
+__rvv_uint8m8_t test_vadd_vx_u8m8_m_vl(__rvv_bool1_t arg_0, __rvv_uint8m8_t arg_1, __rvv_uint8m8_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i64(<vscale x 32 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.nxv32i16.i16.i32(<vscale x 32 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_uint16m8_t test_vadd_vx_u16m8_vl(__rvv_uint16m8_t arg_0, uint16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u16m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i64(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 32 x i16> @llvm.riscv.vadd.mask.nxv32i16.i16.i32(<vscale x 32 x i16> [[ARG_1:%.*]], <vscale x 32 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 32 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
+//
+__rvv_uint16m8_t test_vadd_vx_u16m8_m_vl(__rvv_bool2_t arg_0, __rvv_uint16m8_t arg_1, __rvv_uint16m8_t arg_2, uint16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u16m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i64(<vscale x 16 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.nxv16i32.i32.i32(<vscale x 16 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_uint32m8_t test_vadd_vx_u32m8_vl(__rvv_uint32m8_t arg_0, uint32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u32m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i64(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i32> @llvm.riscv.vadd.mask.nxv16i32.i32.i32(<vscale x 16 x i32> [[ARG_1:%.*]], <vscale x 16 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 16 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
+//
+__rvv_uint32m8_t test_vadd_vx_u32m8_m_vl(__rvv_bool4_t arg_0, __rvv_uint32m8_t arg_1, __rvv_uint32m8_t arg_2, uint32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u32m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i64(<vscale x 8 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.nxv8i64.i64.i32(<vscale x 8 x i64> [[ARG_0:%.*]], i64 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_uint64m8_t test_vadd_vx_u64m8_vl(__rvv_uint64m8_t arg_0, uint64_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u64m8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u64m8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i64(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u64m8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i64> @llvm.riscv.vadd.mask.nxv8i64.i64.i32(<vscale x 8 x i64> [[ARG_1:%.*]], <vscale x 8 x i64> [[ARG_2:%.*]], i64 [[ARG_3:%.*]], <vscale x 8 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
+//
+__rvv_uint64m8_t test_vadd_vx_u64m8_m_vl(__rvv_bool8_t arg_0, __rvv_uint64m8_t arg_1, __rvv_uint64m8_t arg_2, uint64_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u64m8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i64(<vscale x 4 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.i8.i32(<vscale x 4 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_uint8mf2_t test_vadd_vx_u8mf2_vl(__rvv_uint8mf2_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i64(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.i8.i32(<vscale x 4 x i8> [[ARG_1:%.*]], <vscale x 4 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 4 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
+//
+__rvv_uint8mf2_t test_vadd_vx_u8mf2_m_vl(__rvv_bool16_t arg_0, __rvv_uint8mf2_t arg_1, __rvv_uint8mf2_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i64(<vscale x 2 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.nxv2i16.i16.i32(<vscale x 2 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_uint16mf2_t test_vadd_vx_u16mf2_vl(__rvv_uint16mf2_t arg_0, uint16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u16mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i64(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i16> @llvm.riscv.vadd.mask.nxv2i16.i16.i32(<vscale x 2 x i16> [[ARG_1:%.*]], <vscale x 2 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
+//
+__rvv_uint16mf2_t test_vadd_vx_u16mf2_m_vl(__rvv_bool32_t arg_0, __rvv_uint16mf2_t arg_1, __rvv_uint16mf2_t arg_2, uint16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u16mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32mf2_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i64(<vscale x 1 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32mf2_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.nxv1i32.i32.i32(<vscale x 1 x i32> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_uint32mf2_t test_vadd_vx_u32mf2_vl(__rvv_uint32mf2_t arg_0, uint32_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u32mf2_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u32mf2_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i64(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u32mf2_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i32> @llvm.riscv.vadd.mask.nxv1i32.i32.i32(<vscale x 1 x i32> [[ARG_1:%.*]], <vscale x 1 x i32> [[ARG_2:%.*]], i32 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
+//
+__rvv_uint32mf2_t test_vadd_vx_u32mf2_m_vl(__rvv_bool64_t arg_0, __rvv_uint32mf2_t arg_1, __rvv_uint32mf2_t arg_2, uint32_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u32mf2_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i64(<vscale x 2 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.i8.i32(<vscale x 2 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_uint8mf4_t test_vadd_vx_u8mf4_vl(__rvv_uint8mf4_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i64(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.i8.i32(<vscale x 2 x i8> [[ARG_1:%.*]], <vscale x 2 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 2 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
+//
+__rvv_uint8mf4_t test_vadd_vx_u8mf4_m_vl(__rvv_bool32_t arg_0, __rvv_uint8mf4_t arg_1, __rvv_uint8mf4_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16mf4_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i64(<vscale x 1 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16mf4_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.nxv1i16.i16.i32(<vscale x 1 x i16> [[ARG_0:%.*]], i16 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_uint16mf4_t test_vadd_vx_u16mf4_vl(__rvv_uint16mf4_t arg_0, uint16_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u16mf4_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u16mf4_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i64(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u16mf4_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i16> @llvm.riscv.vadd.mask.nxv1i16.i16.i32(<vscale x 1 x i16> [[ARG_1:%.*]], <vscale x 1 x i16> [[ARG_2:%.*]], i16 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
+//
+__rvv_uint16mf4_t test_vadd_vx_u16mf4_m_vl(__rvv_bool64_t arg_0, __rvv_uint16mf4_t arg_1, __rvv_uint16mf4_t arg_2, uint16_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u16mf4_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8mf8_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i64(<vscale x 1 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i64 [[ARG_2:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8mf8_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.i8.i32(<vscale x 1 x i8> [[ARG_0:%.*]], i8 [[ARG_1:%.*]], i32 [[ARG_2:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_uint8mf8_t test_vadd_vx_u8mf8_vl(__rvv_uint8mf8_t arg_0, uint8_t arg_1, size_t arg_2)
+{
+    return __builtin_rvv_vadd_vx_u8mf8_vl(arg_0, arg_1, arg_2);
+}
+
+// CHECK-RV64-O2-LABEL: @test_vadd_vx_u8mf8_m_vl(
+// CHECK-RV64-O2-NEXT:  entry:
+// CHECK-RV64-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i64(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i64 [[ARG_4:%.*]])
+// CHECK-RV64-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+// CHECK-RV32-O2-LABEL: @test_vadd_vx_u8mf8_m_vl(
+// CHECK-RV32-O2-NEXT:  entry:
+// CHECK-RV32-O2-NEXT:    [[TMP0:%.*]] = tail call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.i8.i32(<vscale x 1 x i8> [[ARG_1:%.*]], <vscale x 1 x i8> [[ARG_2:%.*]], i8 [[ARG_3:%.*]], <vscale x 1 x i1> [[ARG_0:%.*]], i32 [[ARG_4:%.*]])
+// CHECK-RV32-O2-NEXT:    ret <vscale x 1 x i8> [[TMP0]]
+//
+__rvv_uint8mf8_t test_vadd_vx_u8mf8_m_vl(__rvv_bool64_t arg_0, __rvv_uint8mf8_t arg_1, __rvv_uint8mf8_t arg_2, uint8_t arg_3, size_t arg_4)
+{
+    return __builtin_rvv_vadd_vx_u8mf8_m_vl(arg_0, arg_1, arg_2, arg_3, arg_4);
+}