[CallingConv] Generate isCCArgumentReg() predicate via tablegen

[void]

Summary

The purpose of isCCArgumentReg() is to help identify whether a given
register can be used for passing arguments when calling a function. The
initial usage is for the `-fzero-call-used-regs' commandline option,
which can optionally zero out argument registers. We don't care about
the registers used for the return values.

We piggyback off of *CallingConv.td information, which is used to
generate code to allocate a register. Instead of actually allocating a
register, it checks to see if a given register *could* be allocated,
based on the calling convention, and reports "true" if it is one of the
registers in the CC (the opposite of the allocation code, which reports
"false" when the register is allocated).

[arsenm]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

3060

Not sure why you need ArgFlags or are setting inreg here, you need to preserve this from the original IR

[void]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

3060

I should explain better in the commit message what's going on.

The ArgFlags is here because some *CallingConv.td files have custom code in them to check these flags.

What all of this code is doing is simply saying whether or not a register is part of a calling convention. Because of that, I don't need to retain many of the flags and other stuff that's needed when allocating the register.

[void]

Improved the commit message.

[void]

Add override method to BogusRegisterInfo.

[jrtc27]

Revision summary seems to be totally lacking any explanation of what this actually is for. Also how is this meant to interact with architectures like MIPS where return value registers aren't argument registers (v0 and v1); is it meant to include those or not? The name suggests it does, but the old function name suggested it didn't (and was just a stub outside of X86?).

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

73

Spelling

[arsenm]

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

3060

But if the code is checking them, and this is lying to it, what good is it? inreg can change the register/register class used for a parameter

[uweigand]

This seems to add a large amount of code that may duplicate information already available elsewhere. It's hard to say, in particular because I don't quite understand the exact semantics of the new isCallingConvReg. For what registers exactly should this return true? Those that may hold (part of) an argument or return value? Those that hold some platform-specific value like a GOT pointer? Those that may be clobbered by the call?

[void]

• s/isCallingConvReg/isCCArgumentReg/g
• Improve commit message to explain better the purpose of this predicate.

[void]

spelling

[void]

In D120094#3331146, @jrtc27 wrote:

Revision summary seems to be totally lacking any explanation of what this actually is for. Also how is this meant to interact with architectures like MIPS where return value registers aren't argument registers (v0 and v1); is it meant to include those or not? The name suggests it does, but the old function name suggested it didn't (and was just a stub outside of X86?).

I improved the commit message.

You're correct that we don't care about return values here. I changed the predicate's name to better reflect that.

[void]

Accidental commit fixed.

[uweigand]

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

472

This whole series of functions still is quite confusing and seems really pointless to me.

If you want to answer the question: "identify whether a given register can be used for passing arguments when calling a function" on SystemZ, this is very simple: Just look at the existing lists

ELFArgGPRs,  ELFArgFPRs  (for the ELF calling convention)
XPLINK64ArgGPR,  XPLINK64ArgFPRs, XPLINK64ArgVRs (for the XPLINK calling convention)

This will correctly answer the above question without any need for TableGen generated routines or any of this additional code (which looks at those lists anyway, so it isn't even that those would be avoided ...).

[void]

Simplify the SystemZ isCCArgumentReg predicate.

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

472

The point of using TableGen is to make it as generic as possible so that all backends have a ready-made call that will answer the question for them without having to resort to custom code. If one backend (in this case SystemZ) has a simpler way to do this, then we should use that instead. I'll change the code for SystemZ.

[uweigand]

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

480

Thanks for reworking this, this looks much simpler. However, this version now solely returns general purpose registers used for argument passing. The SystemZ calling convention may in addition also use floating-point registers (and, for XPLINK64, vector registers) to pass arguments of certain types; these are ignored by this implementation.

Is the semantics of isCCArgRegister such that only GPRs *should* be returned? In that case, I think this should be clearly documented (and also, some of the other implementations may have to be adapted?). However, if all registers need to be returned here, then you'll also have to check those other lists mentioned above.

[void]

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

480

I ARE DUMM! I didn't look at your comment above well-enough. Instead, I looked at some of the other code in the SystemZ directory. My mistake. I'll fix this.

[void]

Include the FP registers for SystemZ.

[uweigand]

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

480

SystemZ changes LGTM now, thanks!

[kparzysz]

The Hexagon part looks ok.

[kaz7]

VE part looks OK too.

[nigelp-xmos]

XCore OK.

llvm/include/llvm/CodeGen/CallingConvLower.h

void addLoc(const CCValAssign &V) {
     Locs.push_back(V);
   }
 
   LLVMContext &getContext() const { return Context; }
   MachineFunction &getMachineFunction() const { return MF; }
   CallingConv::ID getCallingConv() const { return CallingConv; }
   bool isVarArg() const { return IsVarArg; }
 
+  /// getTargetRegisterInfo - Useful when checking if a register is part of a
+  /// calling convention.
+  const TargetRegisterInfo &getTargetRegisterInfo() const { return TRI; }
+
   /// getNextStackOffset - Return the next stack offset such that all stack
   /// slots satisfy their alignment requirements.
   unsigned getNextStackOffset() const {
     return StackOffset;
   }
 
   /// getAlignedCallFrameSize - Return the size of the call frame needed to
   /// be able to store all arguments and such that the alignment requirement

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

public:
 
   //===--------------------------------------------------------------------===//
   // Register Info
   //===--------------------------------------------------------------------===//
 
   /// Returns true if the updated CSR list was initialized and false otherwise.
   bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
 
-  /// Returns true if a register can be used as an argument to a function.
-  bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const;
+  /// Returns true if Reg is part of the calling convention.
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const;
 
   /// Returns true if a register is a fixed register.
   bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const;
 
   /// Returns true if a register is a general purpose register.
   bool isGeneralPurposeRegister(const MachineFunction &MF,
                                 MCRegister Reg) const;
 

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
     return false;
   }
 
   /// This is a wrapper around getCallPreservedMask().
   /// Return true if the register is preserved after the call.
   virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
                                     const MachineFunction &MF) const;
 
-  /// Returns true if PhysReg can be used as an argument to a function.
-  virtual bool isArgumentRegister(const MachineFunction &MF,
-                                  MCRegister PhysReg) const {
-    return false;
-  }
+  /// Returns true if Reg is part of the calling convention.
+  virtual bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const = 0;
 
   /// Returns true if PhysReg is a fixed register.
   virtual bool isFixedRegister(const MachineFunction &MF,
                                MCRegister PhysReg) const {
     return false;
   }
 
   /// Returns true if PhysReg is a general purpose register.

llvm/lib/CodeGen/MachineRegisterInfo.cpp

for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
       }
     }
     if (IsRootReserved)
       return true;
   }
   return false;
 }
 
-bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF,
-                                             MCRegister Reg) const {
-  return getTargetRegisterInfo()->isArgumentRegister(MF, Reg);
+bool MachineRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+  return getTargetRegisterInfo()->isCCArgumentReg(MF, Reg);
 }
 
 bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF,
                                           MCRegister Reg) const {
   return getTargetRegisterInfo()->isFixedRegister(MF, Reg);
 }
 
 bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF,
                                                    MCRegister Reg) const {
   return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg);
 }

llvm/lib/CodeGen/PrologEpilogInserter.cpp

for (MCRegister Reg : AllocatableSet.set_bits()) {
     if (OnlyGPR && !TRI.isGeneralPurposeRegister(MF, Reg))
       continue;
 
     // Want only used registers.
     if (OnlyUsed && !UsedRegs[Reg])
       continue;
 
     // Want only registers used for arguments.
-    if (OnlyArg && !TRI.isArgumentRegister(MF, Reg))
+    if (OnlyArg && !TRI.isCCArgumentReg(MF, Reg))
       continue;
 
     RegsToZero.set(Reg);
   }
 
   // Remove registers that are live when leaving the function.
   for (const MachineBasicBlock &MBB : MF)
     for (const MachineInstr &MI : MBB.terminators()) {

llvm/lib/Target/AArch64/AArch64CallingConvention.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
 #define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
 
 #include "llvm/CodeGen/CallingConvLower.h"
 
 namespace llvm {
+
 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
                       CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                       CCState &State);
 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
                                  CCValAssign::LocInfo LocInfo,
                                  ISD::ArgFlagsTy ArgFlags, CCState &State);
 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
                           CCValAssign::LocInfo LocInfo,
bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                     CCState &State);
 bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                          CCState &State);
 bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
                              CCValAssign::LocInfo LocInfo,
                              ISD::ArgFlagsTy ArgFlags, CCState &State);
+
+// Methods to determine if a register belongs to the calling convention.
+bool CC_AArch64_AAPCS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                              MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                              CCState &State);
+bool CC_AArch64_DarwinPCS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                  MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                  CCState &State);
+bool CC_AArch64_DarwinPCS_ILP32_VarArg_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                               MVT ValVT, MVT LocVT,
+                                               ISD::ArgFlagsTy ArgFlags,
+                                               CCState &State);
+bool CC_AArch64_DarwinPCS_VarArg_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                         MVT ValVT, MVT LocVT,
+                                         ISD::ArgFlagsTy ArgFlags,
+                                         CCState &State);
+bool CC_AArch64_GHC_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                            MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                            CCState &State);
+bool CC_AArch64_WebKit_JS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                  MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                  CCState &State);
+bool CC_AArch64_Win64_CFGuard_Check_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                            MVT ValVT, MVT LocVT,
+                                            ISD::ArgFlagsTy ArgFlags,
+                                            CCState &State);
+bool CC_AArch64_Win64_VarArg_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                     MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                     CCState &State);
+
 } // namespace llvm
 
 #endif

llvm/lib/Target/AArch64/AArch64CallingConvention.cpp

static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
   const Align MemAlign = ArgFlags.getNonZeroMemAlign();
   Align SlotAlign = std::min(MemAlign, StackAlign);
   if (!Subtarget.isTargetDarwin())
     SlotAlign = std::max(SlotAlign, Align(8));
 
   return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
 }
 
+static bool CC_AArch64_Custom_Stack_Block_IsCCReg(MCPhysReg &, unsigned &,
+                                                  MVT &, MVT &,
+                                                  ISD::ArgFlagsTy &,
+                                                  CCState &) {
+  return false;
+}
+
+static bool CC_AArch64_Custom_Block_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                            MVT &ValVT, MVT &LocVT,
+                                            ISD::ArgFlagsTy &ArgFlags,
+                                            CCState &State) {
+  const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
+      State.getMachineFunction().getSubtarget());
+  bool IsDarwinILP32 = Subtarget.isTargetILP32() && Subtarget.isTargetMachO();
+
+  ArrayRef<MCPhysReg> RegList;
+  if (LocVT.SimpleTy == MVT::i64 ||
+      (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32))
+    RegList = XRegList;
+  else if (LocVT.SimpleTy == MVT::f16)
+    RegList = HRegList;
+  else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
+    RegList = SRegList;
+  else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
+    RegList = DRegList;
+  else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
+    RegList = QRegList;
+  else if (LocVT.isScalableVector())
+    RegList = ZRegList;
+
+  for (MCPhysReg RegB : RegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
 // TableGen provides definitions of the calling convention analysis entry
 // points.
 #include "AArch64GenCallingConv.inc"

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
   bool cannotEliminateFrame(const MachineFunction &MF) const;
 
   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
   bool hasBasePointer(const MachineFunction &MF) const;
   unsigned getBaseRegister() const;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister PhysReg) const override;
+
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                MachineFunction &MF) const override;
 
   unsigned getLocalAddressRegister(const MachineFunction &MF) const;
   bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the AArch64 implementation of the TargetRegisterInfo
 // class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64RegisterInfo.h"
+#include "AArch64CallingConvention.h"
 #include "AArch64FrameLowering.h"
 #include "AArch64InstrInfo.h"
 #include "AArch64MachineFunctionInfo.h"
 #include "AArch64Subtarget.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/BinaryFormat/Dwarf.h"
bool AArch64RegisterInfo::requiresRegisterScavenging(
   return true;
 }
 
 bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
     const MachineFunction &MF) const {
   return true;
 }
 
+bool AArch64RegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                          MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+  const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
+
+  bool IsVarArg = F.isVarArg();
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), IsVarArg, MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  switch (F.getCallingConv()) {
+  default:
+    report_fatal_error("Unsupported calling convention.");
+  case CallingConv::WebKit_JS:
+    return CC_AArch64_WebKit_JS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::GHC:
+    return CC_AArch64_GHC_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::C:
+  case CallingConv::Fast:
+  case CallingConv::PreserveMost:
+  case CallingConv::CXX_FAST_TLS:
+  case CallingConv::Swift:
+  case CallingConv::SwiftTail:
+  case CallingConv::Tail:
+    if (STI.isTargetWindows() && IsVarArg)
+      return CC_AArch64_Win64_VarArg_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+    if (!STI.isTargetDarwin())
+      return CC_AArch64_AAPCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+    if (!IsVarArg)
+      return CC_AArch64_DarwinPCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+    if (STI.isTargetILP32())
+      return CC_AArch64_DarwinPCS_ILP32_VarArg_IsCCReg(Reg, 0, VT, VT, ArgFlags,
+                                                       CCInfo);
+    return CC_AArch64_DarwinPCS_VarArg_IsCCReg(Reg, 0, VT, VT, ArgFlags,
+                                               CCInfo);
+  case CallingConv::Win64:
+    if (IsVarArg)
+      return CC_AArch64_Win64_VarArg_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+    return CC_AArch64_AAPCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::CFGuard_Check:
+    return CC_AArch64_Win64_CFGuard_Check_IsCCReg(Reg, 0, VT, VT, ArgFlags,
+                                                  CCInfo);
+  case CallingConv::AArch64_VectorCall:
+  case CallingConv::AArch64_SVE_VectorCall:
+    return CC_AArch64_AAPCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  }
+  return false;
+}
+
 bool
 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
   // This function indicates whether the emergency spillslot should be placed
   // close to the beginning of the stackframe (closer to FP) or the end
   // (closer to SP).
   //
   // The beginning works most reliably if we have a frame pointer.
   // In the presence of any non-constant space between FP and locals,

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/KnownBits.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 
+#define CC_ASSIGN_REGS_ONLY
 #include "AMDGPUGenCallingConv.inc"
 
 static cl::opt<bool> AMDGPUBypassSlowDiv(
   "amdgpu-bypass-slow-div",
   cl::desc("Skip 64-bit divide for dynamic 32-bit values"),
   cl::init(true));
 
 // Find a larger type to do a load / store of a vector with.

llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

 #include "R600MachineFunctionInfo.h"
 #include "R600Subtarget.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsR600.h"
 
 using namespace llvm;
 
+#define CC_ASSIGN_REGS_ONLY
 #include "R600GenCallingConv.inc"
 
 R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
                                        const R600Subtarget &STI)
     : AMDGPUTargetLowering(TM, STI), Subtarget(&STI), Gen(STI.getGeneration()) {
   addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass);
   addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
   addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass);

llvm/lib/Target/AMDGPU/R600RegisterInfo.h

struct R600RegisterInfo final : public R600GenRegisterInfo {
   // another.
   bool isPhysRegLiveAcrossClauses(Register Reg) const;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
+
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 
 } // End namespace llvm
 
 #endif

llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp

 }
 
 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
   MCRegAliasIterator R(Reg, this, true);
 
   for (; R.isValid(); ++R)
     Reserved.set(*R);
 }
+
+bool R600RegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                       MCRegister Reg) const {
+  llvm_unreachable("Not supported yet");
+  return false;
+}

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

public:
   }
 
   bool isConstantPhysReg(MCRegister PhysReg) const override;
 
   bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
     return !isSGPRClass(RC);
   }
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
+
   ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
                                      unsigned EltSize) const;
 
   bool shouldCoalesce(MachineInstr *MI,
                       const TargetRegisterClass *SrcRC,
                       unsigned SubReg,
                       const TargetRegisterClass *DstRC,
                       unsigned DstSubReg,

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

 #include "AMDGPURegisterBankInfo.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUInstPrinter.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIMachineFunctionInfo.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_TARGET_DESC
 #include "AMDGPUGenRegisterInfo.inc"
 
 static cl::opt<bool> EnableSpillSGPRToVGPR(
   "amdgpu-spill-sgpr-to-vgpr",
SIRegisterInfo::getAllSGPR64(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(),
                       ST.getMaxNumSGPRs(MF) / 2);
 }
 
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR32(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
 }
+
+#define CC_CHECK_REGS_ONLY
+#include "AMDGPUGenCallingConv.inc"
+
+bool SIRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                     MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  switch (F.getCallingConv()) {
+  case CallingConv::AMDGPU_VS:
+  case CallingConv::AMDGPU_GS:
+  case CallingConv::AMDGPU_PS:
+  case CallingConv::AMDGPU_CS:
+  case CallingConv::AMDGPU_HS:
+  case CallingConv::AMDGPU_ES:
+  case CallingConv::AMDGPU_LS:
+    return CC_AMDGPU_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::C:
+  case CallingConv::Fast:
+  case CallingConv::Cold:
+    return CC_AMDGPU_Func_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::AMDGPU_Gfx:
+    return CC_SI_Gfx_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::AMDGPU_KERNEL:
+  case CallingConv::SPIR_KERNEL:
+  default:
+    report_fatal_error("Unsupported calling convention for call");
+  }
+
+  return false;
+}

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
                                         int64_t Offset) const override;
   void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
                          int64_t Offset) const override;
   bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
                           int64_t Offset) const override;
 
   bool cannotEliminateFrame(const MachineFunction &MF) const;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
+
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
   Register getBaseRegister() const { return BasePtr; }
 
   /// emitLoadConstPool - Emits a load from constpool to materialize the
   /// specified immediate.
   virtual void
   emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the base ARM implementation of TargetRegisterInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMBaseRegisterInfo.h"
 #include "ARM.h"
 #include "ARMBaseInstrInfo.h"
+#include "ARMCallingConv.h"
 #include "ARMFrameLowering.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMSubtarget.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "MCTargetDesc/ARMBaseInfo.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"

 cannotEliminateFrame(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
     return true;
   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
          hasStackRealignment(MF);
 }
 
+bool ARMBaseRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                          MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  switch (F.getCallingConv()) {
+  default:
+    report_fatal_error("Unsupported calling convention");
+  case CallingConv::ARM_APCS:
+    return CC_ARM_APCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::ARM_AAPCS:
+    return CC_ARM_AAPCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::ARM_AAPCS_VFP:
+    return CC_ARM_AAPCS_VFP_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::Fast:
+    return FastCC_ARM_APCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::GHC:
+    return CC_ARM_APCS_GHC_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::PreserveMost:
+    return CC_ARM_AAPCS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  case CallingConv::CFGuard_Check:
+    return CC_ARM_Win32_CFGuard_Check_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  }
+
+  return false;
+}
+
 Register
 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
   const ARMFrameLowering *TFI = getFrameLowering(MF);
 
   if (TFI->hasFP(MF))
     return STI.getFramePointerReg();
   return ARM::SP;

llvm/lib/Target/ARM/ARMCallingConv.h

bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCState &State);
 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
                     CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                     CCState &State);
 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
                         CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                         CCState &State);
 
+// Methods to determine if a register belongs to the calling convention.
+bool CC_ARM_AAPCS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT, MVT LocVT,
+                          ISD::ArgFlagsTy ArgFlags, CCState &State);
+bool CC_ARM_AAPCS_VFP_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                              MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                              CCState &State);
+bool CC_ARM_APCS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT, MVT LocVT,
+                         ISD::ArgFlagsTy ArgFlags, CCState &State);
+bool CC_ARM_APCS_GHC_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                             MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                             CCState &State);
+bool FastCC_ARM_APCS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                             MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                             CCState &State);
+bool CC_ARM_Win32_CFGuard_Check_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                        MVT ValVT, MVT LocVT,
+                                        ISD::ArgFlagsTy ArgFlags,
+                                        CCState &State);
+
 } // namespace llvm
 
 #endif

llvm/lib/Target/ARM/ARMCallingConv.cpp

static bool CC_ARM_AAPCS_VFP_Custom_f16(unsigned ValNo, MVT ValVT, MVT LocVT,
                                         CCValAssign::LocInfo LocInfo,
                                         ISD::ArgFlagsTy ArgFlags,
                                         CCState &State) {
   // f16 arguments are extended to f32 and assigned to a register in [s0, s15]
   return CustomAssignInRegList(ValNo, ValVT, MVT::f32, LocInfo, State,
                                SRegList);
 }
 
+static bool CC_ARM_AAPCS_Custom_f64_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                            MVT ValVT, MVT LocVT,
+                                            ISD::ArgFlagsTy ArgFlags,
+                                            CCState &State) {
+  for (MCPhysReg RegB : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+static bool CC_ARM_AAPCS_Custom_f16_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                            MVT ValVT, MVT LocVT,
+                                            ISD::ArgFlagsTy ArgFlags,
+                                            CCState &State) {
+  for (MCPhysReg RegB : RRegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+static bool CC_ARM_AAPCS_VFP_Custom_f16_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                                MVT ValVT, MVT LocVT,
+                                                ISD::ArgFlagsTy ArgFlags,
+                                                CCState &State) {
+  for (MCPhysReg RegB : SRegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+static bool CC_ARM_AAPCS_Custom_Aggregate_IsCCReg(MCPhysReg RegA,
+                                                  unsigned ValNo, MVT ValVT,
+                                                  MVT LocVT,
+                                                  ISD::ArgFlagsTy ArgFlags,
+                                                  CCState &State) {
+  ArrayRef<MCPhysReg> RegList;
+  switch (LocVT.SimpleTy) {
+  case MVT::i32:
+    RegList = RRegList;
+    break;
+  case MVT::f16:
+  case MVT::bf16:
+  case MVT::f32:
+    RegList = SRegList;
+    break;
+  case MVT::v4f16:
+  case MVT::v4bf16:
+  case MVT::f64:
+    RegList = DRegList;
+    break;
+  case MVT::v8f16:
+  case MVT::v8bf16:
+  case MVT::v2f64:
+    RegList = QRegList;
+    break;
+  default:
+    llvm_unreachable("Unexpected member type for block aggregate");
+    break;
+  }
+
+  for (MCPhysReg RegB : RegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_ARM_APCS_Custom_f64_IsCCReg(MCPhysReg RegA, unsigned ValNo,
+                                           MVT ValVT, MVT LocVT,
+                                           ISD::ArgFlagsTy ArgFlags,
+                                           CCState &State) {
+  for (MCPhysReg RegB : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return true;
+}
+
 // Include the table generated calling convention implementations.
 #include "ARMGenCallingConv.inc"

llvm/lib/Target/AVR/AVRCallingConv.h

+//===-- AVRCallingConv.h - AVR Calling Convention Info ----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains information about the AVR calling conventions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_AVR_CALLING_CONV_H
+#define LLVM_AVR_CALLING_CONV_H
+
+namespace llvm {
+namespace avr {
+
+/// Registers for calling conventions, ordered in reverse as required by ABI.
+/// Both arrays must be of the same length.
+extern const MCPhysReg RegList8[];
+extern const MCPhysReg RegList16[];
+extern const unsigned RegListSize;
+
+} // end namespace avr
+} // end namespace llvm
+
+#endif // LLVM_AVR_REGISTER_INFO_H

llvm/lib/Target/AVR/AVRISelLowering.cpp

 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/IR/Function.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #include "AVR.h"
+#include "AVRCallingConv.h"
 #include "AVRMachineFunctionInfo.h"
 #include "AVRSubtarget.h"
 #include "AVRTargetMachine.h"
 #include "MCTargetDesc/AVRMCTargetDesc.h"
 
 namespace llvm {
 
 AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
bool AVRTargetLowering::isOffsetFoldingLegal(
     const GlobalAddressSDNode *GA) const {
   return true;
 }
 
 //===----------------------------------------------------------------------===//
 //             Formal Arguments Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+#define CC_ASSIGN_REGS_ONLY
 #include "AVRGenCallingConv.inc"
 
+namespace avr {
 /// Registers for calling conventions, ordered in reverse as required by ABI.
 /// Both arrays must be of the same length.
-static const MCPhysReg RegList8[] = {
-    AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
-    AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
-    AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9,  AVR::R8};
-static const MCPhysReg RegList16[] = {
+const MCPhysReg RegList8[] = {AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21,
+                              AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16,
+                              AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11,
+                              AVR::R10, AVR::R9,  AVR::R8};
+
+const MCPhysReg RegList16[] = {
     AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
     AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
     AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
     AVR::R11R10, AVR::R10R9,  AVR::R9R8};
 
+const unsigned RegListSize = array_lengthof(RegList8);
+
 static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
               "8-bit and 16-bit register arrays must be of equal length");
+} // namespace avr
 
 /// Analyze incoming and outgoing function arguments. We need custom C++ code
 /// to handle special constraints in the ABI.
 /// In addition, all pieces of a certain argument have to be passed either
 /// using registers or the stack but never mixing both.
 template <typename ArgT>
 static void
 analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
for (unsigned i = 0; i != NumArgs;) {
     TotalBytes = alignTo(TotalBytes, 2);
     // Skip zero sized arguments
     if (TotalBytes == 0)
       continue;
     // The index of the first register to be used
     unsigned RegIdx = RegLastIdx + TotalBytes;
     RegLastIdx = RegIdx;
     // If there are not enough registers, use the stack
-    if (RegIdx >= array_lengthof(RegList8)) {
+    if (RegIdx >= array_lengthof(avr::RegList8)) {
       UseStack = true;
     }
     for (; i != j; ++i) {
       MVT VT = Args[i].VT;
 
       if (UseStack) {
         auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
         unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
                                                TD->getABITypeAlign(evt));
         CCInfo.addLoc(
             CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
       } else {
         unsigned Reg;
         if (VT == MVT::i8) {
-          Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
+          Reg = CCInfo.AllocateReg(avr::RegList8[RegIdx]);
         } else if (VT == MVT::i16) {
-          Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
+          Reg = CCInfo.AllocateReg(avr::RegList16[RegIdx]);
         } else {
           llvm_unreachable(
               "calling convention can only manage i8 and i16 types");
         }
         assert(Reg && "register not available in calling convention");
         CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
         // Registers inside a particular argument are sorted in increasing order
         // (remember the array is reversed).
static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
   }
 
   // The index of the first register to use.
   int RegIdx = TotalBytes - 1;
   for (unsigned i = 0; i != NumArgs; ++i) {
     MVT VT = Args[i].VT;
     unsigned Reg;
     if (VT == MVT::i8) {
-      Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
+      Reg = CCInfo.AllocateReg(avr::RegList8[RegIdx]);
     } else if (VT == MVT::i16) {
-      Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
+      Reg = CCInfo.AllocateReg(avr::RegList16[RegIdx]);
     } else {
       llvm_unreachable("calling convention can only manage i8 and i16 types");
     }
     assert(Reg && "register not available in calling convention");
     CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
     // Registers sort in increasing order
     RegIdx -= VT.getStoreSize();
   }

llvm/lib/Target/AVR/AVRRegisterInfo.h

public:
   /// Splits a 16-bit `DREGS` register into the lo/hi register pair.
   /// \param Reg A 16-bit register to split.
   void splitReg(Register Reg, Register &LoReg, Register &HiReg) const;
 
   bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
                       unsigned SubReg, const TargetRegisterClass *DstRC,
                       unsigned DstSubReg, const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
+
+  /// Returns true if PhysReg is part of the calling convention.
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_REGISTER_INFO_H

llvm/lib/Target/AVR/AVRRegisterInfo.cpp

 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/IR/Function.h"
 
 #include "AVR.h"
+#include "AVRCallingConv.h"
 #include "AVRInstrInfo.h"
 #include "AVRMachineFunctionInfo.h"
 #include "AVRTargetMachine.h"
 #include "MCTargetDesc/AVRMCTargetDesc.h"
 
 #define GET_REGINFO_TARGET_DESC
 #include "AVRGenRegisterInfo.inc"
 
bool AVRRegisterInfo::shouldCoalesce(
   if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
     return false;
   }
 
   return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
                                             NewRC, LIS);
 }
 
+#define CC_CHECK_REGS_ONLY
+#include "AVRGenCallingConv.inc"
+
+bool AVRRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                      MCRegister RegA) const {
+  const Function &F = MF.getFunction();
+  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
+  const AVRRegisterInfo *TRI = STI.getRegisterInfo();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(RegA);
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+
+  if (F.isVarArg()) {
+    SmallVector<CCValAssign, 16> RVLocs;
+    CCState CCInfo(F.getCallingConv(), true, MF, RVLocs, F.getContext());
+    ISD::ArgFlagsTy ArgFlags;
+    ArgFlags.setInReg();
+
+    return ArgCC_AVR_Vararg_IsCCReg(RegA, 0, VT, VT, ArgFlags, CCInfo);
+  }
+
+  const MCPhysReg *RegList;
+  if (VT == MVT::i8)
+    RegList = avr::RegList8;
+  else if (VT == MVT::i16)
+    RegList = avr::RegList16;
+
+  for (unsigned I = 0, E = avr::RegListSize; I != E; ++I)
+    if (TRI->isSuperOrSubRegisterEq(RegA, RegList[I]))
+      return true;
+
+  return false;
+}
+
 } // end of namespace llvm

llvm/lib/Target/BPF/BPFISelLowering.cpp

SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::DYNAMIC_STACKALLOC:
     report_fatal_error("Unsupported dynamic stack allocation");
   default:
     llvm_unreachable("unimplemented operand");
   }
 }
 
 // Calling Convention Implementation
+#define CC_ASSIGN_REGS_ONLY
 #include "BPFGenCallingConv.inc"
 
 SDValue BPFTargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
   switch (CallConv) {
   default:

llvm/lib/Target/BPF/BPFRegisterInfo.h

 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "BPFGenRegisterInfo.inc"
 
 namespace llvm {
 
-struct BPFRegisterInfo : public BPFGenRegisterInfo {
+struct BPFRegisterInfo final : public BPFGenRegisterInfo {
 
   BPFRegisterInfo();
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
+
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 }
 
 #endif

llvm/lib/Target/BPF/BPFRegisterInfo.cpp

 //===-- BPFRegisterInfo.cpp - BPF Register Information ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the BPF implementation of the TargetRegisterInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "BPFRegisterInfo.h"
 #include "BPF.h"
 #include "BPFSubtarget.h"
+#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/Support/ErrorHandling.h"
if (MI.getOpcode() == BPF::FI_ri) {
     MI.getOperand(i).ChangeToRegister(FrameReg, false);
     MI.getOperand(i + 1).ChangeToImmediate(Offset);
   }
 }
 
 Register BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   return BPF::R10;
 }
+
+#define CC_CHECK_REGS_ONLY
+#include "BPFGenCallingConv.inc"
+
+bool BPFRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                      MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (MF.getSubtarget<BPFSubtarget>().getHasAlu32())
+    return CC_BPF32_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return CC_BPF64_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+}

llvm/lib/Target/Hexagon/HexagonCallingConv.h

+//==- HexagonCallingConv.h - Hexagon Calling Conventions ---------*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains information for the Hexagon's calling conventions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONCALLINGCONV_H
+#define LLVM_LIB_TARGET_HEXAGON_HEXAGONCALLINGCONV_H
+
+#include "llvm/CodeGen/CallingConvLower.h"
+
+namespace llvm {
+
+class HexagonCCState final : public CCState {
+  unsigned NumNamedVarArgParams = 0;
+
+public:
+  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
+                 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
+                 unsigned NumNamedArgs)
+      : CCState(CC, IsVarArg, MF, locs, C), NumNamedVarArgParams(NumNamedArgs) {
+  }
+  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
+};
+
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONCALLINGCONV_H

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the interfaces that Hexagon uses to lower LLVM code
 // into a selection DAG.
 //
 //===----------------------------------------------------------------------===//
 
 #include "HexagonISelLowering.h"
 #include "Hexagon.h"
+#include "HexagonCallingConv.h"
 #include "HexagonMachineFunctionInfo.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "HexagonTargetMachine.h"
 #include "HexagonTargetObjectFile.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"

 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/IntrinsicsHexagon.h"
-#include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/Value.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
static cl::opt<bool> AlignLoads("hexagon-align-loads",
   cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
 
 static cl::opt<bool>
     DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden,
                             cl::init(false),
                             cl::desc("Disable minimum alignment of 1 for "
                                      "arguments passed by value on stack"));
 
-namespace {
-
-  class HexagonCCState : public CCState {
-    unsigned NumNamedVarArgParams = 0;
-
-  public:
-    HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
-                   SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
-                   unsigned NumNamedArgs)
-        : CCState(CC, IsVarArg, MF, locs, C),
-          NumNamedVarArgParams(NumNamedArgs) {}
-    unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
-  };
-
-} // end anonymous namespace
-
-
 // Implement calling convention for Hexagon.
 
 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                        CCValAssign::LocInfo &LocInfo,
                        ISD::ArgFlagsTy &ArgFlags, CCState &State) {
   static const MCPhysReg ArgRegs[] = {
     Hexagon::R0, Hexagon::R1, Hexagon::R2,
     Hexagon::R3, Hexagon::R4, Hexagon::R5
   };
   const unsigned NumArgRegs = array_lengthof(ArgRegs);
   unsigned RegNum = State.getFirstUnallocated(ArgRegs);
 
   // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
   if (RegNum != NumArgRegs && RegNum % 2 == 1)
     State.AllocateReg(ArgRegs[RegNum]);
 
   // Always return false here, as this function only makes sure that the first
   // unallocated register has an even register number and does not actually
   // allocate a register for the current argument.
   return false;
 }
 
+#define CC_ASSIGN_REGS_ONLY
 #include "HexagonGenCallingConv.inc"
 
-
 SDValue
 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
       const {
   return SDValue();
 }
 
 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
 /// by "Src" to address "Dst" of size "Size".  Alignment information is

llvm/lib/Target/Hexagon/HexagonRegisterInfo.h

 
 namespace llvm {
 
 namespace Hexagon {
   // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
   enum { ps_sub_lo = 0, ps_sub_hi = 1 };
 }
 
-class HexagonRegisterInfo : public HexagonGenRegisterInfo {
+class HexagonRegisterInfo final : public HexagonGenRegisterInfo {
 public:
   HexagonRegisterInfo(unsigned HwMode);
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
         const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
         CallingConv::ID) const override;
public:
 
   unsigned getFirstCallerSavedNonParamReg() const;
 
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
 
   bool isEHReturnCalleeSaveReg(unsigned Reg) const;
+
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp

 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the Hexagon implementation of the TargetRegisterInfo
 // class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "HexagonRegisterInfo.h"
 #include "Hexagon.h"
+#include "HexagonCallingConv.h"
 #include "HexagonMachineFunctionInfo.h"
 #include "HexagonSubtarget.h"
 #include "HexagonTargetMachine.h"
 #include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/LiveRegUnits.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
HexagonRegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                         unsigned Kind) const {
   return &Hexagon::IntRegsRegClass;
 }
 
 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
   return Hexagon::R6;
 }
 
+static bool CC_SkipOdd_IsCCReg(MCPhysReg RegA, unsigned ValNO, MVT &ValVT,
+                               MVT &LocVT, ISD::ArgFlagsTy &ArgFlags,
+                               CCState &State) {
+  static const MCPhysReg ArgRegs[] = {Hexagon::R0, Hexagon::R1, Hexagon::R2,
+                                      Hexagon::R3, Hexagon::R4, Hexagon::R5};
+
+  for (MCPhysReg RegB : ArgRegs)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+#define CC_CHECK_REGS_ONLY
+#include "HexagonGenCallingConv.inc"
+
+bool HexagonRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                          MCRegister Reg) const {
+  (void)CC_Hexagon_Legacy_IsCCReg; // Silence unused function warning.
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  unsigned NumParams = F.getFunctionType()->getNumParams();
+  SmallVector<CCValAssign, 16> RVLocs;
+  HexagonCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs,
+                        F.getContext(), NumParams);
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (MF.getSubtarget<HexagonSubtarget>().useHVXOps())
+    return CC_Hexagon_HVX_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  else
+    return CC_Hexagon_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return false;
+}

llvm/lib/Target/Lanai/LanaiISelLowering.cpp

void LanaiTargetLowering::LowerAsmOperandForConstraint(
 
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+#define CC_ASSIGN_REGS_ONLY
 #include "LanaiGenCallingConv.inc"
 
 static unsigned NumFixedArgs;
 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
                               CCValAssign::LocInfo LocInfo,
                               ISD::ArgFlagsTy ArgFlags, CCState &State) {
   // Handle fixed arguments with default CC.
   // Note: Both the default and fast CC handle VarArg the same and hence the

llvm/lib/Target/Lanai/LanaiRegisterInfo.h

 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "LanaiGenRegisterInfo.inc"
 
 namespace llvm {
 
-struct LanaiRegisterInfo : public LanaiGenRegisterInfo {
+struct LanaiRegisterInfo final : public LanaiGenRegisterInfo {
   LanaiRegisterInfo();
 
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
 
   // Code Generation virtual methods.
   const uint16_t *
   getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
+
   // Debug information queries.
   unsigned getRARegister() const;
   Register getFrameRegister(const MachineFunction &MF) const override;
   Register getBaseRegister() const;
   bool hasBasePointer(const MachineFunction &MF) const;
 
   int getDwarfRegNum(unsigned RegNum, bool IsEH) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H

llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp

 
 #include "LanaiRegisterInfo.h"
 #include "LanaiAluCode.h"
 #include "LanaiCondCode.h"
 #include "LanaiFrameLowering.h"
 #include "LanaiInstrInfo.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define GET_REGINFO_TARGET_DESC
 #include "LanaiGenRegisterInfo.inc"
bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   // When we need stack realignment and there are dynamic allocas, we can't
   // reference off of the stack pointer, so we reserve a base pointer.
   if (hasStackRealignment(MF) && MFI.hasVarSizedObjects())
     return true;
 
   return false;
 }
 
+#define CC_CHECK_REGS_ONLY
+#include "LanaiGenCallingConv.inc"
+
+bool LanaiRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                        MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (F.getCallingConv() == CallingConv::Fast)
+    return CC_Lanai32_Fast_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+  else
+    return CC_Lanai32_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return false;
+}
+
 unsigned LanaiRegisterInfo::getRARegister() const { return Lanai::RCA; }
 
 Register
 LanaiRegisterInfo::getFrameRegister(const MachineFunction & /*MF*/) const {
   return Lanai::FP;
 }
 
 Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; }
 
 const uint32_t *
 LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
                                         CallingConv::ID /*CC*/) const {
   return CSR_RegMask;
 }

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

MSP430TargetLowering::getRegForInlineAsmConstraint(
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+#define CC_ASSIGN_REGS_ONLY
 #include "MSP430GenCallingConv.inc"
 
 /// For each argument in a function store the number of pieces it is composed
 /// of.
 template<typename ArgT>
 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
                               SmallVectorImpl<unsigned> &Out) {
   unsigned CurrentArgIndex;

llvm/lib/Target/MSP430/MSP430RegisterInfo.h

 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "MSP430GenRegisterInfo.inc"
 
 namespace llvm {
 
-struct MSP430RegisterInfo : public MSP430GenRegisterInfo {
+struct MSP430RegisterInfo final : public MSP430GenRegisterInfo {
 public:
   MSP430RegisterInfo();
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   const TargetRegisterClass*
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override {
+    return false;
+  }
+
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/Mips/MipsFastISel.cpp

 }
 
 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
                             CCValAssign::LocInfo LocInfo,
                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
   llvm_unreachable("should not be called");
 }
 
+#define CC_ASSIGN_REGS_ONLY
 #include "MipsGenCallingConv.inc"
 
 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
   return CC_MipsO32;
 }
 
 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
                                      const Value *LHS, const Value *RHS) {

llvm/lib/Target/Mips/MipsISelLowering.cpp

static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
 
   return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
 }
 
 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                        CCState &State) LLVM_ATTRIBUTE_UNUSED;
 
+#define CC_ASSIGN_REGS_ONLY
 #include "MipsGenCallingConv.inc"
 
  CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
    return CC_Mips_FixedArg;
  }
 
  CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
    return RetCC_Mips;

llvm/lib/Target/Mips/MipsRegisterInfo.h

public:
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
   static const uint32_t *getMips16RetHelperMask();
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
+
   /// Stack Frame Processing Methods
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   // Stack realignment queries.
   bool canRealignStack(const MachineFunction &MF) const override;
 

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the MIPS implementation of the TargetRegisterInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsRegisterInfo.h"
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "Mips.h"
+#include "MipsCCState.h"
 #include "MipsMachineFunction.h"
 #include "MipsSubtarget.h"
 #include "MipsTargetMachine.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   // don't have variable sized objects.
   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
     return true;
 
   // We have to reserve the base pointer register in the presence of variable
   // sized objects.
   return MF.getRegInfo().canReserveReg(BP);
 }
+
+static bool CC_MipsO32_FP32_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                    MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                    CCState &State) {
+  for (MCPhysReg RegB : {Mips::D6, Mips::D7})
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_MipsO32_FP64_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                    MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                    CCState &State) {
+  for (MCPhysReg RegB : {Mips::D12_64, Mips::D14_64})
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_Mips_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                            MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                            CCState &State) LLVM_ATTRIBUTE_UNUSED;
+static bool CC_MipsO32_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                               MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                               CCState &State);
+
+#define CC_CHECK_REGS_ONLY
+#include "MipsGenCallingConv.inc"
+
+bool MipsRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                       MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs,
+                     F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (F.getCallingConv() == CallingConv::Fast)
+    return CC_MipsO32_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return CC_Mips_FixedArg_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+}

llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h

 #include "ManagedStringPool.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include <sstream>
 
 #define GET_REGINFO_HEADER
 #include "NVPTXGenRegisterInfo.inc"
 
 namespace llvm {
-class NVPTXRegisterInfo : public NVPTXGenRegisterInfo {
+
+class NVPTXRegisterInfo final : public NVPTXGenRegisterInfo {
 private:
   // Hold Strings that can be free'd all together with NVPTXRegisterInfo
   ManagedStringPool ManagedStrPool;
 
 public:
   NVPTXRegisterInfo();
 
   //------------------------------------------------------
   // Pure virtual functions from TargetRegisterInfo
   //------------------------------------------------------
 
   // NVPTX callee saved registers
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
+  // No calling convention is specified.
+  bool isCCArgumentReg(MachineFunction &, MCRegister) const override {
+    return false;
+  }
+
   Register getFrameRegister(const MachineFunction &MF) const override;
   Register getFrameLocalRegister(const MachineFunction &MF) const;
 
   ManagedStringPool *getStrPool() const {
     return const_cast<ManagedStringPool *>(&ManagedStrPool);
   }
 
   const char *getName(unsigned RegNo) const {
     std::stringstream O;
     O << "reg" << RegNo;
     return getStrPool()->getManagedString(O.str().c_str())->c_str();
   }
-
 };
 
 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/PowerPC/PPCCallingConv.h

bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
                       CCState &State);
 bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                          CCState &State);
 bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
                           CCValAssign::LocInfo LocInfo,
                           ISD::ArgFlagsTy ArgFlags, CCState &State);
 
+// Methods to determine if a register belongs to the calling convention.
+bool CC_PPC32_SVR4_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT, MVT LocVT,
+                           ISD::ArgFlagsTy ArgFlags, CCState &State);
+bool CC_PPC64_ELF_FIS_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                              MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                              CCState &State);
+bool CC_PPC32_SVR4_ByVal_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                 MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                 CCState &State);
+bool CC_PPC32_SVR4_VarArg_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT,
+                                  MVT LocVT, ISD::ArgFlagsTy ArgFlags,
+                                  CCState &State);
+
 } // End llvm namespace
 
 #endif
 

llvm/lib/Target/PowerPC/PPCCallingConv.cpp

if (HiRegList[i] == Reg)
       break;
 
   State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
   State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
                                          LocVT, LocInfo));
   return true;
 }
 
+#define CC_ASSIGN_REGS_ONLY
 #include "PPCGenCallingConv.inc"

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

static void emitAccCopyInfo(MachineBasicBlock &MBB, MCRegister DestReg,
                               MCRegister SrcReg);
 
   bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
                             int &FrameIdx) const override;
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
+
   // Support for virtual base registers.
   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
   Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx,
                                         int64_t Offset) const override;
   void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
                          int64_t Offset) const override;
   bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
                           int64_t Offset) const override;

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetRegisterInfo
 // class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "PPCRegisterInfo.h"
+#include "PPCCCState.h"
+#include "PPCCallingConv.h"
 #include "PPCFrameLowering.h"
 #include "PPCInstrBuilder.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
   unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
   Offset += MI->getOperand(OffsetOperandNo).getImm();
 
   return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
          MI->getOpcode() == TargetOpcode::STACKMAP ||
          MI->getOpcode() == TargetOpcode::PATCHPOINT ||
          (isInt<16>(Offset) && (Offset % offsetMinAlign(*MI)) == 0);
 }
+
+static bool CC_PPC32_SVR4_Custom_Dummy_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                               MVT &ValVT, MVT &LocVT,
+                                               ISD::ArgFlagsTy &ArgFlags,
+                                               CCState &State) {
+  return false;
+}
+
+static bool CC_PPC32_SVR4_Custom_AlignArgRegs_IsCCReg(MCPhysReg &RegA,
+                                                      unsigned &ValNo,
+                                                      MVT &ValVT, MVT &LocVT,
+                                                      ISD::ArgFlagsTy &ArgFlags,
+                                                      CCState &State) {
+  static const MCPhysReg ArgRegs[] = {
+      PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+  };
+
+  for (MCPhysReg RegB : ArgRegs)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128_IsCCReg(
+    MCPhysReg &RegA, unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+    ISD::ArgFlagsTy &ArgFlags, CCState &State) {
+  static const MCPhysReg ArgRegs[] = {
+      PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+  };
+
+  for (MCPhysReg RegB : ArgRegs)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs_IsCCReg(
+    MCPhysReg &RegA, unsigned &ValNo, MVT &ValVT, MVT &LocVT,
+    ISD::ArgFlagsTy &ArgFlags, CCState &State) {
+  static const MCPhysReg ArgRegs[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4,
+                                      PPC::F5, PPC::F6, PPC::F7, PPC::F8};
+
+  for (MCPhysReg RegB : ArgRegs)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+static bool CC_PPC32_SPE_CustomSplitFP64_IsCCReg(MCPhysReg &RegA,
+                                                 unsigned &ValNo, MVT &ValVT,
+                                                 MVT &LocVT,
+                                                 ISD::ArgFlagsTy &ArgFlags,
+                                                 CCState &State) {
+  static const MCPhysReg RegList[] = {PPC::R3, PPC::R5, PPC::R7, PPC::R9,
+                                      PPC::R4, PPC::R6, PPC::R8, PPC::R10};
+
+  for (MCPhysReg RegB : RegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+  return false;
+}
+
+inline bool CC_PPC_AnyReg_Error_IsCCReg(MCPhysReg &, unsigned &, MVT &, MVT &,
+                                        ISD::ArgFlagsTy &, CCState &) {
+  llvm_unreachable("The AnyReg calling convention is only supported by the "
+                   "stackmap and patchpoint intrinsics.");
+  // gracefully fallback to PPC C calling convention on Release builds.
+  return false;
+}
+
+#define CC_CHECK_REGS_ONLY
+#include "PPCGenCallingConv.inc"
+
+bool PPCRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                      MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  CallingConv::ID CC = F.getCallingConv();
+  SmallVector<CCValAssign, 16> RVLocs;
+  PPCCCState CCInfo(CC, F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (CC == CallingConv::Fast)
+    return CC_PPC64_ELF_FIS_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return false;
+}

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "RISCVGenRegisterInfo.inc"
 
 namespace llvm {
 
-struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
+struct RISCVRegisterInfo final : public RISCVGenRegisterInfo {
 
   RISCVRegisterInfo(unsigned HwMode);
 
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
struct RISCVRegisterInfo final : public RISCVGenRegisterInfo {
   const TargetRegisterClass *
   getLargestLegalSuperClass(const TargetRegisterClass *RC,
                             const MachineFunction &) const override;
 
   void getOffsetOpcodes(const StackOffset &Offset,
                         SmallVectorImpl<uint64_t> &Ops) const override;
 
   unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
+
+  bool isCCArgumentReg(MachineFunction &, MCRegister) const override {
+    llvm_unreachable("isCCArgumentReg not implemented for RISCV");
+    return false;
+  }
 };
 }
 
 #endif

llvm/lib/Target/Sparc/SparcISelLowering.cpp

if (LocVT == MVT::i32 && Offset < 6*8) {
     else
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
     return true;
   }
 
   State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
   return true;
 }
-
+#define CC_ASSIGN_REGS_ONLY
 #include "SparcGenCallingConv.inc"
 
 // The calling conventions in SparcCallingConv.td are described in terms of the
 // callee's register window. This function translates registers to the
 // corresponding caller window %o register.
 static unsigned toCallerWindow(unsigned Reg) {
   static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
                 "Unexpected enum");

llvm/lib/Target/Sparc/SparcRegisterInfo.h

 #define LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H
 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "SparcGenRegisterInfo.inc"
 
 namespace llvm {
-struct SparcRegisterInfo : public SparcGenRegisterInfo {
+
+struct SparcRegisterInfo final : public SparcGenRegisterInfo {
   SparcRegisterInfo();
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
 
   const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
                                                 unsigned Kind) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   bool canRealignStack(const MachineFunction &MF) const override;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/Sparc/SparcRegisterInfo.cpp

 //===----------------------------------------------------------------------===//
 
 #include "SparcRegisterInfo.h"
 #include "Sparc.h"
 #include "SparcMachineFunctionInfo.h"
 #include "SparcSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 
bool SparcRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   if (getFrameLowering(MF)->hasReservedCallFrame(MF))
     return true;
 
   // Otherwise, we'd need a base pointer, but those aren't implemented
   // for SPARC at the moment.
 
   return false;
 }
+
+static bool CC_Sparc_Assign_Split_64_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                             MVT &ValVT, MVT &LocVT,
+                                             ISD::ArgFlagsTy &ArgFlags,
+                                             CCState &State) {
+  static const MCPhysReg RegList[] = {SP::I0, SP::I1, SP::I2,
+                                      SP::I3, SP::I4, SP::I5};
+
+  for (MCPhysReg RegB : RegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_Sparc64_Full_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                    MVT &ValVT, MVT &LocVT,
+                                    ISD::ArgFlagsTy &ArgFlags, CCState &State) {
+  assert((LocVT == MVT::f32 || LocVT == MVT::f128 ||
+          LocVT.getSizeInBits() == 64) &&
+         "Can't handle non-64 bits locations");
+
+  // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
+  unsigned size = (LocVT == MVT::f128) ? 16 : 8;
+  Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8);
+  unsigned Offset = State.AllocateStack(size, alignment);
+  unsigned Reg = 0;
+
+  if (LocVT == MVT::i64 && Offset < 6 * 8)
+    // Promote integers to %i0-%i5.
+    Reg = SP::I0 + Offset / 8;
+  else if (LocVT == MVT::f64 && Offset < 16 * 8)
+    // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
+    Reg = SP::D0 + Offset / 8;
+  else if (LocVT == MVT::f32 && Offset < 16 * 8)
+    // Promote floats to %f1, %f3, ...
+    Reg = SP::F1 + Offset / 4;
+  else if (LocVT == MVT::f128 && Offset < 16 * 8)
+    // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
+    Reg = SP::Q0 + Offset / 16;
+
+  // Promote to register when possible, otherwise use the stack slot.
+  if (Reg)
+    return State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, Reg);
+
+  // This argument goes on the stack in an 8-byte slot.
+  // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
+  // the right-aligned float. The first 4 bytes of the stack slot are undefined.
+  if (LocVT == MVT::f32)
+    Offset += 4;
+
+  return State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, Offset);
+}
+
+static bool CC_Sparc64_Half_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                    MVT &ValVT, MVT &LocVT,
+                                    ISD::ArgFlagsTy &ArgFlags, CCState &State) {
+  assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
+  unsigned Offset = State.AllocateStack(4, Align(4));
+
+  if (LocVT == MVT::f32 && Offset < 16 * 8)
+    return State.getTargetRegisterInfo().isSuperOrSubRegisterEq(
+        RegA, SP::F0 + Offset / 4);
+
+  if (LocVT == MVT::i32 && Offset < 6 * 8)
+    return State.getTargetRegisterInfo().isSuperOrSubRegisterEq(
+        RegA, SP::I0 + Offset / 8);
+
+  return State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, Offset);
+}
+
+static bool CC_Sparc_Assign_SRet_IsCCReg(MCPhysReg &, unsigned &, MVT &, MVT &,
+                                         ISD::ArgFlagsTy &, CCState &) {
+  return false;
+}
+
+#define CC_CHECK_REGS_ONLY
+#include "SparcGenCallingConv.inc"
+
+bool SparcRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                        MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (MF.getSubtarget<SparcSubtarget>().is64Bit())
+    return CC_Sparc64_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return CC_Sparc32_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+}

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
   }
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
 //===----------------------------------------------------------------------===//
 // Calling conventions
 //===----------------------------------------------------------------------===//
 
+#define CC_ASSIGN_REGS_ONLY
 #include "SystemZGenCallingConv.inc"
 
 const MCPhysReg *SystemZTargetLowering::getScratchRegisters(
   CallingConv::ID) const {
   static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
                                            SystemZ::R14D, 0 };
   return ScratchRegs;
 }

llvm/lib/Target/SystemZ/SystemZRegisterInfo.h

public:
   int getCallFrameSize() override final { return SystemZMC::ELFCallFrameSize; }
 
   int getStackPointerBias() override final { return 0; }
 
   /// Destroys the object. Bogus destructor overriding base class destructor
   ~SystemZELFRegisters() = default;
 };
 
-struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
+struct SystemZRegisterInfo final : public SystemZGenRegisterInfo {
 public:
   SystemZRegisterInfo(unsigned int RA);
 
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is currently only used by LOAD_STACK_GUARD, which requires a non-%r0
   /// register, hence ADDR64.
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
public:
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   void eliminateFrameIndex(MachineBasicBlock::iterator MI,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS) const override;
 
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
+
   /// SrcRC and DstRC will be morphed into NewRC if this returns true.
- bool shouldCoalesce(MachineInstr *MI,
-                      const TargetRegisterClass *SrcRC,
-                      unsigned SubReg,
-                      const TargetRegisterClass *DstRC,
-                      unsigned DstSubReg,
-                      const TargetRegisterClass *NewRC,
+  bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
+                      unsigned SubReg, const TargetRegisterClass *DstRC,
+                      unsigned DstSubReg, const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp

 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZRegisterInfo.h"
+#include "SystemZCallingConv.h"
 #include "SystemZInstrInfo.h"
 #include "SystemZSubtarget.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/VirtRegMap.h"

 
 const TargetRegisterClass *
 SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
   if (RC == &SystemZ::CCRRegClass)
     return &SystemZ::GR32BitRegClass;
   return RC;
 }
 
+bool SystemZRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                          MCRegister RegA) const {
+  const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
+  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
+
+  if (Subtarget.isTargetELF()) {
+    for (const MCPhysReg RegB : llvm::concat<const MCPhysReg>(
+             SystemZ::ELFArgGPRs, SystemZ::ELFArgFPRs))
+      if (TRI->isSuperOrSubRegisterEq(RegA, RegB))
+        return true;
+  } else if (Subtarget.isTargetXPLINK64()) {
+    for (const MCPhysReg RegB : llvm::concat<const MCPhysReg>(
+             SystemZ::XPLINK64ArgGPRs, SystemZ::XPLINK64ArgFPRs,
+             SystemZ::XPLINK64ArgVRs))
+      if (TRI->isSuperOrSubRegisterEq(RegA, RegB))
+        return true;
+  } else {
+    llvm_unreachable("Unknown Calling Convention!");
+  }
+
+  return false;
+}

llvm/lib/Target/VE/VEISelLowering.cpp

 using namespace llvm;
 
 #define DEBUG_TYPE "ve-lower"
 
 //===----------------------------------------------------------------------===//
 // Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+#define CC_ASSIGN_REGS_ONLY
 #include "VEGenCallingConv.inc"
 
 CCAssignFn *getReturnCC(CallingConv::ID CallConv) {
   switch (CallConv) {
   default:
     return RetCC_VE_C;
   case CallingConv::Fast:
     return RetCC_VE_Fast;

llvm/lib/Target/VE/VERegisterInfo.h

 #define LLVM_LIB_TARGET_VE_VEREGISTERINFO_H
 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "VEGenRegisterInfo.inc"
 
 namespace llvm {
-struct VERegisterInfo : public VEGenRegisterInfo {
-public:
+
+struct VERegisterInfo final : public VEGenRegisterInfo {
   VERegisterInfo();
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
   const uint32_t *getNoPreservedMask() const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool isConstantPhysReg(MCRegister PhysReg) const override;
 
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
                                                 unsigned Kind) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
+
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/VERegisterInfo.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "VERegisterInfo.h"
 #include "VE.h"
 #include "VESubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
 }
 
 Register VERegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   return VE::SX9;
 }
+
+#define CC_CHECK_REGS_ONLY
+#include "VEGenCallingConv.inc"
+
+bool VERegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                     MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  CallingConv::ID CC = F.getCallingConv();
+  bool IsVarArg = F.isVarArg();
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CC, IsVarArg, MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  if (IsVarArg)
+    return CC_VE2_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  if (CC == CallingConv::Fast)
+    return CC_VE_Fast_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+
+  return CC_VE_C_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+}

llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h

public:
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
   // This does not apply to wasm.
   const uint32_t *getNoPreservedMask() const override { return nullptr; }
+
+  bool isCCArgumentReg(MachineFunction &, MCRegister) const override {
+    return false;
+  }
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/X86/X86CallingConv.h

 
 bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT,
                CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                CCState &State);
 
 bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
             ISD::ArgFlagsTy ArgFlags, CCState &State);
 
+// Methods to determine if a register belongs to the calling convention.
+bool CC_X86_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT, MVT LocVT,
+                    ISD::ArgFlagsTy ArgFlags, CCState &State);
+
 } // End llvm namespace
 
 #endif
 

llvm/lib/Target/X86/X86CallingConv.cpp

static bool CC_X86_64_Pointer(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                               ISD::ArgFlagsTy &ArgFlags, CCState &State) {
   if (LocVT != MVT::i64) {
     LocVT = MVT::i64;
     LocInfo = CCValAssign::ZExt;
   }
   return false;
 }
 
+static bool CC_X86_64_Pointer_IsCCReg(MCPhysReg &, unsigned &, MVT &, MVT &,
+                                      ISD::ArgFlagsTy &, CCState &) {
+  return false;
+}
+
+static bool CC_X86_Intr_IsCCReg(MCPhysReg &RegA, unsigned &ValNo, MVT &ValVT,
+                                MVT &LocVT, ISD::ArgFlagsTy &ArgFlags,
+                                CCState &State) {
+  return false;
+}
+
+static bool CC_X86_32_MCUInReg_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                       MVT &ValVT, MVT &LocVT,
+                                       ISD::ArgFlagsTy &ArgFlags,
+                                       CCState &State) {
+  for (MCPhysReg RegB : {X86::EAX, X86::EDX, X86::ECX})
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_X86_32_RegCall_Assign2Regs_IsCCReg(MCPhysReg &RegA,
+                                                  unsigned &ValNo, MVT &ValVT,
+                                                  MVT &LocVT,
+                                                  ISD::ArgFlagsTy &ArgFlags,
+                                                  CCState &State) {
+  // List of GPR registers that are available to store values in regcall
+  // calling convention.
+  static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
+                                      X86::ESI};
+  for (MCPhysReg RegB : RegList)
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_X86_AnyReg_Error_IsCCReg(MCPhysReg &, unsigned &, MVT &, MVT &,
+                                        ISD::ArgFlagsTy &, CCState &) {
+  llvm_unreachable("The AnyReg calling convention is only supported by the "
+                   "stackmap and patchpoint intrinsics.");
+  // gracefully fallback to X86 C calling convention on Release builds.
+  return false;
+}
+
+static bool CC_X86_32_VectorCall_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                         MVT &ValVT, MVT &LocVT,
+                                         ISD::ArgFlagsTy &ArgFlags,
+                                         CCState &State) {
+  // On the second pass, go through the HVAs only.
+  if (ArgFlags.isSecArgPass()) {
+    if (ArgFlags.isHva())
+      for (MCPhysReg RegB : CC_X86_VectorCallGetSSEs(ValVT))
+        if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+          return true;
+
+    return false;
+  }
+
+  // Process only vector types as defined by vectorcall spec:
+  // "A vector type is either a floating point type, for example,
+  //  a float or double, or an SIMD vector type, for example, __m128 or __m256".
+  if (!(ValVT.isFloatingPoint() ||
+        (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {
+    return false;
+  }
+
+  if (ArgFlags.isHva())
+    return false; // If this is an HVA - Stop the search.
+
+  // Assign XMM register.
+  for (MCPhysReg RegB : CC_X86_VectorCallGetSSEs(ValVT))
+    if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+      return true;
+
+  return false;
+}
+
+static bool CC_X86_64_VectorCall_IsCCReg(MCPhysReg &RegA, unsigned &ValNo,
+                                         MVT &ValVT, MVT &LocVT,
+                                         ISD::ArgFlagsTy &ArgFlags,
+                                         CCState &State) {
+  // On the second pass, go through the HVAs only.
+  if (ArgFlags.isSecArgPass()) {
+    if (ArgFlags.isHva())
+      for (MCPhysReg RegB : CC_X86_VectorCallGetSSEs(ValVT))
+        if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+          return true;
+
+    return true;
+  }
+
+  // Process only vector types as defined by vectorcall spec:
+  // "A vector type is either a floating-point type, for example,
+  //  a float or double, or an SIMD vector type, for example, __m128 or __m256".
+  if (!(ValVT.isFloatingPoint() ||
+        (ValVT.isVector() && ValVT.getSizeInBits() >= 128)))
+    return State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, X86::R9);
+
+  if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {
+    for (MCPhysReg RegB : CC_X86_64_VectorCallGetGPRs())
+      if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+        return true;
+
+    for (MCPhysReg RegB : CC_X86_VectorCallGetSSEs(ValVT))
+      if (State.getTargetRegisterInfo().isSuperOrSubRegisterEq(RegA, RegB))
+        return true;
+  }
+
+  return false;
+}
+
 // Provides entry points of CC_X86 and RetCC_X86.
 #include "X86GenCallingConv.inc"

llvm/lib/Target/X86/X86RegisterInfo.h

public:
   const uint32_t *getDarwinTLSCallPreservedMask() const;
 
   /// getReservedRegs - Returns a bitset indexed by physical register number
   /// indicating if a register is a special register that has particular uses and
   /// should be considered unavailable at all times, e.g. SP, RA. This is used by
   /// register scavenger to determine what registers are free.
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
-  /// isArgumentReg - Returns true if Reg can be used as an argument to a
-  /// function.
-  bool isArgumentRegister(const MachineFunction &MF,
-                          MCRegister Reg) const override;
+  /// isCCArgumentReg - Returns true if PhysReg is part of the calling
+  /// convention.
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 
   /// Returns true if PhysReg is a fixed register.
   bool isFixedRegister(const MachineFunction &MF,
                        MCRegister PhysReg) const override;
 
   void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
 
   bool hasBasePointer(const MachineFunction &MF) const;

llvm/lib/Target/X86/X86RegisterInfo.cpp

BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   }
 
   assert(checkAllSuperRegsMarked(Reserved,
                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
                                   X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
   return Reserved;
 }
 
-bool X86RegisterInfo::isArgumentRegister(const MachineFunction &MF,
-                                         MCRegister Reg) const {
+bool X86RegisterInfo::isCCArgumentReg(MachineFunction &MF,
   const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
   const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
   auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) {
     return TRI.isSuperOrSubRegisterEq(RegA, RegB);
   };
 
   if (!ST.is64Bit())
     return llvm::any_of(

llvm/lib/Target/XCore/XCoreISelLowering.cpp

if (AI->isAtomic())
       return MachineMemOperand::MOVolatile;
   return MachineMemOperand::MONone;
 }
 
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
+#define CC_ASSIGN_REGS_ONLY
 #include "XCoreGenCallingConv.inc"
 
 //===----------------------------------------------------------------------===//
 //                  Call Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
 /// XCore call implementation
 SDValue

llvm/lib/Target/XCore/XCoreRegisterInfo.h

 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
 #include "XCoreGenRegisterInfo.inc"
 
 namespace llvm {
 
-struct XCoreRegisterInfo : public XCoreGenRegisterInfo {
-public:
+struct XCoreRegisterInfo final : public XCoreGenRegisterInfo {
   XCoreRegisterInfo();
 
   /// Code Generation virtual methods...
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
 
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   // Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   //! Return whether to emit frame moves
   static bool needsFrameMoves(const MachineFunction &MF);
+
+  bool isCCArgumentReg(MachineFunction &MF, MCRegister Reg) const override;
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/XCore/XCoreRegisterInfo.cpp

 
 #include "XCoreRegisterInfo.h"
 #include "XCore.h"
 #include "XCoreInstrInfo.h"
 #include "XCoreMachineFunctionInfo.h"
 #include "XCoreSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "xcore-reg-info"
 
 #define GET_REGINFO_TARGET_DESC

 }
 
 
 Register XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const XCoreFrameLowering *TFI = getFrameLowering(MF);
 
   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
 }
+
+#define CC_CHECK_REGS_ONLY
+#include "XCoreGenCallingConv.inc"
+
+bool XCoreRegisterInfo::isCCArgumentReg(MachineFunction &MF,
+                                        MCRegister Reg) const {
+  const Function &F = MF.getFunction();
+  const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, RVLocs, F.getContext());
+  MVT VT = MVT(*legalclasstypes_begin(*RC));
+  ISD::ArgFlagsTy ArgFlags;
+  ArgFlags.setInReg();
+
+  return CC_XCore_IsCCReg(Reg, 0, VT, VT, ArgFlags, CCInfo);
+}

llvm/unittests/CodeGen/MFCommon.inc

public:
   }
 
   Register getFrameRegister(const MachineFunction &MF) const override {
     return 0;
   }
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override {}
+
+  bool isCCArgumentReg(MachineFunction &, MCRegister) const override {
+    return false;
+  }
 };
 
 class BogusSubtarget : public TargetSubtargetInfo {
 public:
   BogusSubtarget(TargetMachine &TM)
       : TargetSubtargetInfo(Triple(""), "", "", "", {}, {}, nullptr, nullptr,
                             nullptr, nullptr, nullptr, nullptr),
         FL(), TL(TM) {}

llvm/utils/TableGen/CallingConvEmitter.cpp

 public:
   explicit CallingConvEmitter(RecordKeeper &R) : Records(R) {}
 
   void run(raw_ostream &o);
 
 private:
   void EmitCallingConv(Record *CC, raw_ostream &O);
   void EmitAction(Record *Action, unsigned Indent, raw_ostream &O);
+  void EmitCCRegisterQuery(Record *CC, raw_ostream &O);
+  void EmitQueryAction(Record *Action, unsigned Indent, raw_ostream &O);
   unsigned Counter;
 };
 } // End anonymous namespace
 
 void CallingConvEmitter::run(raw_ostream &O) {
   std::vector<Record*> CCs = Records.getAllDerivedDefinitions("CallingConv");
+  if (CCs.empty())
+    return;
 
   // Emit prototypes for all of the non-custom CC's so that they can forward ref
   // each other.
+  O << "#ifndef CC_CHECK_REGS_ONLY\n";
+
   Records.startTimer("Emit prototypes");
   for (Record *CC : CCs) {
     if (!CC->getValueAsBit("Custom")) {
       unsigned Pad = CC->getName().size();
       if (CC->getValueAsBit("Entry")) {
         O << "bool llvm::";
         Pad += 12;
       } else {
         O << "static bool ";
         Pad += 13;
       }
       O << CC->getName() << "(unsigned ValNo, MVT ValVT,\n"
         << std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
         << std::string(Pad, ' ')
         << "ISD::ArgFlagsTy ArgFlags, CCState &State);\n";
     }
   }
 
   // Emit each non-custom calling convention description in full.
   Records.startTimer("Emit full descriptions");
   for (Record *CC : CCs) {
     if (!CC->getValueAsBit("Custom"))
       EmitCallingConv(CC, O);
   }
+
+  O << "#endif // !CC_CHECK_REGS_ONLY\n";
+
+  O << "\n#ifndef CC_ASSIGN_REGS_ONLY\n";
+
+  // Emit function to check if a register is part of the calling convention.
+  O << "// Function to determine if a register is part of the calling "
+    << "convention.\n\n";
+
+  for (Record *CC : CCs) {
+    if (!CC->getValueAsBit("Custom")) {
+      if (CC->getName().startswith("RetCC_") ||
+          CC->getName().startswith("RetFastCC_"))
+        continue;
+
+      unsigned Pad = CC->getName().size();
+      if (CC->getValueAsBit("Entry")) {
+        O << "bool llvm::";
+        Pad += 12;
+      } else {
+        O << "static bool ";
+        Pad += 13;
+      }
+
+      O << CC->getName() << "_IsCCReg(MCPhysReg RegA, unsigned ValNo, "
+        << "MVT ValVT, MVT LocVT, ISD::ArgFlagsTy ArgFlags, "
+        << "CCState &State);\n";
+    }
   }
 
+  // Emit each non-custom calling convention description in full.
+  Records.startTimer("Emit full descriptions");
+  for (Record *CC : CCs)
+    if (!CC->getValueAsBit("Custom") &&
+        !(CC->getName().startswith("RetCC_") ||
+          CC->getName().startswith("RetFastCC_")))
+      EmitCCRegisterQuery(CC, O);
+
+  O << "#endif // !CC_ASSIGN_REGS_ONLY\n";
+}
 
 void CallingConvEmitter::EmitCallingConv(Record *CC, raw_ostream &O) {
   ListInit *CCActions = CC->getValueAsListInit("Actions");
   Counter = 0;
 
   O << "\n\n";
   unsigned Pad = CC->getName().size();
   if (CC->getValueAsBit("Entry")) {
if (Action->isSubClassOf("CCDelegateTo")) {
       O << IndentStr << "  return false;\n";
     } else {
       errs() << *Action;
       PrintFatalError(Action->getLoc(), "Unknown CCAction!");
     }
   }
 }
 
+void CallingConvEmitter::EmitCCRegisterQuery(Record *CC, raw_ostream &O) {
+  ListInit *CCActions = CC->getValueAsListInit("Actions");
+  Counter = 0;
+
+  O << "\n\n";
+  unsigned Pad = CC->getName().size();
+  if (CC->getValueAsBit("Entry")) {
+    O << "bool llvm::";
+    Pad += 12;
+  } else {
+    O << "static bool ";
+    Pad += 13;
+  }
+  O << CC->getName() << "_IsCCReg(MCPhysReg RegA, unsigned ValNo, MVT ValVT, "
+    << "MVT LocVT, ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
+
+  // Emit all of the actions, in order.
+  for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
+    O << "\n";
+    EmitQueryAction(CCActions->getElementAsRecord(i), 2, O);
+  }
+
+  O << "\n  return false; // Register not part of CC.\n";
+  O << "}\n";
+}
+
+void CallingConvEmitter::EmitQueryAction(Record *Action, unsigned Indent,
+                                         raw_ostream &O) {
+  std::string IndentStr = std::string(Indent, ' ');
+
+  if (Action->isSubClassOf("CCPredicateAction")) {
+    O << IndentStr << "if (";
+
+    if (Action->isSubClassOf("CCIfType")) {
+      ListInit *VTs = Action->getValueAsListInit("VTs");
+      for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
+        Record *VT = VTs->getElementAsRecord(i);
+        if (i != 0)
+          O << " ||\n    " << IndentStr;
+        O << "LocVT == " << getEnumName(getValueType(VT));
+      }
+    } else if (Action->isSubClassOf("CCIf")) {
+      O << Action->getValueAsString("Predicate");
+    } else {
+      errs() << *Action;
+      PrintFatalError(Action->getLoc(), "Unknown CCPredicateAction!");
+    }
+
+    O << ") {\n";
+    EmitQueryAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
+    O << IndentStr << "}\n";
+    return;
+  }
+
+  if (Action->isSubClassOf("CCDelegateTo")) {
+    Record *CC = Action->getValueAsDef("CC");
+    O << IndentStr << "if (" << CC->getName() << "_IsCCReg("
+      << "RegA, ValNo, ValVT, LocVT, ArgFlags, State))\n"
+      << IndentStr << "  return true;\n";
+  } else if (Action->isSubClassOf("CCAssignToReg")) {
+    ListInit *RegList = Action->getValueAsListInit("RegList");
+    if (RegList->size() == 1) {
+      O << IndentStr << "if (State.getTargetRegisterInfo()"
+        << ".isSuperOrSubRegisterEq(RegA, "
+        << getQualifiedName(RegList->getElementAsRecord(0)) << "))\n"
+        << IndentStr << "  return true;\n";
+    } else {
+      O << IndentStr << "static const MCPhysReg RegList" << ++Counter
+        << "[] = {\n"
+        << IndentStr << "  ";
+
+      ListSeparator LS;
+      for (unsigned i = 0, e = RegList->size(); i != e; ++i)
+        O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+      O << "\n" << IndentStr << "};\n";
+
+      O << IndentStr << "for (MCPhysReg RegB : RegList" << Counter << ") {\n"
+        << IndentStr << "  if (State.getTargetRegisterInfo()"
+        << ".isSuperOrSubRegisterEq(RegA, RegB)) {\n"
+        << IndentStr << "    return true;\n"
+        << IndentStr << "  }\n"
+        << IndentStr << "}\n";
+    }
+  } else if (Action->isSubClassOf("CCAssignToRegWithShadow")) {
+    ListInit *RegList = Action->getValueAsListInit("RegList");
+
+    if (RegList->size() == 1) {
+      O << IndentStr << "if (State.getTargetRegisterInfo()"
+        << ".isSuperOrSubRegisterEq(RegA, "
+        << getQualifiedName(RegList->getElementAsRecord(0)) << "))\n"
+        << IndentStr << "  return true;\n";
+    } else {
+      O << IndentStr << "static const MCPhysReg RegList" << ++Counter
+        << "[] = {\n";
+      O << IndentStr << "  ";
+
+      ListSeparator LS;
+      for (unsigned i = 0, e = RegList->size(); i != e; ++i)
+        O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+      O << "\n" << IndentStr << "};\n";
+
+      O << IndentStr << "for (MCPhysReg RegB : RegList" << Counter << ") {\n"
+        << IndentStr << "  if (State.getTargetRegisterInfo()"
+        << ".isSuperOrSubRegisterEq(RegA, RegB)) {\n"
+        << IndentStr << "    return true;\n"
+        << IndentStr << "  }\n"
+        << IndentStr << "}\n";
+    }
+  } else if (Action->isSubClassOf("CCPromoteToType") ||
+             Action->isSubClassOf("CCPromoteToUpperBitsInType") ||
+             Action->isSubClassOf("CCBitConvertToType") ||
+             Action->isSubClassOf("CCTruncToType") ||
+             Action->isSubClassOf("CCPassIndirect")) {
+    Record *DestTy = Action->getValueAsDef("DestTy");
+    MVT::SimpleValueType DestVT = getValueType(DestTy);
+    O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n";
+  } else if (Action->isSubClassOf("CCCustom")) {
+    O << IndentStr << "if (" << Action->getValueAsString("FuncName")
+      << "_IsCCReg(RegA, ValNo, ValVT, LocVT, ArgFlags, State))\n";
+    O << IndentStr << "  return true;\n";
+  } else if (Action->isSubClassOf("CCAssignToStack") ||
+             Action->isSubClassOf("CCAssignToStackWithShadow") ||
+             Action->isSubClassOf("CCPassByVal")) {
+    // Do nothing.
+  } else {
+    errs() << *Action;
+    PrintFatalError(Action->getLoc(), "Unknown CCAction!");
+  }
+}
+
 namespace llvm {
 
 void EmitCallingConv(RecordKeeper &RK, raw_ostream &OS) {
   emitSourceFileHeader("Calling Convention Implementation Fragment", OS);
   CallingConvEmitter(RK).run(OS);
 }
 
 } // End llvm namespace