User Details
- User Since
- Mar 6 2013, 6:15 AM (410 w, 3 d)
Thu, Jan 14
LGTM
Nov 25 2020
LGTM
Nov 13 2020
Nov 4 2020
My bad, I missed that you implemented passing the option to backend.
Nov 2 2020
What's a goal of this change? Do you want to suppress an error message when the option provided to Clang? If so, is it a real-life case?
Oct 30 2020
Oct 28 2020
LGTM with a few nits. Thanks.
Oct 12 2020
MIPS changes LGTM
Oct 9 2020
LGTM
Oct 6 2020
LGTM. Thanks!
Sep 29 2020
LGTM
Sep 25 2020
LGTM
Sep 24 2020
LGTM
Sep 20 2020
LGTM
Aug 17 2020
LGTM
Aug 7 2020
LGTM
LGTM
Jul 29 2020
LGTM
Jul 17 2020
LGTM. Thanks
Jul 16 2020
LGTM
Jul 15 2020
Maybe it's better to switch off generation of the madd.fmt by default if the problem is so wide spread? I'm concerned that AFAIK no one other architectures supported by LLVM has configuration options like the proposed LLVM_DISABLE_MIPS_MADD4.
Jul 14 2020
Do you have commit access?
Jul 6 2020
LGTM. Thanks
Jun 19 2020
Do you have commit access?
Jun 16 2020
Does this patch depend on D81919?
Please include context in all patches sent to review.
To get a full diff, use one of the following commands:
git show HEAD -U999999 > mypatch.patch git diff -U999999 @{u} > mypatch.patch git diff HEAD~1 -U999999 > mypatch.patch
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface
Jun 3 2020
Jun 2 2020
I cannot select default behaviour for the LLVM in case of generating .eh_frame sections for MIPS:
- Unconditionally use pc-relative relocations.
- Use pc-relative relocations by default, but provide options for switching to absolute relocations.
- Use absolute relocations by default, but provide options for switching to pc-relative relocations.
Thanks for review, testing and comments.
May 22 2020
- Please include as much context as possible with your diff. This instruction helps to do that.
- Such patch needs test case(s). Maybe it's enough to update the linux-ld.c test case which is failed now. Update failed cases and check both "soft" and "hard" float cases in this test.
May 21 2020
May 13 2020
May 7 2020
Looks good overall, just a few nits inline.
May 1 2020
Initially the test case just checks that LLD does not crash under some conditions. It's not mandatory to test exact symbols' values and/or offsets between symbols. But after this fix the test additionally becomes more tolerant to exact symbol addresses. It's fine.
As to me, I'd remove the "Ideally we'd use..." comment.
Apr 24 2020
Apr 3 2020
I have fixed MIPS-related mistakes at rGf22445b. Thanks for finding them.
Mar 27 2020
LGTM. Two nits inlined.
Mar 22 2020
Thanks for the catching the issues.
Mar 17 2020
LGTM
Mar 15 2020
Mar 13 2020
LGTM Thanks for the patch.
Mar 8 2020
The following test cases failed on my machine. Initially, assembler shows error: unknown instruction. Now assembler shows correct error message instruction requires a CPU feature not currently enabled and the checks should be updated and moved to invalid-xxx.s files.
MC/Mips/mips1/invalid-mips5-wrong-error.s MC/Mips/mips2/invalid-mips5-wrong-error.s MC/Mips/mips3/invalid-mips5-wrong-error.s MC/Mips/mips4/invalid-mips5-wrong-error.s MC/Mips/mips64r6/invalid-mips5-wrong-error.s
Feb 27 2020
Feb 26 2020
Feb 16 2020
LGTM
LGTM
LGTM
Feb 10 2020
Looking good to me as-is.
Feb 6 2020
I see, thanks. Is there the same or similar functionality in GCC?
Jan 30 2020
Is it possible to emulate these new intrinsics using existing ones and some additional code? Is code generated in this case much larger/slower then the code generated by the new intrinsics?
Jan 29 2020
LGTM
Thanks
Jan 27 2020
LGTM
Thanks
Jan 26 2020
Closed by commit rG27f93515.
Jan 25 2020
LGTM
Jan 23 2020
LGTM
LGTM
Jan 21 2020
- Add llvm-exegesis note.
Jan 17 2020
LGTM
Jan 16 2020
LGTM
LGTM
I'll take a look on MIPS vector register definitions. Four register classes looks really ill formed.
Jan 13 2020
LGTM
Jan 11 2020
I'm sorry for the delay. The patch is LGTM.
Thanks.
Jan 6 2020
LGTM
Jan 4 2020
Dec 27 2019
LGTM
Dec 25 2019
LGTM
Dec 17 2019
LGTM
Dec 16 2019
LGTM