tstellar (Tom Stellard)
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User Since
Feb 9 2017, 1:53 PM (40 w, 4 d)

Recent Activity

Today

tstellar added a comment to D34848: Driver: Don't mix system tools with devtoolset tools on RHEL.

Ping.

Tue, Nov 21, 5:41 AM

Yesterday

tstellar added inline comments to D35755: [Solaris] gcc toolchain handling revamp.
Mon, Nov 20, 5:27 AM

Fri, Nov 17

tstellar committed rL318542: Merging r318289:.
Merging r318289:
Fri, Nov 17, 10:48 AM

Wed, Nov 15

tstellar committed rL318346: Merging r312748:.
Merging r312748:
Wed, Nov 15, 2:42 PM
tstellar committed rL318344: Merging r312043:.
Merging r312043:
Wed, Nov 15, 2:27 PM
tstellar committed rL318333: Merging r310475:.
Merging r310475:
Wed, Nov 15, 12:49 PM
tstellar committed rL318315: Merging r315578:.
Merging r315578:
Wed, Nov 15, 9:51 AM

Tue, Nov 14

tstellar added a comment to D40047: AMDGPU/GCN: Remove xnack from 801 and 810.

Does this change break backwards compatibility with the gfx801 target? If so, which ROCm version will I need to use with these changes?

Tue, Nov 14, 5:58 PM
tstellar committed rL318236: Merging r313776:.
Merging r313776:
Tue, Nov 14, 4:21 PM
tstellar committed rL318233: Merging r315464:.
Merging r315464:
Tue, Nov 14, 4:08 PM
tstellar committed rL318225: Merging r310905 and r310994:.
Merging r310905 and r310994:
Tue, Nov 14, 3:53 PM
tstellar committed rL318192: Merging r315310:.
Merging r315310:
Tue, Nov 14, 12:49 PM
tstellar committed rL318191: Merging r317204 and r318172:.
Merging r317204 and r318172:
Tue, Nov 14, 12:40 PM
tstellar committed rL318188: Merging r317470:.
Merging r317470:
Tue, Nov 14, 12:10 PM
tstellar committed rL318183: Merging r314798:.
Merging r314798:
Tue, Nov 14, 11:56 AM
tstellar committed rL318181: Merging r310543:.
Merging r310543:
Tue, Nov 14, 11:47 AM
tstellar committed rL318180: Merging r310522:.
Merging r310522:
Tue, Nov 14, 11:43 AM
tstellar committed rL318178: Merging r317115:.
Merging r317115:
Tue, Nov 14, 11:22 AM
tstellar committed rL318176: Merging r316452:.
Merging r316452:
Tue, Nov 14, 11:22 AM
tstellar committed rL318175: Merging r311269:.
Merging r311269:
Tue, Nov 14, 11:17 AM
tstellar committed rL318171: Merging r309875:.
Merging r309875:
Tue, Nov 14, 11:11 AM

Mon, Nov 13

tstellar committed rL318133: Merging r313278:.
Merging r313278:
Mon, Nov 13, 6:40 PM
tstellar committed rL318120: Merging r315611:.
Merging r315611:
Mon, Nov 13, 4:18 PM
tstellar committed rL318118: Merging r315586:.
Merging r315586:
Mon, Nov 13, 4:02 PM
tstellar committed rL318116: Merging r313675:.
Merging r313675:
Mon, Nov 13, 3:52 PM
tstellar committed rL318114: Merging r312296:.
Merging r312296:
Mon, Nov 13, 3:43 PM
tstellar committed rL318113: Merging r312292:.
Merging r312292:
Mon, Nov 13, 3:37 PM
tstellar committed rL318107: Merging r311777:.
Merging r311777:
Mon, Nov 13, 3:26 PM
tstellar committed rL318105: Merging r311013:.
Merging r311013:
Mon, Nov 13, 3:13 PM
tstellar committed rL318099: Merging r309288:.
Merging r309288:
Mon, Nov 13, 2:52 PM
tstellar committed rL318096: Merging r316824:.
Merging r316824:
Mon, Nov 13, 2:27 PM
tstellar committed rL318088: Merging r312693:.
Merging r312693:
Mon, Nov 13, 1:28 PM

Thu, Nov 9

tstellar accepted D39880: AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td.

LGTM.

Thu, Nov 9, 4:39 PM
tstellar added a comment to D39828: AMDGPU: Update code object description.

Will this change be backwards compatible? If not, could you add to the documentation which version of the ROCm runtime is required for the new format.

Thu, Nov 9, 3:47 PM
tstellar added a comment to D39828: AMDGPU: Update code object description.

Does this mean the code object format has changed?

Thu, Nov 9, 3:43 PM
tstellar updated subscribers of D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

! In D39670#919711, @yaxunl wrote:

As Matt said, the risk of having two sets of address space mapping is high. Also I estimate the workload to switch r600 to the new addr space mapping is moderate. On the hand, the workload for separating r600 from amdgcn is high.

Thu, Nov 9, 9:21 AM

Wed, Nov 8

tstellar added a comment to D38128: Handle COPYs of physregs better (regalloc hints).

I think the changes to the multilevel-break.ll test are OK. The register usage is increased by 2, but this won't have any impact on performance for this test. Here is a patch to make this test pass with your changes: https://reviews.llvm.org/P8046

Wed, Nov 8, 5:47 AM

Tue, Nov 7

tstellar added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

We discussed this internally and concluded that having a static address space mapping is more important. Most of issues are due to using dummy pointer info. Such places should be few in r600 code, therefore we will continue fixing these issues unless we found there need excessive efforts to do so.

Tue, Nov 7, 7:29 PM
tstellar added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

r600 doesn't support generic address space, so in that case, I would recommend only defining an intrinsic to be used by amdgcn. I understand the problem with non-constant address spaces, but I think the best solution here would be to try to make more of a separation between the amdgcn code and the r600 code in the backend rather than trying to change the address space mapping for r600. r600 should really be mostly read-only at this point.

Tue, Nov 7, 10:24 AM
tstellar added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Which intrinsic functions are you refering to? To me it seems easier to not touch r600 at all, but I guess I'm not as deep into the code as you. Can you give me some specific examples for how adding support to r600 for this alternative mapping simplifies the backend?

Tue, Nov 7, 9:57 AM
tstellar added a comment to D39670: [AMDGPU] Fix pointer info for pseudo source for r600.

Why are we trying to use this alternative address space mapping for r600?

Tue, Nov 7, 9:04 AM

Mon, Nov 6

tstellar added a comment to D38128: Handle COPYs of physregs better (regalloc hints).

The AMDGPU tests look OK, but the CHECK lines for test/CodeGen/AMDGPU/sgpr-control-flow.ll should be updated like this:
https://reviews.llvm.org/P8044

Mon, Nov 6, 3:14 PM

Wed, Nov 1

tstellar committed rL317161: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:12 PM
tstellar committed rL317157: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:07 PM
tstellar committed rL317173: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:06 PM
tstellar committed rL317179: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:05 PM
tstellar committed rL317178: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:05 PM
tstellar committed rL317177: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:05 PM
tstellar committed rL317176: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:05 PM
tstellar committed rL317175: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:05 PM
tstellar committed rL317174: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:04 PM
tstellar committed rL317159: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:04 PM
tstellar committed rL317172: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:03 PM
tstellar committed rL317170: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:03 PM
tstellar committed rL317169: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:02 PM
tstellar committed rL317168: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:02 PM
tstellar committed rL317167: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:02 PM
tstellar committed rL317166: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 7:02 PM
tstellar committed rL317165: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 7:01 PM
tstellar committed rL317164: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 6:58 PM
tstellar committed rL317163: Creating release candidate rc1 from release_501 branch.
Creating release candidate rc1 from release_501 branch
Wed, Nov 1, 6:58 PM
tstellar committed rL317162: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 6:56 PM
tstellar committed rL317160: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 6:56 PM
tstellar committed rL317158: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 6:55 PM
tstellar committed rL317156: Creating release directory for release_501..
Creating release directory for release_501.
Wed, Nov 1, 6:55 PM

Fri, Oct 27

tstellar committed rL316815: AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal.
AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal
Fri, Oct 27, 4:58 PM
tstellar closed D38439: AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal by committing rL316815: AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal.
Fri, Oct 27, 4:58 PM

Wed, Oct 25

tstellar committed rL316607: Merging r315485:.
Merging r315485:
Wed, Oct 25, 1:57 PM

Tue, Oct 24

tstellar added inline comments to D38439: AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal.
Tue, Oct 24, 11:46 AM

Oct 16 2017

tstellar added a comment to D38959: AMDGPU: Don't use TargetStreamer if it has not been initialized.

Why is this necessary? Do other targets need to do ths?

Oct 16 2017, 9:37 AM

Oct 12 2017

tstellar committed rL315663: Merging r312357:.
Merging r312357:
Oct 12 2017, 7:33 PM

Oct 11 2017

tstellar added a comment to D37230: Set hasSideEffects=0 for TargetOpcode::BUNDLE.

I think this is failing because the s_add_u32 s32, s32, 0xc00{{$}} is moved after the loads.

Oct 11 2017, 9:19 AM
tstellar added a comment to D38128: Handle COPYs of physregs better (regalloc hints).

Unfortunately, all the AMDGPU testcases that change from using vcc to a regular sgpr are regressions. Do you have any idea why this is happening?

I found out that since AMDGPU is passing regalloc hints with type 0 (generic), those VCC hints got cleared. After thinking about it, I thought that it would still be good to let target pass hints of type 0 since otherwise target would always have to implement getRegAllocationHints() unnecessarily. I first thought that perhaps type-0 hints should only get cleared if they are not rediscovered (recomputed) in calculateSpillWeightAndHint(). That saved the VCC reg from being removed. But I then realized that it would not make sense to ever remove a target hint, even if it is type-0. It should not be added by target unless there is a special reason for doing so making it more important than other hints, even if it is a COPY hint with less weight than others (not sure that would happen). So I removed the clearRegAllocationHints(). This means target can always add a hint and expect it to be first in the hints vector.

For AMDGPU, that meant a lot of the FAILs disappeared, which was nice. There are a few left:

  • a lot of v_cmp_eq_f32_e64 -> v_cmp_eq_f32_e32. Is it OK?
Oct 11 2017, 9:04 AM

Oct 10 2017

tstellar committed rL315353: Merging r314513:.
Merging r314513:
Oct 10 2017, 12:58 PM
tstellar added a comment to D38128: Handle COPYs of physregs better (regalloc hints).

Unfortunately, all the AMDGPU testcases that change from using vcc to a regular sgpr are regressions. Do you have any idea why this is happening?

Oct 10 2017, 8:21 AM

Oct 9 2017

tstellar committed rL315224: Merging r309979:.
Merging r309979:
Oct 9 2017, 11:02 AM

Sep 29 2017

tstellar committed rL314583: Fix formatting in 5.0.1 release schedule..
Fix formatting in 5.0.1 release schedule.
Sep 29 2017, 8:39 PM
tstellar committed rL314582: Add 5.0.1 release schedule.
Add 5.0.1 release schedule
Sep 29 2017, 8:38 PM
tstellar created D38439: AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal.
Sep 29 2017, 8:17 PM
tstellar committed rL314569: Merging r313392:.
Merging r313392:
Sep 29 2017, 4:54 PM
tstellar committed rL314567: Merging r311951 and r312038:.
Merging r311951 and r312038:
Sep 29 2017, 4:40 PM
tstellar committed rL314565: Merging r312348:.
Merging r312348:
Sep 29 2017, 4:24 PM
tstellar committed rL314555: Merging r314252:.
Merging r314252:
Sep 29 2017, 1:36 PM
tstellar committed rL314554: Merging r314251:.
Merging r314251:
Sep 29 2017, 1:32 PM
tstellar committed rL314553: Merging r311599:.
Merging r311599:
Sep 29 2017, 1:28 PM
tstellar accepted D37753: [AMDGPU] implemented pal metadata.

Could you add tests for the AsmParser changes, otherwise LGTM.

Sep 29 2017, 8:51 AM

Sep 28 2017

tstellar committed rL314476: Merging r312447:.
Merging r312447:
Sep 28 2017, 4:43 PM
tstellar committed rL314464: Merging r312651:.
Merging r312651:
Sep 28 2017, 2:59 PM
tstellar committed rL314437: Merging r313998:.
Merging r313998:
Sep 28 2017, 10:54 AM
tstellar committed rL314434: Merging r312622:.
Merging r312622:
Sep 28 2017, 10:24 AM

Sep 27 2017

tstellar committed rL314327: Merging r312337:.
Merging r312337:
Sep 27 2017, 11:10 AM
tstellar committed rL314326: Revert "Merging r312337:".
Revert "Merging r312337:"
Sep 27 2017, 11:08 AM
tstellar committed rL314324: Merging r312337:.
Merging r312337:
Sep 27 2017, 10:58 AM

Sep 18 2017

tstellar committed rL313609: docs: Fix formatting in HowToReleaseLLVM.
docs: Fix formatting in HowToReleaseLLVM
Sep 18 2017, 8:29 PM
tstellar committed rL313608: docs: Add instructions for how to submit a merge request.
docs: Add instructions for how to submit a merge request
Sep 18 2017, 8:24 PM
tstellar closed D37936: docs: Add instructions for how to submit a merge request by committing rL313608: docs: Add instructions for how to submit a merge request.
Sep 18 2017, 8:24 PM

Sep 15 2017

tstellar updated the diff for D37936: docs: Add instructions for how to submit a merge request.

Address review comments.

Sep 15 2017, 10:29 PM
tstellar created D37936: docs: Add instructions for how to submit a merge request.
Sep 15 2017, 2:53 PM

Sep 14 2017

tstellar committed rL313339: Bump version to 5.0.1.
Bump version to 5.0.1
Sep 14 2017, 9:07 PM
tstellar committed rL313337: Merging r313334:.
Merging r313334:
Sep 14 2017, 8:07 PM