Add f64 patterns

In D46365#1132085, @jvesely wrote:

I've tried the updated version of the patch, although it did not apply cleanly. It also causes GPU hangs on my turks in piglit tests.

Ping.

In D46150#1082433, @nhaehnle wrote:

Is the default implementation really unable to do this? That seems a bit silly...

We also need to constrain the register class when we select G_IMPLICIT_DEF.

Rebase patch on latest ToT.

Move isSDNodeSourceOfDivergence() implementation from AMDGPUTargetLowering
to SITargetLowering.

Ping.

Remove unused options and document how to use the script.

Completely disable isSDNodeSourceOfDivergence() for r600.

Rebase patch after splitting some of the changes requested
into separate patches.

In D46298#1110789, @arsenm wrote:

In D46298#1110788, @alex-t wrote:

I agree isVGPR should be illegal to call for R600

So, how would you handle the bunch of r600 tests then?
We could claim the support of DA related stuff for GCN only but it should be explicitly agreed and documented somehow.

Disable this for r600. It doesn't have the SGPR/VGPR split issue we want this for, so it doesn't really matter

Move getTargetTransforInfo to TargetMachine sub-classes.

Removed unused Processors.td file and made all AMDGPUCommonSubtarget
functions non-virtual.

In D46298#1086262, @alex-t wrote:

Could you please clarify - why do you consider that check meaningless for r600?
I see that this line : " const SISubtarget &ST = MF->getSubtarget<SISubtarget>(); " is misleading and in fact is not correct.
I'd better check and choose the R600Subtarget or SISubtarget.
If I understand right we need just check which subtarget to retrieve for physregs check.

Since we consider any VGPR formal argument as divergent it does not matter R600 or SI at all.
We need to choose right TargetRegisterInfo (r600 or SI again)

So, for virtual register : if (MRI.isLiveIn(Reg) && TRI.isVGPR(Reg) ) return true

Or I maybe don't know something substantial? :)