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asavonic (Andrew Savonichev)
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User Since
Jun 2 2016, 11:01 PM (263 w, 3 d)

Recent Activity

Wed, Jun 16

asavonic added a comment to D98895: [X86][Draft] Disable long double type for -mno-x87 option.

@erichkeane, can you please check if this patch is OK for Clang?

Wed, Jun 16, 8:41 AM · Restricted Project
asavonic added a reviewer for D98895: [X86][Draft] Disable long double type for -mno-x87 option: erichkeane.
Wed, Jun 16, 8:40 AM · Restricted Project

Wed, Jun 9

asavonic added inline comments to D103955: [MCA] Use LSU for the in-order pipeline.
Wed, Jun 9, 6:59 AM · Restricted Project
asavonic updated the summary of D103955: [MCA] Use LSU for the in-order pipeline.
Wed, Jun 9, 4:53 AM · Restricted Project
asavonic requested review of D103955: [MCA] Use LSU for the in-order pipeline.
Wed, Jun 9, 4:52 AM · Restricted Project

Mon, Jun 7

asavonic committed rGb31f41e78b27: [Clang] Support a user-defined __dso_handle (authored by asavonic).
[Clang] Support a user-defined __dso_handle
Mon, Jun 7, 2:55 AM
asavonic closed D101156: [Clang] Support a user-defined __dso_handle.
Mon, Jun 7, 2:55 AM · Restricted Project

Sun, Jun 6

asavonic added inline comments to D101156: [Clang] Support a user-defined __dso_handle.
Sun, Jun 6, 2:58 PM · Restricted Project
asavonic updated the diff for D101156: [Clang] Support a user-defined __dso_handle.
  • Used llvm::TrackingVH to track Init changes.
Sun, Jun 6, 2:52 PM · Restricted Project

Thu, Jun 3

asavonic added a comment to D101156: [Clang] Support a user-defined __dso_handle.

ping

Thu, Jun 3, 3:15 AM · Restricted Project

Fri, May 28

asavonic added a comment to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

ping

Fri, May 28, 2:22 AM · Restricted Project

Thu, May 27

asavonic updated the diff for D98895: [X86][Draft] Disable long double type for -mno-x87 option.
  • Disabled double or float return for x86 targets
  • Refactored checks into a separate function.
Thu, May 27, 4:12 AM · Restricted Project

Wed, May 26

asavonic committed rG8ac66d61eab3: [AArch64] Generate LD1 for anyext i8 or i16 vector load (authored by asavonic).
[AArch64] Generate LD1 for anyext i8 or i16 vector load
Wed, May 26, 4:49 AM
asavonic closed D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load.
Wed, May 26, 4:49 AM · Restricted Project

Tue, May 25

asavonic added inline comments to D98895: [X86][Draft] Disable long double type for -mno-x87 option.
Tue, May 25, 5:40 AM · Restricted Project

Mon, May 24

asavonic updated the diff for D98895: [X86][Draft] Disable long double type for -mno-x87 option.

Added LIT run lines for i686 and windows targets.

Mon, May 24, 10:16 AM · Restricted Project
asavonic added inline comments to D98895: [X86][Draft] Disable long double type for -mno-x87 option.
Mon, May 24, 10:14 AM · Restricted Project
asavonic updated the summary of D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load.
Mon, May 24, 9:05 AM · Restricted Project
asavonic updated the diff for D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load.

Sounds good. Can we make sure there is test coverage for big endian too.

Mon, May 24, 8:55 AM · Restricted Project
asavonic added a comment to D101156: [Clang] Support a user-defined __dso_handle.

I went ahead and implemented a fix for EmitGlobalVarDefinition. Please let me know what approach is preferable: Diff 339986 or Diff 347341.

Mon, May 24, 4:32 AM · Restricted Project
asavonic updated the diff for D101156: [Clang] Support a user-defined __dso_handle.
Mon, May 24, 3:54 AM · Restricted Project

May 21 2021

asavonic updated the summary of D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load.
May 21 2021, 11:55 AM · Restricted Project
asavonic updated the summary of D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load.
May 21 2021, 11:53 AM · Restricted Project
asavonic requested review of D102939: [AArch64] Lower INSERT_SUBVECTOR to LD1_POST.
May 21 2021, 11:51 AM · Restricted Project
asavonic added a reviewer for D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load: t.p.northover.
May 21 2021, 11:43 AM · Restricted Project
asavonic added reviewers for D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load: SjoerdMeijer, jmolloy.
May 21 2021, 11:42 AM · Restricted Project
asavonic requested review of D102938: [AArch64] Generate LD1 for anyext i8 or i16 vector load.
May 21 2021, 11:41 AM · Restricted Project

May 20 2021

asavonic committed rGa647100b4320: [AArch64] Combine vector shift instructions in SelectionDAG (authored by asavonic).
[AArch64] Combine vector shift instructions in SelectionDAG
May 20 2021, 1:00 AM
asavonic closed D102333: [AArch64] Combine shift instructions in SelectionDAG.
May 20 2021, 1:00 AM · Restricted Project

May 19 2021

asavonic updated the diff for D102333: [AArch64] Combine shift instructions in SelectionDAG.
  • Applied CR comments.
May 19 2021, 10:20 AM · Restricted Project
asavonic added inline comments to D98895: [X86][Draft] Disable long double type for -mno-x87 option.
May 19 2021, 8:30 AM · Restricted Project

May 18 2021

asavonic requested review of D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
May 18 2021, 2:19 PM · Restricted Project
asavonic reopened D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

@SjoerdMeijer, can you please check if the new revision of the patch is OK?

May 18 2021, 2:17 PM · Restricted Project
asavonic added a comment to D98895: [X86][Draft] Disable long double type for -mno-x87 option.

ping

May 18 2021, 2:09 PM · Restricted Project
asavonic updated the diff for D102333: [AArch64] Combine shift instructions in SelectionDAG.
  • Used TLI.SimplifyDemandedBits for performShiftCombine.
  • Extended SimplifyDemandedBits to cover AArch64 VLSHR + VSHL.
May 18 2021, 6:51 AM · Restricted Project

May 14 2021

asavonic added a comment to D102333: [AArch64] Combine shift instructions in SelectionDAG.

Thanks a lot Dave! I'll follow your first suggestion, and if does not work, we can get back to the original patch.

May 14 2021, 8:28 AM · Restricted Project

May 12 2021

asavonic added a comment to D101156: [Clang] Support a user-defined __dso_handle.

What's the crash exactly/ Is IRGen just unhappy about processing the user definition when we've generated a declaration with a different type? Because we're already supposed to be being cautious about this.

May 12 2021, 2:14 PM · Restricted Project
asavonic requested review of D102333: [AArch64] Combine shift instructions in SelectionDAG.
May 12 2021, 8:54 AM · Restricted Project

May 5 2021

asavonic committed rG1ee50b473168: [AArch64] Fix scalar imm variants of SIMD shift left instructions (authored by asavonic).
[AArch64] Fix scalar imm variants of SIMD shift left instructions
May 5 2021, 6:29 AM
asavonic closed D101580: [AArch64] Fix scalar imm variants of SIMD shift left instructions.
May 5 2021, 6:29 AM · Restricted Project

May 4 2021

asavonic committed rGb451ecd86e13: [Clang][AArch64] Disable rounding of return values for AArch64 (authored by asavonic).
[Clang][AArch64] Disable rounding of return values for AArch64
May 4 2021, 10:29 AM
asavonic closed D100591: [Clang][AArch64] Disable rounding of return values for AArch64.
May 4 2021, 10:29 AM · Restricted Project

Apr 29 2021

asavonic requested review of D101580: [AArch64] Fix scalar imm variants of SIMD shift left instructions.
Apr 29 2021, 3:00 PM · Restricted Project

Apr 26 2021

asavonic added a comment to D98895: [X86][Draft] Disable long double type for -mno-x87 option.

The option was added in D19658 and D13979, but I'm not sure how it is supposed to work for SystemV ABI.
GCC emits an error if long double type is used with -mno-x87: "test.c:37:1: error: x87 register return with x87 disabled".

Apr 26 2021, 8:36 AM · Restricted Project
asavonic added reviewers for D98895: [X86][Draft] Disable long double type for -mno-x87 option: bruno, echristo, rsmith, nadav.
Apr 26 2021, 8:36 AM · Restricted Project
asavonic updated the diff for D100591: [Clang][AArch64] Disable rounding of return values for AArch64.

Keep rounding of return values for big-endian targets.

Apr 26 2021, 7:21 AM · Restricted Project
asavonic added a comment to D100591: [Clang][AArch64] Disable rounding of return values for AArch64.

On big-endian targets the rounding up to 64-bits (specified in the AAPCS) is significant; it means that structs get passed in the high bits of x0 rather than low. E.g. https://godbolt.org/z/6v36oexsW. I think this patch would break that.

Apr 26 2021, 7:21 AM · Restricted Project

Apr 23 2021

asavonic added a comment to D101156: [Clang] Support a user-defined __dso_handle.

John, can you please review this patch?
I originally wanted to add a diagnostic to prevent the crash in CG (PR49198), but the case seems easy enough to support.

Apr 23 2021, 7:37 AM · Restricted Project
asavonic added a reviewer for D101156: [Clang] Support a user-defined __dso_handle: rjmccall.
Apr 23 2021, 7:36 AM · Restricted Project
asavonic requested review of D101156: [Clang] Support a user-defined __dso_handle.
Apr 23 2021, 5:19 AM · Restricted Project

Apr 22 2021

asavonic added a comment to D100591: [Clang][AArch64] Disable rounding of return values for AArch64.

Ping.
Please let me know if the patch is acceptable for AArch64, or something else should be done to avoid overhead from rounding of return values.

Apr 22 2021, 2:51 AM · Restricted Project

Apr 15 2021

asavonic added a comment to D100591: [Clang][AArch64] Disable rounding of return values for AArch64.

I think the right thing to do here is to recognize generally that we're emitting a mandatory tail call, and so suppress *all* the normal transformations on the return value.

Apr 15 2021, 2:33 PM · Restricted Project
asavonic added inline comments to D100591: [Clang][AArch64] Disable rounding of return values for AArch64.
Apr 15 2021, 12:07 PM · Restricted Project
asavonic requested review of D100591: [Clang][AArch64] Disable rounding of return values for AArch64.
Apr 15 2021, 12:05 PM · Restricted Project

Apr 12 2021

asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

There were two issues with the patch, so I reverted it:

Apr 12 2021, 1:41 PM · Restricted Project
asavonic added a reverting change for rGcca9b5985c0c: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant: rGf037b07b5c2e: Revert "[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant".
Apr 12 2021, 6:30 AM
asavonic committed rGf037b07b5c2e: Revert "[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant" (authored by asavonic).
Revert "[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant"
Apr 12 2021, 6:30 AM
asavonic added a reverting change for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant: rGf037b07b5c2e: Revert "[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant".
Apr 12 2021, 6:30 AM · Restricted Project
asavonic committed rGcca9b5985c0c: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant (authored by asavonic).
[AArch64] Add Machine InstCombiner patterns for FMUL indexed variant
Apr 12 2021, 6:15 AM
asavonic closed D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Apr 12 2021, 6:15 AM · Restricted Project

Apr 11 2021

asavonic added a comment to D100225: [Clang][AArch64] Coerce integer return values through an undef vector.

So we can just remove this rounding from classifyReturnType?
Thanks a lot John! I will upload this change as a separate review.

Apr 11 2021, 1:05 PM · Restricted Project
asavonic added a comment to D100225: [Clang][AArch64] Coerce integer return values through an undef vector.

Why does the ABI "require" this to be returned as an i64 if some of the bits are undefined?

Apr 11 2021, 11:52 AM · Restricted Project
asavonic added reviewers for D100225: [Clang][AArch64] Coerce integer return values through an undef vector: rjmccall, dmgreen.
Apr 11 2021, 8:09 AM · Restricted Project
asavonic updated the summary of D100225: [Clang][AArch64] Coerce integer return values through an undef vector.
Apr 11 2021, 8:08 AM · Restricted Project
asavonic retitled D100227: [AArch64][InstCombine] Optimize coercion through an undef vector from [AArch64] Teach InstCombine to optimize coercion through an undef vector to [AArch64][InstCombine] Optimize coercion through an undef vector.
Apr 11 2021, 8:02 AM · Restricted Project

Apr 9 2021

asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Apr 9 2021, 2:26 PM · Restricted Project
asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

Added test cases for fp16 to the MIR test.

Apr 9 2021, 2:17 PM · Restricted Project
asavonic requested review of D100227: [AArch64][InstCombine] Optimize coercion through an undef vector.
Apr 9 2021, 1:16 PM · Restricted Project
asavonic requested review of D100225: [Clang][AArch64] Coerce integer return values through an undef vector.
Apr 9 2021, 12:59 PM · Restricted Project
asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Apr 9 2021, 7:26 AM · Restricted Project
asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
  • Removed extra assert
  • Removed arguments that can be queried from Root
  • Removed assignments to RC and Opc
  • Changed tests to ensure that basic blocks are not merged
  • Added fp16 cases to arm64-fma-combines.ll
Apr 9 2021, 7:21 AM · Restricted Project

Apr 8 2021

asavonic committed rGf08a2fc09e75: [MCA] Add tests for IPC on Cortex-A55 (authored by asavonic).
[MCA] Add tests for IPC on Cortex-A55
Apr 8 2021, 9:40 AM
asavonic closed D98174: [MCA] Add tests for IPC on Cortex-A55.
Apr 8 2021, 9:40 AM · Restricted Project

Apr 7 2021

asavonic added a comment to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

But the other thing I was just wondering, not that I mind these patterns here, but are we not expecting that the VDUP is sunk to its user? I think that's probably what I would expect, but don't know if that is a fair expectation.

Apr 7 2021, 1:46 PM · Restricted Project
asavonic updated the diff for D98174: [MCA] Add tests for IPC on Cortex-A55.

Enabled auto-generated checks for all tests except the XFAIL'ed ones.

Apr 7 2021, 11:11 AM · Restricted Project
asavonic added a comment to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

I've uploaded a separate patch for the FIXME issue: https://reviews.llvm.org/D100047
Let me know if anything should be fixed or improved for this one.

Apr 7 2021, 9:58 AM · Restricted Project
asavonic requested review of D100047: [AArch64] Handle processLogicalImmediate error in Machine InstCombine.
Apr 7 2021, 9:49 AM · Restricted Project

Mar 31 2021

asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Mar 31 2021, 1:22 PM · Restricted Project
asavonic added inline comments to D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Mar 31 2021, 11:38 AM · Restricted Project
asavonic updated the diff for D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.

Added test/CodeGen/AArch64/machine-combiner-fmul-dup.mir

Mar 31 2021, 11:34 AM · Restricted Project
asavonic requested review of D99662: [AArch64] Add Machine InstCombiner patterns for FMUL indexed variant.
Mar 31 2021, 7:35 AM · Restricted Project

Mar 26 2021

asavonic updated the diff for D98174: [MCA] Add tests for IPC on Cortex-A55.
  • Adjusted SDIV operands to match the average latency specified in the model.
  • Added FP tests.
  • Added a test for instructions with OOO write and retire.
Mar 26 2021, 8:08 AM · Restricted Project

Mar 25 2021

asavonic committed rGbba25a9cd827: [MCA] Support carry-over instructions for in-order processors (authored by asavonic).
[MCA] Support carry-over instructions for in-order processors
Mar 25 2021, 2:18 PM
asavonic closed D99339: [MCA] Support carry-over instructions for in-order processors.
Mar 25 2021, 2:17 PM · Restricted Project
asavonic added a comment to D99339: [MCA] Support carry-over instructions for in-order processors.

Thanks for the review Andrea!

Mar 25 2021, 12:55 PM · Restricted Project
asavonic updated the diff for D99339: [MCA] Support carry-over instructions for in-order processors.
  • Refactored code, added updateCarriedOver function
  • Used a different prefix for non-event debugging messages
Mar 25 2021, 12:52 PM · Restricted Project
asavonic requested review of D99339: [MCA] Support carry-over instructions for in-order processors.
Mar 25 2021, 7:19 AM · Restricted Project

Mar 24 2021

asavonic committed rG292da93d59a3: [MCA] Disable RCU for InOrderIssueStage (authored by asavonic).
[MCA] Disable RCU for InOrderIssueStage
Mar 24 2021, 3:56 AM
asavonic closed D98628: [MCA] Disable RCU for InOrderIssueStage.
Mar 24 2021, 3:56 AM · Restricted Project

Mar 23 2021

asavonic updated the diff for D98628: [MCA] Disable RCU for InOrderIssueStage.
  • Enabled negative readadvance tracking.
  • Reverted unnecessary changes in RetireStage.
Mar 23 2021, 12:43 PM · Restricted Project

Mar 22 2021

asavonic added inline comments to D98628: [MCA] Disable RCU for InOrderIssueStage.
Mar 22 2021, 8:50 AM · Restricted Project

Mar 19 2021

asavonic updated the diff for D98628: [MCA] Disable RCU for InOrderIssueStage.

Removed RetireStage from the in-order pipeline.
Retire and execute events are emitted in the same cycle.

Mar 19 2021, 11:08 AM · Restricted Project

Mar 18 2021

asavonic added a comment to D98895: [X86][Draft] Disable long double type for -mno-x87 option.

I'm not sure that this is the right approach, but I wanted to get feedback on
how the issue should be fixed. Currently, the compiler crashes on almost any
code with long double and -mno-x87 (excluding cases where CG does not properly disable x87):

Mar 18 2021, 2:01 PM · Restricted Project
asavonic requested review of D98895: [X86][Draft] Disable long double type for -mno-x87 option.
Mar 18 2021, 1:45 PM · Restricted Project
asavonic updated the diff for D98628: [MCA] Disable RCU for InOrderIssueStage.

RCU is now optional for RetireStage
RCU statistic is disabled for in-order processors.

Mar 18 2021, 12:19 PM · Restricted Project
asavonic added a comment to D98628: [MCA] Disable RCU for InOrderIssueStage.

There is nothing wrong with using a dummy RCU for the InOrderIssue stage.

The RCUtokenID is always stored in the instruction at dispatch time. You don't need any changes to pre-existing dispatch stage APIs (and listeners).

Mar 18 2021, 12:15 PM · Restricted Project
asavonic committed rGe6ce0db37847: [MCA] Ensure that writes occur in-order (authored by asavonic).
[MCA] Ensure that writes occur in-order
Mar 18 2021, 7:12 AM
asavonic closed D98604: [MCA] Ensure that writes occur in-order.
Mar 18 2021, 7:11 AM · Restricted Project

Mar 16 2021

asavonic updated the diff for D98604: [MCA] Ensure that writes occur in-order.

Store LastWriteBackCycle instead of recomputing it.

Mar 16 2021, 1:26 PM · Restricted Project
asavonic added a comment to D98604: [MCA] Ensure that writes occur in-order.

Is there a reason why you don't allow the bypassing of the write-back hazard check for all RetiresOOO instructions?

NOTE: normally this may not be a problem in practice, since RetiresOOO instructions (for what I have read) tend to have a high write latency. Still, it sounds a bit odd to me that we lift the check in one case, but not the other.
Mar 16 2021, 12:58 PM · Restricted Project