In D70401#4635875, @koute wrote:

I know that there are still open issues regarding the psABI, but considering how slow it's been going, couldn't we merge this in anyway and mark it as experimental and subject to change? Please?

The patch is simple enough to not become a maintenance burden, and GCC already has it even though the ABI's unfinished, and the RV32E target itself is most likely going to be used for standalone bare metal programs where the exact ABI shouldn't matter too much as long as it works.

I'm asking because I'd really like to have this merged so that I could use Rust to target RV32E/RV64E. Right now I have to maintain my own toolchain, which is painful; if this got merged (even in an experimental fashion, like GCC has) I could just get upstream Rust to support it out-of-box.

In D145539#4176831, @jrtc27 wrote:

In D145539#4176824, @luojia wrote:

In D145539#4176791, @jrtc27 wrote:

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Yes llvm-objcopy can do this and this is the current approach on EDK2 RISC-V. But for languages like Rust it will be more convenient if the compiler backend writes it out directly from build target configuration

And how are you going to do that without a full PE/COFF specification for RISC-V?

In D145539#4176791, @jrtc27 wrote:

I'm guessing this is so you can llvm-objcopy an ELF into a PE/COFF?.. Because without relocations being defined you can't do much else of use...

Applied suggestions from @jrtc27.

Update full-context diff.

Hello! Any further updates to this patch? It seems like all the inline comments have been resolved.

What's the current state of this patch? :)

Hello! I noticed that the pause hint instruction is merged into spec (https://github.com/riscv/riscv-isa-manual/pull/398) and got ratified (https://github.com/riscv/riscv-isa-manual/commit/7a58119dad5bd43e2171a26b56ef60f9591a1c9c).