[RISCV][MC] Add support for RV64E

[jobnoorman]

Summary

Implement MC support for the recently ratified RV64E base instruction set.

This patch does two things. First, it implements RV64E by trying to share as much code as possible with RV32E. This seems to make sense since the logic is exactly the same (restrict the available registers to x0-x15). However, it has some consequences that make me wonder if this is a good idea:

• the existing feature (FeatureRV32E) and predicate (IsRV32E) have been renamed to FeatureRVE and IsRVE. The acronym "RVE" might not be immediately clear to people;
• the RV128I base ISA doesn't currently define an equivalent RV128E variant. This is not a problem since LLVM doesn't implement it yet but we might have to reintroduce some checks this patch removes if it ever does.

Secondly, this patch introduces the recently proposed (but not yet ratified) lp64e ABI. It doesn't do anything besides setting the EF_RISCV_RVE ELF flag and some consistency checking. I'm not sure whether it's acceptable to introduce such an unstable ABI so I can remove this part or move it to a separate revision if that's preferred.

[jobnoorman]

Fix Clang driver tests.

[asb]

Thanks Job - your comment "Secondly, this patch introduces the recently proposed (but not yet ratified) lp64e ABI. " gave me some concern that this patch may have included too many codegen changes in addition to the minimal MC layer needs, but delving into it I see that's not what you meant. The situation is a bit subtle.

• ABI_LP64E is only used internally by LLVM and isn't directly exposed in the emitted ELF.
• The EF_RISCV_RVE ELF attribute is set by this patch, but that flag is already defined in the ratified psABI doc and specified as "This bit is set when the binary targets the E ABI." So I think is correct.
• EDIT: I'd originally worried about the stack alignment attribute, but further discussion and inspection of course confirms this attribute is only emitted to .s in the codegen path. RVE codegen isn't implemented yet, so the emission of this attribute won't happen - the codepath would probably be better off as an assert for now.
  • Relatedly, we don't seem to have any tests covering that attribute (i.e. I can emit ALIGN_16 for RV32E and ALIGN_4 for everything else and all our tests pass). It looks like fixing that would be a necessary step for this. (this comment still holds true - test coverage should be expanded here).

For anyone else following along and wondering how RVE escape the experimental extensions flag despite being only just ratified: RVE was one of the initial set of extensions that predated the whole ratification process, and at least some level of support shipped in GCC for quite some time.

(EDITED): I'd orriginally worried about the stack alignment question being a blocker, but upon fixing my understanding of the attribute emission that's no longer a concern (only affects the codegen path, which isn't implemented). So from my perspective, I think we'd be OK to integrate MC layer RV64E support (to the same level as RV32E) despite the lack of a finalised ABI. I'd welcome any other thoughts on this of course.

Other things this patch will eventually need are:

• Updates to RISCVUsage.rst
• Addition to the LLVM release notes llvm/docs/ReleaseNotes.rst (we're not always the best at this, but we try to add things as we go).

I'm wondering if @kito-cheng and @jrtc27 might be able to comment from the perspective of any GCC progress on RV64E support (Kito) and what's next for agreeing the RV64E ABI (both). Thanks in advance!

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

65

The TODO in the branch a few lines above should probably be copied here as well.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

49–50

Per the draft ABI this should be 8-byte alignment for RV64E.

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVFeatures.td

597

How about this?

def IsRVE : Predicate<"Subtarget->isRVE()">,
                        AssemblerPredicate<(all_of FeatureRVE)>;
def IsRV32E : Predicate<"Subtarget->is32RVE()">,
                        AssemblerPredicate<(all_of FeatureRVE, Feature32Bit)>;
def IsRV64E : Predicate<"Subtarget->is64RVE()">,
                       AssemblerPredicate<(all_of FeatureRVE, Feature64Bit)>;

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVFeatures.td

597

Oops, I mean Subtarget->isRV32E() and Subtarget->isRV64E().

[jrtc27]

llvm/lib/Target/RISCV/RISCVFeatures.td

597

Why do you need that? Just use IsRV32/64 and IsRVE as appropriate. We don't have IsRV32F, IsRV64D, IsRV32A, etc.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

78–81

They'll surely come together, just change the error message to RVE?

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVFeatures.td

597

I have no strong opinion on this, it's just a suggestion on one of the concerns in the patch description:

the existing feature (FeatureRV32E) and predicate (IsRV32E) have been renamed to FeatureRVE and IsRVE. The acronym "RVE" might not be immediately clear to people;

And we do have RV32E and RV64E in the spec, maybe we should rename them to RVE?

[jobnoorman]

Address reviewer comments:

• Sidestep stack alignment uncertainty by using report_fatal_error when codegen is reached for RVE;
• Unify codegen error reporting for RV32E and RV64E;
• Update RISCVUsage.rst and ReleaseNotes.rst

[jobnoorman]

Fix patch apply error. Sorry about the noise.

[jobnoorman]

Rebase.

[asb]

Everything that's in here looks good to me, and I think all the review comments have been addressed.

One thing I've just spotted is we still mark the E extension as 1.9, while the ratified version appears to be 2.0. I recently added a test for __riscv_i in riscv-target-features.c, but it's not possible to add the analogous one without more codegen support (the clang invocation errors out due to the ilp32e abi being selected). We're probably missing rv32e coverage here. Most extension versions are reflected in attributes.ll, but of course we'll error out due to codegen. EDIT: probably belongs in attribute-arch.s.

I personally think just bumping E from 1.9 to 2.0 shouldn't be a big dea., but it's perhaps something that might be best not to mingle in this patch - as noted before, RVE was defined long before the ratification process exists, so it is a bit of a special case. How posting a separate patch that moves E from 1.9 to 2.0 (which would be fine to apply even before adding RV64E), and ensuring we have some test coverage for that change? Thanks!

[jobnoorman]

Allow rv64e in arch strings (e.g., in the arch assembly attribute). Also add a test for this.

[jobnoorman]

Rebase

[kito-cheng]

@jobnoorman do you need some help to commit this and D144384? let me know if you need help, and I would suggest you could drop a mail to Chris to obtain write access https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access :)

[jobnoorman]

In D143570#4215828, @kito-cheng wrote:

@jobnoorman do you need some help to commit this and D144384? let me know if you need help, and I would suggest you could drop a mail to Chris to obtain write access https://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access :)

If you could commit these, that would be very helpful :) I was planning to ask for commit access after landing these.

Author details: Job Noorman <[e-mail]>

[kito-cheng]

@jobnoorman could you rebase again? I got conflict during apply this patch

[asb]

I expect you'll need to / want to update the C++ RISCVISAInfo unit tests as they were added after this patch was first proposed.

[jobnoorman]

Woops, sorry about that. Done!

[jobnoorman]

In D143570#4216040, @asb wrote:

I expect you'll need to / want to update the C++ RISCVISAInfo unit tests as they were added after this patch was first proposed.

My previous comment was about the rebase, I will look into this now.

[jobnoorman]

• Add RISCVISAInfo unit tests
• Update error message of RISCVISAInfo::parseArchString to reflect that we support RV64E now

[asb]

LGTM - thanks. I'll land this for you now since it already got a LGTM from Kito.

[jobnoorman]

Fix failing test, sorry about that!

[asb]

Apologies, the commited version of this patch missed the clang/test/Driver/riscv-arch.c change. rGe54cdd058e223bd62840e901b8b462c011d2fae5 committed to fix this.

clang/test/Driver/riscv-arch.c

 // RV64IMM: error: invalid arch name 'rv64imm'
 
 // RUN: %clang --target=riscv64-unknown-elf -march=RV64I -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64I-UPPER %s
 // RV64I-UPPER: error: invalid arch name 'RV64I'
 
 // Testing specific messages and unsupported extensions.
 
-// RUN: %clang --target=riscv64-unknown-elf -march=rv64e -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64E %s
-// RV64E: error: invalid arch name 'rv64e',
-// RV64E: standard user-level extension 'e' requires 'rv32'
-
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32imC -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-LOWER %s
 // RV32-LOWER: error: invalid arch name 'rv32imC',
 // RV32-LOWER: string must be lowercase
 
 // RUN: %clang --target=riscv32-unknown-elf -march=unknown -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-STR %s
 // RV32-STR: error: invalid arch name 'unknown',
 // RV32-STR: string must begin with rv32{i,e,g} or rv64{i,g}
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32q -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-LETTER %s
 // RV32-LETTER: error: invalid arch name 'rv32q',
 // RV32-LETTER: first letter should be 'e', 'i' or 'g'
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s
 // RV32-ORDER: error: invalid arch name 'rv32imcq',
 // RV32-ORDER: standard user-level extension not given in canonical order 'q'
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv64e -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-EER %s
-// RV64-EER: error: invalid arch name 'rv64e',
-// RV64-EER: standard user-level extension 'e' requires 'rv32'
-
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
 // RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
 // RV32-ZVE32F-ER: 'zve32f' requires 'f' or 'zfinx' extension to also be specified
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
 // RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',

clang/test/Driver/riscv-features.c

 
 // DEFAULT-LINUX: "-funwind-tables=2"
 // DEFAULT-LINUX-SAME: "-target-feature" "+m"
 // DEFAULT-LINUX-SAME: "-target-feature" "+a"
 // DEFAULT-LINUX-SAME: "-target-feature" "+f"
 // DEFAULT-LINUX-SAME: "-target-feature" "+d"
 // DEFAULT-LINUX-SAME: "-target-feature" "+c"
 
-// RUN: not %clang -cc1 -triple riscv64-unknown-elf -target-feature +e 2>&1 | FileCheck %s -check-prefix=RV64-WITH-E
-
-// RV64-WITH-E: error: invalid feature combination: standard user-level extension 'e' requires 'rv32'
-
 // RUN: not %clang -c --target=riscv64-linux-gnu -gsplit-dwarf %s 2>&1 | FileCheck %s --check-prefix=ERR-SPLIT-DWARF
 // RUN: not %clang -c --target=riscv64 -gsplit-dwarf=single %s 2>&1 | FileCheck %s --check-prefix=ERR-SPLIT-DWARF
 // RUN: %clang -### -c --target=riscv64 -mno-relax -g -gsplit-dwarf %s 2>&1 | FileCheck %s --check-prefix=SPLIT-DWARF
 
 // ERR-SPLIT-DWARF: error: -gsplit-dwarf{{.*}} is unsupported with RISC-V linker relaxation (-mrelax)
 // SPLIT-DWARF:     "-split-dwarf-file"

llvm/docs/RISCVUsage.rst

 
 The RISC-V target provides code generation for processors implementing
 supported variations of the RISC-V specification.  It lives in the
 ``llvm/lib/Target/RISCV`` directory.
 
 Base ISAs
 =========
 
-The specification defines four base instruction sets: RV32I, RV32E, RV64I,
-and RV128I. Currently, LLVM fully supports RV32I, and RV64I.  RV32E is
-supported by the assembly-based tools only.  RV128I is not supported.
+The specification defines five base instruction sets: RV32I, RV32E, RV64I,
+RV64E, and RV128I. Currently, LLVM fully supports RV32I, and RV64I.  RV32E and
+RV64E are supported by the assembly-based tools only.  RV128I is not supported.
 
 To specify the target triple:
 
   .. table:: RISC-V Architectures
 
      ============ ==============================================================
      Architecture Description
      ============ ==============================================================
      ``riscv32``   RISC-V with XLEN=32 (i.e. RV32I or RV32E)
-     ``riscv64``   RISC-V with XLEN=64 (i.e. RV64I)
+     ``riscv64``   RISC-V with XLEN=64 (i.e. RV64I or RV64E)
      ============ ==============================================================
 
 To select an E variant ISA (e.g. RV32E instead of RV32I), use the base
 architecture string (e.g. ``riscv32``) with the extension ``e``.
 
 .. _riscv-extensions:
 
 Extensions

llvm/docs/ReleaseNotes.rst

 * Added support for the vendor-defined XTHeadMemPair (two-GPR memory operations)
   extension disassembler/assembler.
 * Added support for the vendor-defined XTHeadMemIdx (indexed memory operations)
   extension disassembler/assembler.
 * Support for the now-ratified Zawrs extension is no longer experimental.
 * Adds support for the vendor-defined XTHeadCmo (cache management operations) extension.
 * Adds support for the vendor-defined XTHeadSync (multi-core synchronization instructions) extension.
 * Added support for the vendor-defined XTHeadFMemIdx (indexed memory operations for floating point) extension.
+* Assembler support for RV64E was added.
 
 Changes to the WebAssembly Backend
 ----------------------------------
 
 * ...
 
 Changes to the Windows Target
 -----------------------------

llvm/lib/Support/RISCVISAInfo.cpp

RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
   if (llvm::any_of(Arch, isupper)) {
     return createStringError(errc::invalid_argument,
                              "string must be lowercase");
   }
 
   bool HasRV64 = Arch.startswith("rv64");
   // ISA string must begin with rv32 or rv64.
   if (!(Arch.startswith("rv32") || HasRV64) || (Arch.size() < 5)) {
-    return createStringError(errc::invalid_argument,
-                             "string must begin with rv32{i,e,g} or rv64{i,g}");
+    return createStringError(
+        errc::invalid_argument,
+        "string must begin with rv32{i,e,g} or rv64{i,e,g}");
   }
 
   unsigned XLen = HasRV64 ? 64 : 32;
   std::unique_ptr<RISCVISAInfo> ISAInfo(new RISCVISAInfo(XLen));
 
   // The canonical order specified in ISA manual.
   // Ref: Table 22.1 in RISC-V User-Level ISA V2.2
   StringRef StdExts = AllStdExts;
   char Baseline = Arch[4];
 
   // First letter should be 'e', 'i' or 'g'.
   switch (Baseline) {
   default:
     return createStringError(errc::invalid_argument,
                              "first letter should be 'e', 'i' or 'g'");
-  case 'e': {
-    // Extension 'e' is not allowed in rv64.
-    if (HasRV64)
-      return createStringError(
-          errc::invalid_argument,
-          "standard user-level extension 'e' requires 'rv32'");
-    break;
-  }
+  case 'e':
   case 'i':
     break;
   case 'g':
     // g = imafd
     if (Arch.size() > 5 && isdigit(Arch[5]))
       return createStringError(errc::invalid_argument,
                                "version not supported for 'g'");
     StdExts = StdExts.drop_front(4);
if (!isSupportedExtension(Ext)) {
                                Desc.str().c_str(), Ext.str().c_str());
     }
   }
 
   return RISCVISAInfo::postProcessAndChecking(std::move(ISAInfo));
 }
 
 Error RISCVISAInfo::checkDependency() {
-  bool IsRv32 = XLen == 32;
-  bool HasE = Exts.count("e") != 0;
   bool HasD = Exts.count("d") != 0;
   bool HasF = Exts.count("f") != 0;
   bool HasZfinx = Exts.count("zfinx") != 0;
   bool HasZdinx = Exts.count("zdinx") != 0;
   bool HasVector = Exts.count("zve32x") != 0;
   bool HasZve32f = Exts.count("zve32f") != 0;
   bool HasZve64d = Exts.count("zve64d") != 0;
   bool HasZvl = MinVLen != 0;
 
-  if (HasE && !IsRv32)
-    return createStringError(
-        errc::invalid_argument,
-        "standard user-level extension 'e' requires 'rv32'");
-
   if (HasF && HasZfinx)
     return createStringError(errc::invalid_argument,
                              "'f' and 'zfinx' extensions are incompatible");
 
   if (HasZve32f && !HasF && !HasZfinx)
     return createStringError(
         errc::invalid_argument,
         "'zve32f' requires 'f' or 'zfinx' extension to also be specified");
if (XLen == 32) {
     if (hasExtension("d"))
       return "ilp32d";
     if (hasExtension("e"))
       return "ilp32e";
     return "ilp32";
   } else if (XLen == 64) {
     if (hasExtension("d"))
       return "lp64d";
+    if (hasExtension("e"))
+      return "lp64e";
     return "lp64";
   }
   llvm_unreachable("Invalid XLEN");
 }

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 class RISCVAsmParser : public MCTargetAsmParser {
   SmallVector<FeatureBitset, 4> FeatureBitStack;
 
   SmallVector<ParserOptionsSet, 4> ParserOptionsStack;
   ParserOptionsSet ParserOptions;
 
   SMLoc getLoc() const { return getParser().getTok().getLoc(); }
   bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
-  bool isRV32E() const { return getSTI().hasFeature(RISCV::FeatureRV32E); }
+  bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureRVE); }
 
   RISCVTargetStreamer &getTargetStreamer() {
     assert(getParser().getStreamer().getTargetStreamer() &&
            "do not have a target streamer");
     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
     return static_cast<RISCVTargetStreamer &>(TS);
   }
 
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   }
   }
 
   llvm_unreachable("Unknown match type detected!");
 }
 
 // Attempts to match Name as a register (either using the default name or
 // alternative ABI names), setting RegNo to the matching register. Upon
-// failure, returns true and sets RegNo to 0. If IsRV32E then registers
+// failure, returns true and sets RegNo to 0. If IsRVE then registers
 // x16-x31 will be rejected.
-static bool matchRegisterNameHelper(bool IsRV32E, MCRegister &RegNo,
+static bool matchRegisterNameHelper(bool IsRVE, MCRegister &RegNo,
                                     StringRef Name) {
   RegNo = MatchRegisterName(Name);
   // The 16-/32- and 64-bit FPRs have the same asm name. Check that the initial
   // match always matches the 64-bit variant, and not the 16/32-bit one.
   assert(!(RegNo >= RISCV::F0_H && RegNo <= RISCV::F31_H));
   assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F));
   // The default FPR register class is based on the tablegen enum ordering.
   static_assert(RISCV::F0_D < RISCV::F0_H, "FPR matching must be updated");
   static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated");
   if (RegNo == RISCV::NoRegister)
     RegNo = MatchRegisterAltName(Name);
-  if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31)
+  if (IsRVE && RegNo >= RISCV::X16 && RegNo <= RISCV::X31)
     RegNo = RISCV::NoRegister;
   return RegNo == RISCV::NoRegister;
 }
 
 bool RISCVAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
                                    SMLoc &EndLoc) {
   if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
     return Error(StartLoc, "invalid register name");
   return false;
 }
 
 OperandMatchResultTy RISCVAsmParser::tryParseRegister(MCRegister &RegNo,
                                                       SMLoc &StartLoc,
                                                       SMLoc &EndLoc) {
   const AsmToken &Tok = getParser().getTok();
   StartLoc = Tok.getLoc();
   EndLoc = Tok.getEndLoc();
   RegNo = 0;
   StringRef Name = getLexer().getTok().getIdentifier();
 
-  if (matchRegisterNameHelper(isRV32E(), (MCRegister &)RegNo, Name))
+  if (matchRegisterNameHelper(isRVE(), (MCRegister &)RegNo, Name))
     return MatchOperand_NoMatch;
 
   getParser().Lex(); // Eat identifier token.
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
                                                    bool AllowParens) {
OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
   switch (getLexer().getKind()) {
   default:
     if (HadParens)
       getLexer().UnLex(LParen);
     return MatchOperand_NoMatch;
   case AsmToken::Identifier:
     StringRef Name = getLexer().getTok().getIdentifier();
     MCRegister RegNo;
-    matchRegisterNameHelper(isRV32E(), RegNo, Name);
+    matchRegisterNameHelper(isRVE(), RegNo, Name);
 
     if (RegNo == RISCV::NoRegister) {
       if (HadParens)
         getLexer().UnLex(LParen);
       return MatchOperand_NoMatch;
     }
     if (HadParens)
       Operands.push_back(RISCVOperand::createToken("(", FirstS));
if (getLexer().isNot(AsmToken::Identifier))
     return MatchOperand_NoMatch;
 
   StringRef Name = getLexer().getTok().getIdentifier();
   if (!Name.consume_back(".t")) {
     Error(getLoc(), "expected '.t' suffix");
     return MatchOperand_ParseFail;
   }
   MCRegister RegNo;
-  matchRegisterNameHelper(isRV32E(), RegNo, Name);
+  matchRegisterNameHelper(isRVE(), RegNo, Name);
 
   if (RegNo == RISCV::NoRegister)
     return MatchOperand_NoMatch;
   if (RegNo != RISCV::V0)
     return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
   getLexer().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseGPRAsFPR(OperandVector &Operands) {
   if (getLexer().isNot(AsmToken::Identifier))
     return MatchOperand_NoMatch;
 
   StringRef Name = getLexer().getTok().getIdentifier();
   MCRegister RegNo;
-  matchRegisterNameHelper(isRV32E(), RegNo, Name);
+  matchRegisterNameHelper(isRVE(), RegNo, Name);
 
   if (RegNo == RISCV::NoRegister)
     return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
   getLexer().Lex();
   Operands.push_back(RISCVOperand::createReg(
       RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
                                          createRISCVDisassembler);
   TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
                                          createRISCVDisassembler);
 }
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder) {
-  bool IsRV32E = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRV32E);
+  bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
 
-  if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
+  if (RegNo >= 32 || (IsRVE && RegNo >= 16))
     return MCDisassembler::Fail;
 
   MCRegister Reg = RISCV::X0 + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 enum ABI {
   ABI_ILP32,
   ABI_ILP32F,
   ABI_ILP32D,
   ABI_ILP32E,
   ABI_LP64,
   ABI_LP64F,
   ABI_LP64D,
+  ABI_LP64E,
   ABI_Unknown
 };
 
 // Returns the target ABI, or else a StringError if the requested ABIName is
 // not supported for the given TT and FeatureBits combination.
 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
                      StringRef ABIName);
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

 #include "RISCVGenSearchableTables.inc"
 } // namespace RISCVInsnOpcode
 
 namespace RISCVABI {
 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
                      StringRef ABIName) {
   auto TargetABI = getTargetABI(ABIName);
   bool IsRV64 = TT.isArch64Bit();
-  bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
+  bool IsRVE = FeatureBits[RISCV::FeatureRVE];
 
   if (!ABIName.empty() && TargetABI == ABI_Unknown) {
     errs()
         << "'" << ABIName
         << "' is not a recognized ABI for this target (ignoring target-abi)\n";
   } else if (ABIName.startswith("ilp32") && IsRV64) {
     errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
               "target-abi)\n";
     TargetABI = ABI_Unknown;
   } else if (ABIName.startswith("lp64") && !IsRV64) {
     errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
               "target-abi)\n";
     TargetABI = ABI_Unknown;
-  } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
+  } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
+             TargetABI != ABI_Unknown) {
     // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
     errs()
         << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
     TargetABI = ABI_Unknown;
+  } else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
+             TargetABI != ABI_Unknown) {
+    // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
+    errs()
+        << "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
+    TargetABI = ABI_Unknown;
   }
 
   if (TargetABI != ABI_Unknown)
     return TargetABI;
 
   // If no explicit ABI is given, try to compute the default ABI.
   auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
   if (!ISAInfo)
     report_fatal_error(ISAInfo.takeError());
   return getTargetABI((*ISAInfo)->computeDefaultABI());
 }
 
 ABI getTargetABI(StringRef ABIName) {
   auto TargetABI = StringSwitch<ABI>(ABIName)
                        .Case("ilp32", ABI_ILP32)
                        .Case("ilp32f", ABI_ILP32F)
                        .Case("ilp32d", ABI_ILP32D)
                        .Case("ilp32e", ABI_ILP32E)
                        .Case("lp64", ABI_LP64)
                        .Case("lp64f", ABI_LP64F)
                        .Case("lp64d", ABI_LP64D)
+                       .Case("lp64e", ABI_LP64E)
                        .Default(ABI_Unknown);
   return TargetABI;
 }
 
 // To avoid the BP value clobbered by a function call, we need to choose a
 // callee saved register to save the value. RV32E only has X8 and X9 as callee
 // saved registers and X8 will be used as fp. So we choose X9 as bp.
 MCRegister getBPReg() { return RISCV::X9; }
 
 // Returns the register holding shadow call stack pointer.
 MCRegister getSCSPReg() { return RISCV::X18; }
 
 } // namespace RISCVABI
 
 namespace RISCVFeatures {
 
 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV64 target requires an RV64 CPU");
   if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
     report_fatal_error("RV32 target requires an RV32 CPU");
-  if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
-    report_fatal_error("RV32E can't be enabled for an RV64 target");
   if (FeatureBits[RISCV::Feature32Bit] &&
       FeatureBits[RISCV::Feature64Bit])
     report_fatal_error("RV32 and RV64 can't be combined");
 }
 
 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
   unsigned XLen = IsRV64 ? 64 : 32;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

void RISCVTargetELFStreamer::finish() {
   case RISCVABI::ABI_LP64F:
     EFlags |= ELF::EF_RISCV_FLOAT_ABI_SINGLE;
     break;
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:
     EFlags |= ELF::EF_RISCV_FLOAT_ABI_DOUBLE;
     break;
   case RISCVABI::ABI_ILP32E:
+  case RISCVABI::ABI_LP64E:
     EFlags |= ELF::EF_RISCV_RVE;
     break;
   case RISCVABI::ABI_Unknown:
     llvm_unreachable("Improperly initialised target ABI");
   }
 
   MCA.setELFHeaderEFlags(EFlags);
 }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
                                                unsigned IntValue,
                                                StringRef StringValue) {}
 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
   TargetABI = ABI;
 }
 
 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
-  if (STI.hasFeature(RISCV::FeatureRV32E))
-    emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
-  else
-    emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
+  if (STI.hasFeature(RISCV::FeatureRVE))
+    report_fatal_error("Codegen not yet implemented for RVE");
+
 
   auto ParseResult = RISCVFeatures::parseFeatureBits(
       STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
     report_fatal_error(ParseResult.takeError());
   } else {
     auto &ISAInfo = *ParseResult;
     emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());

llvm/lib/Target/RISCV/RISCVFeatures.td

def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                                          "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                                           "RV32I Base Instruction Set">;
 
 defvar RV32 = DefaultMode;
 def RV64           : HwMode<"+64bit", [IsRV64]>;
 
-def FeatureRV32E
-    : SubtargetFeature<"e", "IsRV32E", "true",
-                       "Implements RV32E (provides 16 rather than 32 GPRs)">;
-def IsRV32E : Predicate<"Subtarget->isRV32E()">,
-                        AssemblerPredicate<(all_of FeatureRV32E)>;
+def FeatureRVE
+    : SubtargetFeature<"e", "IsRVE", "true",
+                       "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
+def IsRVE : Predicate<"Subtarget->isRVE()">,
+                        AssemblerPredicate<(all_of FeatureRVE)>;
 
 def FeatureRelax
     : SubtargetFeature<"relax", "EnableLinkerRelax", "true",
                        "Enable Linker relaxation.">;
 
 foreach i = {1-31} in
   def FeatureReserveX#i :
       SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
                        "true", "Reserve X"#i>;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static cl::opt<int>
     FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden,
               cl::desc("Give the maximum number of instructions that we will "
                        "use for creating a floating-point immediate value"),
               cl::init(2));
 
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
-  if (Subtarget.isRV32E())
-    report_fatal_error("Codegen not yet implemented for RV32E");
+  if (Subtarget.isRVE())
+    report_fatal_error("Codegen not yet implemented for RVE");
 
   RISCVABI::ABI ABI = Subtarget.getTargetABI();
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
 
   if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
       !Subtarget.hasStdExtF()) {
     errs() << "Hard-float 'f' ABI can't be used for a target that "
                 "doesn't support the F instruction set extension (ignoring "
                           "target-abi)\n";

llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \
-; RUN:   | FileCheck -check-prefix=RV64E %s
-
-; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target

llvm/test/CodeGen/RISCV/rv32e.ll

-; RUN: not --crash llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s
-
-; CHECK: LLVM ERROR: Codegen not yet implemented for RV32E
-
-define void @nothing() nounwind {
-  ret void
-}

llvm/test/CodeGen/RISCV/rve.ll

+; RUN: not --crash llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s
+; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: Codegen not yet implemented for RVE
+
+define void @nothing() nounwind {
+  ret void
+}

llvm/test/MC/RISCV/attribute-arch.s

 ## Arch string without version.
 
 # RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
-# RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -filetype=asm \
+# RUN:     | FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
 
 .attribute arch, "rv32i"
 # CHECK: attribute      5, "rv32i2p0"
 
 .attribute arch, "rv32i2"
 # CHECK: attribute      5, "rv32i2p0"
 
 .attribute arch, "rv32i2p0"
 # CHECK: attribute      5, "rv32i2p0"
 
 .attribute arch, "rv32e"
 # CHECK: attribute      5, "rv32e2p0"
 
+.attribute arch, "rv64e"
+# CHECK-RV64: attribute      5, "rv64e2p0"
+
 .attribute arch, "rv32i2_m2"
 # CHECK: attribute      5, "rv32i2p0_m2p0"
 
 .attribute arch, "rv32i2_ma"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0"
 
 .attribute arch, "rv32g"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0"

llvm/test/MC/RISCV/elf-flags.s

 # RUN: llvm-mc -triple=riscv32 -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVI %s
 # RUN: llvm-mc -triple=riscv64 -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVI %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+c -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVIC %s
 # RUN: llvm-mc -triple=riscv64 -mattr=+c -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-RVIC %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e -filetype=obj < %s \
 # RUN:   | llvm-readobj --file-headers - \
 # RUN:   | FileCheck -check-prefix=CHECK-RVE %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+e -filetype=obj < %s \
+# RUN:   | llvm-readobj --file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-RVE %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
 # RUN: llvm-mc -triple=riscv64 -mattr=+experimental-ztso -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck -check-prefixes=CHECK-TSO %s
 
 # CHECK-RVI:       Flags [ (0x0)
 # CHECK-RVI-NEXT:  ]
 
 # CHECK-RVIC:       Flags [ (0x1)
 # CHECK-RVIC-NEXT:    EF_RISCV_RVC (0x1)

llvm/test/MC/RISCV/invalid-attribute.s

 ## Negative tests:
 ##  - Feed integer value to string type attribute.
 ##  - Feed string value to integer type attribute.
 ##  - Invalid arch string.
 
 # RUN: not llvm-mc %s -triple=riscv32 -filetype=asm 2>&1 | FileCheck %s
 # RUN: not llvm-mc %s -triple=riscv64 -filetype=asm 2>&1 | FileCheck %s
 
 .attribute arch, "foo"
-# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,g}
+# CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g} or rv64{i,e,g}
 
 .attribute arch, "rv32i2p0_y2p0"
 # CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p0_y2p0', invalid standard user-level extension 'y'
 
 .attribute stack_align, "16"
 # CHECK: [[@LINE-1]]:25: error: expected numeric constant
 
 .attribute unaligned_access, "0"

llvm/test/MC/RISCV/mattr-invalid-combination.s

-# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
-# RUN:   | FileCheck %s -check-prefix=RV64E
-
-# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target

llvm/test/MC/RISCV/rv32e-invalid.s

 # RUN: not llvm-mc -triple riscv32 -mattr=+e < %s 2>&1 | FileCheck %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \
 # RUN:     | llvm-objdump --mattr=+e -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefix=CHECK-DIS %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \
+# RUN:     | llvm-objdump --mattr=+e -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefix=CHECK-DIS %s
 
 # Perform a simple check that registers x16-x31 (and the equivalent ABI names)
-# are rejected for RV32E, when both assembling and disassembling.
+# are rejected for RV32E/RV64E, when both assembling and disassembling.
 
 
 # CHECK-DIS: 37 18 00 00 <unknown>
 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction
 lui x16, 1
 # CHECK-DIS: b7 28 00 00 <unknown>
 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction
 lui x17, 2

llvm/test/MC/RISCV/rv32e-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
 # RUN:     | llvm-objdump -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+e -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+e < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
 
 # This file provides a basic test for RV32E, checking that the expected
 # set of registers and instructions are accepted.
 
 # CHECK-ASM-AND-OBJ: lui zero, 1
 lui x0, 1
 # CHECK-ASM-AND-OBJ: auipc ra, 2
 auipc x1, 2

llvm/test/MC/RISCV/rv64e-valid.s

+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+e -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+e < %s \
+# RUN:     | llvm-objdump -M no-aliases -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
+
+# This file provides a basic test for RV64E, checking that the expected
+# set of registers and instructions are accepted. It only tests instructions
+# that are not valid in RV32E.
+
+# CHECK-ASM-AND-OBJ: ld a4, 25(a5)
+ld x14, 25(x15)
+# CHECK-ASM-AND-OBJ: sd a2, 36(a3)
+sd a2, 36(a3)
+
+# CHECK-ASM-AND-OBJ: addiw a4, a5, 37
+addiw a4, a5, 37
+# CHECK-ASM-AND-OBJ: slliw t1, t1, 31
+slliw t1, t1, 31
+# CHECK-ASM-AND-OBJ: srliw a0, a4, 0
+srliw a0, a4, 0
+# CHECK-ASM-AND-OBJ: sraiw a1, sp, 15
+sraiw a1, sp, 15
+# CHECK-ASM-AND-OBJ: slliw t0, t1, 13
+slliw t0, t1, 13
+
+# CHECK-ASM-AND-OBJ: addw ra, zero, zero
+addw ra, zero, zero
+# CHECK-ASM-AND-OBJ: subw t0, t2, t1
+subw t0, t2, t1
+# CHECK-ASM-AND-OBJ: sllw a5, a4, a3
+sllw a5, a4, a3
+# CHECK-ASM-AND-OBJ: srlw a0, s0, t0
+srlw a0, s0, t0
+# CHECK-ASM-AND-OBJ: sraw t0, a3, zero
+sraw t0, a3, zero

llvm/test/MC/RISCV/target-abi-invalid.s

 # RUN: llvm-mc -triple=riscv32 -mattr=+d -target-abi lp64d < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32IFD-LP64D %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64 < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32E-LP64 %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EF-LP64F %s
 # RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EFD-LP64D %s
+# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64e %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV32E-LP64E %s
 
 # RV32I-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32IF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32IFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32E-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32EF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 # RV32EFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
+# RV32E-LP64E: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
 
 # RUN: llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32I-ILP32F %s
 # RUN: llvm-mc -triple=riscv64 -target-abi lp64f < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV64I-LP64F %s
 
 # RV32I-ILP32F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)
 # RV64I-LP64F: Hard-float 'f' ABI can't be used for a target that doesn't support the F instruction set extension (ignoring target-abi)

 # RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32d < %s 2>&1 \
 # RUN:   | FileCheck -check-prefix=RV32EFD-ILP32D %s
 
 # RV32E-ILP32: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EF-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EFD-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 # RV32EFD-ILP32D: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
 
+# RUN: llvm-mc -triple=riscv64 -mattr=+e -target-abi lp64 < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64EF-LP64F %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64EF-LP64F %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64EFD-LP64F %s
+# RUN: llvm-mc -triple=riscv64 -mattr=+e,+d -target-abi lp64d < %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=RV64EFD-LP64D %s
+
+# RV64E-LP64: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
+# RV64EF-LP64F: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
+# RV64EFD-LP64F: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
+# RV64EFD-LP64D: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
+
 nop

llvm/test/MC/RISCV/target-abi-valid.s

 # RUN: llvm-mc -triple=riscv64 -mattr=+d -target-abi lp64d -filetype=obj < %s \
 # RUN:   | llvm-readobj --file-headers - \
 # RUN:   | FileCheck -check-prefix=CHECK-FLOAT-DOUBLE %s
 
 # RUN: llvm-mc -triple=riscv32 -target-abi ilp32e -filetype=obj < %s \
 # RUN:   | llvm-readobj --file-headers - \
 # RUN:   | FileCheck -check-prefix=CHECK-RVE %s
 
+# RUN: llvm-mc -triple=riscv64 -target-abi lp64e -filetype=obj < %s \
+# RUN:   | llvm-readobj --file-headers - \
+# RUN:   | FileCheck -check-prefix=CHECK-RVE %s
+
 # CHECK-NONE:               Flags [ (0x0)
 # CHECK-NONE-NEXT:          ]
 
 # CHECK-FLOAT-SINGLE:       Flags [ (0x2)
 # CHECK-FLOAT-SINGLE-NEXT:    EF_RISCV_FLOAT_ABI_SINGLE (0x2)
 # CHECK-FLOAT-SINGLE-NEXT:  ]
 
 # CHECK-FLOAT-DOUBLE:       Flags [ (0x4)
 # CHECK-FLOAT-DOUBLE-NEXT:    EF_RISCV_FLOAT_ABI_DOUBLE (0x4)
 # CHECK-FLOAT-DOUBLE-NEXT:  ]
 
 # CHECK-RVE:                Flags [ (0x8)
 # CHECK-RVE-NEXT:             EF_RISCV_RVE (0x8)
 # CHECK-RVE-NEXT:           ]
 
 nop

llvm/unittests/Support/RISCVISAInfoTest.cpp

for (StringRef Input : {"RV32", "rV64", "rv32i2P0", "rv64i2p0_A2p0"}) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
               "string must be lowercase");
   }
 }
 
 TEST(ParseArchString, RejectsInvalidBaseISA) {
   for (StringRef Input : {"rv32", "rv64", "rv65i"}) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "string must begin with rv32{i,e,g} or rv64{i,g}");
+              "string must begin with rv32{i,e,g} or rv64{i,e,g}");
   }
   for (StringRef Input : {"rv32j", "rv64k", "rv32_i"}) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
               "first letter should be 'e', 'i' or 'g'");
   }
 }
 
 TEST(ParseArchString, RejectsUnsupportedBaseISA) {
-  EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64e", true).takeError()),
-            "standard user-level extension 'e' requires 'rv32'");
   for (StringRef Input : {"rv128i", "rv128g"}) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "string must begin with rv32{i,e,g} or rv64{i,g}");
+              "string must begin with rv32{i,e,g} or rv64{i,e,g}");
   }
 }
 
 TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
   auto MaybeRV32I = RISCVISAInfo::parseArchString("rv32i", true);
   ASSERT_THAT_EXPECTED(MaybeRV32I, Succeeded());
   RISCVISAInfo &InfoRV32I = **MaybeRV32I;
   RISCVISAInfo::OrderedExtensionMap ExtsRV32I = InfoRV32I.getExtensions();
TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
   ASSERT_THAT_EXPECTED(MaybeRV64I, Succeeded());
   RISCVISAInfo &InfoRV64I = **MaybeRV64I;
   RISCVISAInfo::OrderedExtensionMap ExtsRV64I = InfoRV64I.getExtensions();
   EXPECT_EQ(ExtsRV64I.size(), 1UL);
   EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVExtensionInfo{2, 0}));
   EXPECT_EQ(InfoRV64I.getXLen(), 64U);
   EXPECT_EQ(InfoRV64I.getFLen(), 0U);
 
+  auto MaybeRV64E = RISCVISAInfo::parseArchString("rv64e", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64E, Succeeded());
+  RISCVISAInfo &InfoRV64E = **MaybeRV64E;
+  RISCVISAInfo::OrderedExtensionMap ExtsRV64E = InfoRV64E.getExtensions();
+  EXPECT_EQ(ExtsRV64E.size(), 1UL);
+  EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVExtensionInfo{2, 0}));
+  EXPECT_EQ(InfoRV64E.getXLen(), 64U);
+  EXPECT_EQ(InfoRV64E.getFLen(), 0U);
+
   auto MaybeRV64G = RISCVISAInfo::parseArchString("rv64g", true);
   ASSERT_THAT_EXPECTED(MaybeRV64G, Succeeded());
   RISCVISAInfo &InfoRV64G = **MaybeRV64G;
   RISCVISAInfo::OrderedExtensionMap ExtsRV64G = InfoRV64G.getExtensions();
   EXPECT_EQ(ExtsRV64G.size(), 5UL);
   EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVExtensionInfo{2, 0}));
   EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVExtensionInfo{2, 0}));
   EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVExtensionInfo{2, 0}));