[TargetSupport] Move TargetParser API in a separate LLVM component.

[fpetrogalli]

Summary

[TargetSupport] Generate the defs for RISCV CPUs using llvm-tblgen.

[fpetrogalli]

Abandoning because I accidentally squashed the two commits together when using Arcanist. I'll follow up with two new revisions.

clang/lib/Analysis/CMakeLists.txt

add_clang_library(clangAnalysis
   ThreadSafetyTIL.cpp
   UninitializedValues.cpp
 
   LINK_LIBS
   clangAST
   clangASTMatchers
   clangBasic
   clangLex
+  clangRewrite
+  clangToolingCore
   
   DEPENDS
   omp_gen
   )
 
 add_subdirectory(plugins)
 add_subdirectory(FlowSensitive)

clang/lib/Basic/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   Support
+  TargetSupport
   )
 
 find_first_existing_vc_file("${LLVM_MAIN_SRC_DIR}" llvm_vc)
 find_first_existing_vc_file("${CLANG_SOURCE_DIR}" clang_vc)
 
 # The VC revision include that we want to generate.
 set(version_inc "${CMAKE_CURRENT_BINARY_DIR}/VCSVersion.inc")
 
add_clang_library(clangBasic
   DEPENDS
   omp_gen
   )
 
 target_link_libraries(clangBasic
   PRIVATE
   ${LLVM_ATOMIC_LIB}
 )
+
+target_include_directories(clangBasic PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

clang/lib/Basic/TargetID.cpp

 //===--- TargetID.cpp - Utilities for parsing target ID -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "clang/Basic/TargetID.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Triple.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 #include <map>
 
 namespace clang {
 
 static llvm::SmallVector<llvm::StringRef, 4>
 getAllPossibleAMDGPUTargetIDFeatures(const llvm::Triple &T,
                                      llvm::StringRef Proc) {

clang/lib/Basic/TargetInfo.cpp

 #include "clang/Basic/AddressSpaces.h"
 #include "clang/Basic/CharInfo.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/DiagnosticFrontend.h"
 #include "clang/Basic/LangOptions.h"
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include <cstdlib>
 using namespace clang;
 
 static const LangASMap DefaultAddrSpaceMap = {0};
 
 // TargetInfo Constructor.
 TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) {
   // Set defaults.  Defaults are set for a 32-bit RISC platform, like PPC or

clang/lib/Basic/Targets/AArch64.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_AARCH64_H
 #define LLVM_CLANG_LIB_BASIC_TARGETS_AARCH64_H
 
 #include "OSTargets.h"
 #include "clang/Basic/TargetBuiltins.h"
 #include "llvm/Support/AArch64TargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 namespace clang {
 namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   virtual void setDataLayout() = 0;
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
   static const char *const GCCRegNames[];

clang/lib/Basic/Targets/AMDGPU.h

 #define LLVM_CLANG_LIB_BASIC_TARGETS_AMDGPU_H
 
 #include "clang/Basic/TargetID.h"
 #include "clang/Basic/TargetInfo.h"
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/ADT/StringSet.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Support/Compiler.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 namespace clang {
 namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
 
   static const Builtin::Info BuiltinInfo[];
   static const char *const GCCRegNames[];

clang/lib/Basic/Targets/ARM.h

 #define LLVM_CLANG_LIB_BASIC_TARGETS_ARM_H
 
 #include "OSTargets.h"
 #include "clang/Basic/TargetInfo.h"
 #include "clang/Basic/TargetOptions.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ARMTargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 namespace clang {
 namespace targets {
 
 class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
   // Possible FPU choices.
   enum FPUMode {
     VFP2FPU = (1 << 0),

clang/lib/Basic/Targets/LoongArch.cpp

 //===--- LoongArch.cpp - Implement LoongArch target feature support -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements LoongArch TargetInfo objects.
 //
 //===----------------------------------------------------------------------===//
 
 #include "LoongArch.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/MacroBuilder.h"
 #include "clang/Basic/TargetBuiltins.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace clang;
 using namespace clang::targets;
 
 ArrayRef<const char *> LoongArchTargetInfo::getGCCRegNames() const {
   static const char *const GCCRegNames[] = {
       // General purpose registers.

clang/lib/Basic/Targets/M68k.cpp

 
 #include "M68k.h"
 #include "clang/Basic/Builtins.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/TargetBuiltins.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include <cstdint>
 #include <cstring>
 #include <limits>
 
 namespace clang {
 namespace targets {
 
 M68kTargetInfo::M68kTargetInfo(const llvm::Triple &Triple,

clang/lib/Basic/Targets/RISCV.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCV.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/MacroBuilder.h"
 #include "clang/Basic/TargetBuiltins.h"
 #include "llvm/ADT/StringSwitch.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace clang;
 using namespace clang::targets;
 
 ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
   static const char *const GCCRegNames[] = {
       // Integer registers

clang/lib/Driver/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   BinaryFormat
   MC
   Object
   Option
   ProfileData
   Support
+  TargetSupport
   WindowsDriver
   )
 
 if(WIN32)
   # MSVCToolChain.cpp uses version.dll.
   set(system_libs version)
 endif()
 
add_clang_library(clangDriver
   XRayArgs.cpp
 
   DEPENDS
   ClangDriverOptions
 
   LINK_LIBS
   clangBasic
   ${system_libs}
-  )
+
+target_include_directories(clangDriver PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

clang/lib/Driver/SanitizerArgs.cpp

 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "clang/Driver/ToolChain.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Support/AArch64TargetParser.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/SpecialCaseList.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h"
 #include <memory>
 
 using namespace clang;
 using namespace clang::driver;
 using namespace llvm::opt;
 

clang/lib/Driver/ToolChain.cpp

 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Option/Arg.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Option/OptTable.h"
 #include "llvm/Option/Option.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/VersionTuple.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include <cassert>
 #include <cstddef>
 #include <cstring>
 #include <string>
 
 using namespace clang;

clang/lib/Driver/ToolChains/AMDGPU.h

 
 #include "Gnu.h"
 #include "ROCm.h"
 #include "clang/Basic/TargetID.h"
 #include "clang/Driver/Options.h"
 #include "clang/Driver/Tool.h"
 #include "clang/Driver/ToolChain.h"
 #include "llvm/ADT/SmallString.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 #include <map>
 
 namespace clang {
 namespace driver {
 
 namespace tools {
 namespace amdgpu {

clang/lib/Driver/ToolChains/Arch/AArch64.cpp

 //===--- AArch64.cpp - AArch64 (not ARM) Helpers for Tools ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64.h"
 #include "../CommonArgs.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/AArch64TargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/Host.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 
 /// \returns true if the given triple can determine the default CPU type even

clang/lib/Driver/ToolChains/Arch/ARM.h

 //===--- ARM.h - ARM-specific (not AArch64) Tool Helpers --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ARCH_ARM_H
 #define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_ARCH_ARM_H
 
 #include "clang/Driver/ToolChain.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Option/Option.h"
 #include "llvm/Support/ARMTargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include <string>
 #include <vector>
 
 namespace clang {
 namespace driver {
 namespace tools {
 namespace arm {
 

clang/lib/Driver/ToolChains/Arch/ARM.cpp

 //===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/ARMTargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/Host.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 
 // Get SubArch (vN).

clang/lib/Driver/ToolChains/Arch/CSKY.cpp

 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/CSKYTargetParser.h"
 #include "llvm/Support/Host.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 
 llvm::Optional<llvm::StringRef>

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

 #include "clang/Basic/CharInfo.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/RISCVISAInfo.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 
 // Returns false if an error is diagnosed.

clang/lib/Driver/ToolChains/Clang.cpp

 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Compression.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/YAMLParser.h"
 #include <cctype>
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 

clang/lib/Driver/ToolChains/CommonArgs.cpp

 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
 #include "llvm/Support/Program.h"
 #include "llvm/Support/ScopedPrinter.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/Threading.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/Support/YAMLParser.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;

clang/lib/Driver/ToolChains/Cuda.cpp

 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
 #include "llvm/Support/Program.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include <system_error>
 
 using namespace clang::driver;
 using namespace clang::driver::toolchains;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;

clang/lib/Driver/ToolChains/Darwin.cpp

 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "clang/Driver/SanitizerArgs.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/ProfileData/InstrProf.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/ScopedPrinter.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/Threading.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include <cstdlib> // ::getenv
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
 using namespace clang::driver::toolchains;
 using namespace clang;

clang/lib/Driver/ToolChains/Gnu.cpp

 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "clang/Driver/Tool.h"
 #include "clang/Driver/ToolChain.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Option/ArgList.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/Path.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include <system_error>
 
 using namespace clang::driver;
 using namespace clang::driver::toolchains;
 using namespace clang;
 using namespace llvm::opt;
 

clang/lib/Driver/ToolChains/HIPAMD.cpp

 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/InputInfo.h"
 #include "clang/Driver/Options.h"
 #include "clang/Driver/SanitizerArgs.h"
 #include "llvm/Support/Alignment.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace clang::driver;
 using namespace clang::driver::toolchains;
 using namespace clang::driver::tools;
 using namespace clang;
 using namespace llvm::opt;
 
 #if defined(_WIN32) || defined(_WIN64)

clang/unittests/Basic/CMakeLists.txt

 set(LLVM_LINK_COMPONENTS
   Support
+  TargetSupport
   )
 
 add_clang_unittest(BasicTests
   CharInfoTest.cpp
   DarwinSDKInfoTest.cpp
   DiagnosticTest.cpp
   FileEntryTest.cpp
   FileManagerTest.cpp

llvm/include/llvm/Support/RISCVTargetParser.def

-#ifndef PROC
-#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)
-#endif
-
-PROC(INVALID, {"invalid"}, FK_INVALID, {""})
-PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
-PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
-PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
-PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
-PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
-PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
-PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
-PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
-PROC(SIFIVE_E34, {"sifive-e34"}, FK_NONE, {"rv32imafc"})
-PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
-PROC(SIFIVE_S21, {"sifive-s21"}, FK_64BIT, {"rv64imac"})
-PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
-PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
-PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
-PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
-PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
-
-#undef PROC
-
-#ifndef TUNE_PROC
-#define TUNE_PROC(ENUM, NAME)
-#endif
-
-TUNE_PROC(GENERIC, "generic")
-TUNE_PROC(ROCKET, "rocket")
-TUNE_PROC(SIFIVE_7, "sifive-7-series")
-
-#undef TUNE_PROC

llvm/include/llvm/TargetSupport/TargetParser.h

 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a target parser to recognise hardware features such as
 // FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_SUPPORT_TARGETPARSER_H
-#define LLVM_SUPPORT_TARGETPARSER_H
+#ifndef LLVM_TARGETSUPPORT_TARGETPARSER_H
+#define LLVM_TARGETSUPPORT_TARGETPARSER_H
 
 #include "llvm/ADT/StringRef.h"
 #include <cstdint>
 // FIXME: vector is used because that's what clang uses for subtarget feature
 // lists, but SmallVector would probably be better
 #include <vector>
 
 namespace llvm {

 namespace RISCV {
 
 // We use 64 bits as the known part in the scalable vector types.
 static constexpr unsigned RVVBitsPerBlock = 64;
 
 enum CPUKind : unsigned {
 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
 #define TUNE_PROC(ENUM, NAME) CK_##ENUM,
-#include "RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
 };
 
 enum FeatureKind : unsigned {
   FK_INVALID = 0,
   FK_NONE = 1,
   FK_64BIT = 1 << 2,
 };
 
struct ParsedBranchProtection {
   StringRef Key;
   bool BranchTargetEnforcement;
 };
 
 bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP,
                            StringRef &Err);
 
 } // namespace ARM
-
 } // namespace llvm
 
-#endif
+#endif // LLVM_TARGETSUPPORT_TARGETPARSER_H

llvm/include/llvm/module.modulemap

module Support {
     // Exclude these; they are fundamentally non-modular.
     exclude header "Support/PluginLoader.h"
     exclude header "Support/Solaris/sys/regset.h"
 
     // These are intended for textual inclusion.
     textual header "Support/AArch64TargetParser.def"
     textual header "Support/ARMTargetParser.def"
     textual header "Support/CSKYTargetParser.def"
-    textual header "Support/RISCVTargetParser.def"
     textual header "Support/TargetOpcodes.def"
     textual header "Support/X86TargetParser.def"
   }
 
   // This part of the module is usable from both C and C++ code.
   module ConvertUTF {
     header "Support/ConvertUTF.h"
     export *

llvm/lib/CMakeLists.txt

 add_subdirectory(ObjectYAML)
 add_subdirectory(Option)
 add_subdirectory(Remarks)
 add_subdirectory(Debuginfod)
 add_subdirectory(DebugInfo)
 add_subdirectory(DWP)
 add_subdirectory(ExecutionEngine)
 add_subdirectory(Target)
+add_subdirectory(TargetSupport)
 add_subdirectory(AsmParser)
 add_subdirectory(LineEditor)
 add_subdirectory(ProfileData)
 add_subdirectory(Passes)
 add_subdirectory(TextAPI)
 add_subdirectory(ToolDrivers)
 add_subdirectory(XRay)
 if (LLVM_INCLUDE_TESTS)

llvm/lib/Support/CMakeLists.txt

add_llvm_component_library(LLVMSupport
   StringExtras.cpp
   StringMap.cpp
   StringSaver.cpp
   StringRef.cpp
   SuffixTree.cpp
   SymbolRemappingReader.cpp
   SystemUtils.cpp
   TarWriter.cpp
-  TargetParser.cpp
   ThreadPool.cpp
   TimeProfiler.cpp
   Timer.cpp
   ToolOutputFile.cpp
   TrigramIndex.cpp
   Triple.cpp
   Twine.cpp
   TypeSize.cpp

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

 #include "GISel/AArch64LegalizerInfo.h"
 #include "GISel/AArch64RegisterBankInfo.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/Support/AArch64TargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "aarch64-subtarget"
 
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_TARGET_DESC
 #include "AArch64GenSubtargetInfo.inc"

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SMLoc.h"
 #include "llvm/Support/AArch64TargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <cctype>
 #include <cstdint>
 #include <cstdio>
 #include <string>
 #include <tuple>
 #include <utility>

llvm/lib/Target/AArch64/AsmParser/CMakeLists.txt

add_llvm_component_library(LLVMAArch64AsmParser
   MC
   MCParser
   Support
 
   ADD_TO_COMPONENT
   AArch64
   )
 
+target_include_directories(LLVMAArch64AsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/AArch64/CMakeLists.txt

add_llvm_target(AArch64CodeGen
   AArch64
 )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)
+
+target_include_directories(LLVMAArch64CodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/AMDHSAKernelDescriptor.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
 // This should get the default rounding mode from the kernel. We just set the
 // default here, but this could change if the OpenCL rounding mode pragmas are

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/AMDGPUMetadata.h"
 #include "llvm/Support/AMDHSAKernelDescriptor.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 using namespace llvm::amdhsa;
 
 namespace {
 
 class AMDGPUAsmParser;

llvm/lib/Target/AMDGPU/AsmParser/CMakeLists.txt

 add_llvm_component_library(LLVMAMDGPUAsmParser
   AMDGPUAsmParser.cpp
 
   LINK_COMPONENTS
   MC
   MCParser
   AMDGPUDesc
   AMDGPUInfo
   AMDGPUUtils
   Support
+  TargetSupport
 
   ADD_TO_COMPONENT
   AMDGPU
   )
 
 add_dependencies(LLVMAMDGPUAsmParser LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUAsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/AMDGPU/CMakeLists.txt

add_llvm_target(AMDGPUCodeGen
   SelectionDAG
   Support
   Target
   TransformUtils
   Vectorize
   GlobalISel
   BinaryFormat
   MIRParser
+  TargetSupport
 
   ADD_TO_COMPONENT
   AMDGPU
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(MCA)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)
+
+target_include_directories(LLVMAMDGPUCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

 //===----------------------------------------------------------------------===//
 
 #include "GCNHazardRecognizer.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIMachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 
 namespace {
 
 struct MFMAPaddingRatioParser : public cl::parser<unsigned> {
   MFMAPaddingRatioParser(cl::Option &O) : cl::parser<unsigned>(O) {}
 

llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h

 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H
 #define LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MCA/CustomBehaviour.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 namespace llvm {
 namespace mca {
 
 class AMDGPUInstrPostProcess : public InstrPostProcess {
   void processWaitCnt(std::unique_ptr<Instruction> &Inst, const MCInst &MCI);
 
 public:

llvm/lib/Target/AMDGPU/MCA/CMakeLists.txt

 add_llvm_component_library(LLVMAMDGPUTargetMCA
   AMDGPUCustomBehaviour.cpp
 
   LINK_COMPONENTS
   MC
   MCParser
   AMDGPUDesc
   AMDGPUInfo
   AMDGPUUtils
   Support
   MCA
+  TargetSupport
 
   ADD_TO_COMPONENT
   AMDGPU
   )
 
 add_dependencies(LLVMAMDGPUTargetMCA LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUTargetMCA PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/EndianStream.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
 namespace {
 
 class AMDGPUAsmBackend : public MCAsmBackend {
 public:

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

 #include "Utils/AMDGPUAsmUtils.h"
 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
 static cl::opt<bool> Keep16BitSuffixes(
   "amdgpu-keep-16-bit-reg-suffixes",
   cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
   cl::init(false),

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/AMDGPUMetadata.h"
 #include "llvm/Support/AMDHSAKernelDescriptor.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
 //===----------------------------------------------------------------------===//
 // AMDGPUTargetStreamer
 //===----------------------------------------------------------------------===//
 

llvm/lib/Target/AMDGPU/MCTargetDesc/CMakeLists.txt

add_llvm_component_library(LLVMAMDGPUDesc
 
   LINK_COMPONENTS
   Core
   MC
   AMDGPUInfo
   AMDGPUUtils
   Support
   BinaryFormat
+  TargetSupport
 
   ADD_TO_COMPONENT
   AMDGPU
 )
 
 add_dependencies(LLVMAMDGPUDesc LLVMAMDGPUUtils)
+
+target_include_directories(LLVMAMDGPUDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/ADT/Sequence.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachinePostDominators.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/DebugCounter.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "si-insert-waitcnts"
 
 DEBUG_COUNTER(ForceExpCounter, DEBUG_TYPE"-forceexp",
               "Force emit s_waitcnt expcnt(0) instrs");
 DEBUG_COUNTER(ForceLgkmCounter, DEBUG_TYPE"-forcelgkm",
               "Force emit s_waitcnt lgkmcnt(0) instrs");

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

 #include "AMDGPUMachineModuleInfo.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "llvm/ADT/BitmaskEnum.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/Support/AtomicOrdering.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
 #define DEBUG_TYPE "si-memory-legalizer"
 #define PASS_NAME "SI Memory Legalizer"
 
 static cl::opt<bool> AmdgcnSkipCacheInvalidations(

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsR600.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/AMDHSAKernelDescriptor.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 #define GET_INSTRINFO_NAMED_OPS
 #define GET_INSTRMAP_INFO
 #include "AMDGPUGenInstrInfo.inc"
 
 static llvm::cl::opt<unsigned>
     AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden,
                             llvm::cl::desc("AMDHSA Code Object Version"),

llvm/lib/Target/AMDGPU/Utils/CMakeLists.txt

 add_llvm_component_library(LLVMAMDGPUUtils
   AMDGPUAsmUtils.cpp
   AMDGPUBaseInfo.cpp
   AMDGPUMemoryUtils.cpp
   AMDGPUPALMetadata.cpp
   AMDKernelCodeTUtils.cpp
 
   LINK_COMPONENTS
   Analysis
   Core
   MC
   BinaryFormat
   Support
+  TargetSupport
 
   ADD_TO_COMPONENT
   AMDGPU
   )
+
+target_include_directories(LLVMAMDGPUUtils PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/ARM/ARMAsmPrinter.cpp

 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)

llvm/lib/Target/ARM/ARMSubtarget.cpp

 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ARMTargetParser.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "arm-subtarget"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR

llvm/lib/Target/ARM/ARMTargetMachine.cpp

 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/CodeGen.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/CFGuard.h"
 #include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/Scalar.h"
 #include <cassert>
 #include <memory>
 #include <string>

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/ARMEHABI.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SMLoc.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 #include <iterator>
 #include <limits>
 #include <memory>

llvm/lib/Target/ARM/AsmParser/CMakeLists.txt

 add_llvm_component_library(LLVMARMAsmParser
   ARMAsmParser.cpp
 
   LINK_COMPONENTS
   ARMDesc
   ARMInfo
   MC
   MCParser
   Support
   ARMUtils
 
   ADD_TO_COMPONENT
   ARM
   )
+
+target_include_directories(LLVMARMAsmParser PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/ARM/CMakeLists.txt

add_llvm_target(ARMCodeGen
   ARM
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)
+
+target_include_directories(LLVMARMCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/MC/MCAsmLayout.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/EndianStream.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
 namespace {
 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   ARMELFObjectWriter(uint8_t OSABI)
       : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,

llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCSymbolELF.h"
 #include "llvm/MC/SectionKind.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/ARMEHABI.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cassert>
 #include <climits>
 #include <cstddef>
 #include <cstdint>
 #include <string>
 

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_MC_DESC
 #include "ARMGenRegisterInfo.inc"
 
 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
                                   std::string &Info) {

llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp

 #include "MCTargetDesc/ARMMCTargetDesc.h"
 #include "llvm/MC/ConstantPools.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ARMBuildAttributes.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 using namespace llvm;
 
 //
 // ARMTargetStreamer Implemenation
 //
 
 ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)

llvm/lib/Target/ARM/MCTargetDesc/CMakeLists.txt

add_llvm_component_library(LLVMARMDesc
   MC
   MCDisassembler
   Support
   BinaryFormat
 
   ADD_TO_COMPONENT
   ARM
   )
+
+target_include_directories(LLVMARMDesc PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/RISCV/CMakeLists.txt

 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
 add_llvm_target(RISCVCodeGen
   RISCVAsmPrinter.cpp
   RISCVCallLowering.cpp
   RISCVCodeGenPrepare.cpp
   RISCVMakeCompressible.cpp
add_llvm_target(RISCVCodeGen
   ADD_TO_COMPONENT
   RISCV
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
+
+#target_include_directories(RISCVCodeGen PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt

add_llvm_component_library(LLVMRISCVDesc
   RISCVMatInt.cpp
   RISCVTargetStreamer.cpp
   RISCVELFStreamer.cpp
 
   LINK_COMPONENTS
   MC
   RISCVInfo
   Support
+  MCDisassembler
+  TargetSupport
+  BinaryFormat
   
   ADD_TO_COMPONENT
   RISCV
 )

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVBaseInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/RISCVISAInfo.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 
 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
 
 namespace RISCVSysReg {
 #define GET_SysRegsList_IMPL

llvm/lib/Target/RISCV/RISCV.td

 include "RISCVRegisterBanks.td"
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
+class RISCVProcessorModelPROC<string enum, string enum_features, string default_march> {
+  string Enum = enum;
+  string EnumFeatures = enum_features;
+  string DefaultMarch = default_march;
+}
+
+class RISCVProcessorModelTUNE_PROC<string enum> {
+  string Enum = enum;
+}
+
+def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>, RISCVProcessorModelPROC<"GENERIC_RV32", "FK_NONE", "">;
+def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>, RISCVProcessorModelPROC<"GENERIC_RV64", "FK_64BIT", "">;
 // Support generic for compatibility with other targets. The triple will be used
 // to change to the appropriate rv32/rv64 version.
 def : ProcessorModel<"generic", NoSchedModel, []>;
 
-def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>;
-def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
-def : ProcessorModel<"rocket", RocketModel, []>;
+def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>, RISCVProcessorModelPROC<"ROCKET_RV32", "FK_NONE", "">;
+def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>, RISCVProcessorModelPROC<"ROCKET_RV64", "FK_64BIT", "">;
+def : ProcessorModel<"rocket", RocketModel, []>, RISCVProcessorModelTUNE_PROC<"ROCKET">;
 
 def : ProcessorModel<"sifive-7-series", SiFive7Model, [],
-                     [TuneSiFive7]>;
+                     [TuneSiFive7]>, RISCVProcessorModelTUNE_PROC<"SIFIVE_7">;
 
 def : ProcessorModel<"sifive-e20", RocketModel, [Feature32Bit,
                                                  FeatureStdExtM,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E20", "FK_NONE", "rv32imc">;
 
 def : ProcessorModel<"sifive-e21", RocketModel, [Feature32Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E21", "FK_NONE", "rv32imac">;
 
 def : ProcessorModel<"sifive-e24", RocketModel, [Feature32Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtF,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E24", "FK_NONE", "rv32imafc">;
 
 def : ProcessorModel<"sifive-e31", RocketModel, [Feature32Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E31", "FK_NONE", "rv32imac">;
 
 def : ProcessorModel<"sifive-e34", RocketModel, [Feature32Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtF,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_E34", "FK_NONE", "rv32imafc">;
 
 def : ProcessorModel<"sifive-e76", SiFive7Model, [Feature32Bit,
                                                   FeatureStdExtM,
                                                   FeatureStdExtA,
                                                   FeatureStdExtF,
                                                   FeatureStdExtC],
-                     [TuneSiFive7]>;
+                     [TuneSiFive7]>, RISCVProcessorModelPROC<"SIFIVE_E76", "FK_NONE", "rv32imafc">;
 
 def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_S21", "FK_64BIT", "rv64imac">;
 
 def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_S51", "FK_64BIT", "rv64imac">;
 
 def : ProcessorModel<"sifive-s54", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtF,
                                                  FeatureStdExtD,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_S54", "FK_64BIT", "rv64gc">;
 
 def : ProcessorModel<"sifive-s76", SiFive7Model, [Feature64Bit,
                                                   FeatureStdExtM,
                                                   FeatureStdExtA,
                                                   FeatureStdExtF,
                                                   FeatureStdExtD,
                                                   FeatureStdExtC],
-                     [TuneSiFive7]>;
+                     [TuneSiFive7]>, RISCVProcessorModelPROC<"SIFIVE_S76", "FK_64BIT", "rv64gc">;
 
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtF,
                                                  FeatureStdExtD,
-                                                 FeatureStdExtC]>;
+                                                 FeatureStdExtC]>, RISCVProcessorModelPROC<"SIFIVE_U54", "FK_64BIT", "rv64gc">;
 
 def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
                                                   FeatureStdExtM,
                                                   FeatureStdExtA,
                                                   FeatureStdExtF,
                                                   FeatureStdExtD,
                                                   FeatureStdExtC],
-                     [TuneSiFive7]>;
+                     [TuneSiFive7]>, RISCVProcessorModelPROC<"SIFIVE_U74", "FK_64BIT", "rv64gc">;
 
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
 }

llvm/lib/Target/RISCV/RISCVISelLowering.h

 
 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
 
 #include "RISCV.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 
 namespace llvm {
 class RISCVSubtarget;
 struct RISCVRegisterInfo;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_FLAG,

llvm/lib/Target/X86/MCA/X86CustomBehaviour.h

 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_X86_MCA_X86CUSTOMBEHAVIOUR_H
 #define LLVM_LIB_TARGET_X86_MCA_X86CUSTOMBEHAVIOUR_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MCA/CustomBehaviour.h"
-#include "llvm/Support/TargetParser.h"
 
 namespace llvm {
 namespace mca {
 
 class X86InstrPostProcess : public InstrPostProcess {
   /// Called within X86InstrPostProcess to specify certain instructions
   /// as load and store barriers.
   void setMemBarriers(std::unique_ptr<Instruction> &Inst, const MCInst &MCI);

llvm/lib/TargetSupport/CMakeLists.txt

+
+set(LLVM_TARGET_DEFINITIONS ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
+
+tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${CMAKE_SOURCE_DIR}/lib/Target/RISCV/)
+
+add_public_tablegen_target(RISCVTargetSupportTableGen)
+
+add_llvm_component_library(LLVMTargetSupport
+  TargetParser.cpp
+  LINK_COMPONENTS
+  Support
+)
+
+target_include_directories(LLVMTargetSupport PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/lib/TargetSupport/TargetParser.cpp

 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a target parser to recognise hardware features such as
 // FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 
 using namespace llvm;
 using namespace AMDGPU;
 
 namespace {
struct CPUInfo {
   unsigned Features;
   StringLiteral DefaultMarch;
   bool is64Bit() const { return (Features & FK_64BIT); }
 };
 
 constexpr CPUInfo RISCVCPUInfo[] = {
 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)                              \
   {NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
-#include "llvm/Support/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
 };
 
 bool checkCPUKind(CPUKind Kind, bool IsRV64) {
   if (Kind == CK_INVALID)
     return false;
   return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
 }
 
 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
   if (Kind == CK_INVALID)
     return false;
 #define TUNE_PROC(ENUM, NAME) if (Kind == CK_##ENUM) return true;
-#include "llvm/Support/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
   return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
 }
 
 CPUKind parseCPUKind(StringRef CPU) {
   return llvm::StringSwitch<CPUKind>(CPU)
 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
-#include "llvm/Support/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
 }
 
 CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
   return llvm::StringSwitch<CPUKind>(TuneCPU)
 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
 #define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
-#include "llvm/Support/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
       .Default(CK_INVALID);
 }
 
 StringRef getMArchFromMcpu(StringRef CPU) {
   CPUKind Kind = parseCPUKind(CPU);
   return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
 }
 
 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
   for (const auto &C : RISCVCPUInfo) {
     if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
       Values.emplace_back(C.Name);
   }
 }
 
 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
   for (const auto &C : RISCVCPUInfo) {
     if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
       Values.emplace_back(C.Name);
   }
 #define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
-#include "llvm/Support/RISCVTargetParser.def"
+#include "RISCVTargetParserDef.inc"
 }
 
 // Get all features except standard extension feature
 bool getCPUFeaturesExceptStdExt(CPUKind Kind,
                                 std::vector<StringRef> &Features) {
   unsigned CPUFeatures = RISCVCPUInfo[static_cast<unsigned>(Kind)].Features;
 
   if (CPUFeatures == FK_INVALID)

llvm/unittests/CMakeLists.txt

 add_subdirectory(ObjectYAML)
 add_subdirectory(Option)
 add_subdirectory(Remarks)
 add_subdirectory(Passes)
 add_subdirectory(ProfileData)
 add_subdirectory(Support)
 add_subdirectory(TableGen)
 add_subdirectory(Target)
+add_subdirectory(TargetSupport)
 add_subdirectory(Testing)
 add_subdirectory(TextAPI)
 add_subdirectory(Transforms)
 add_subdirectory(XRay)
 add_subdirectory(tools)

llvm/unittests/Support/CMakeLists.txt

add_llvm_unittest(SupportTests
   ScopedPrinterTest.cpp
   SHA256.cpp
   SourceMgrTest.cpp
   SpecialCaseListTest.cpp
   SuffixTreeTest.cpp
   SwapByteOrderTest.cpp
   SymbolRemappingReaderTest.cpp
   TarWriterTest.cpp
-  TargetParserTest.cpp
   TaskQueueTest.cpp
   ThreadLocalTest.cpp
   ThreadPool.cpp
   Threading.cpp
   TimerTest.cpp
   TimeProfilerTest.cpp
   ToolOutputFileTest.cpp
   TypeNameTest.cpp

 target_link_libraries(SupportTests PRIVATE LLVMTestingSupport ${LLVM_PTHREAD_LIB})
 
 if(NOT LLVM_INTEGRATED_CRT_ALLOC)
   # The test doesn't pass when using a custom allocator, PR47881.
   add_subdirectory(DynamicLibrary)
 endif()
 
 add_subdirectory(CommandLineInit)
+
+target_include_directories(SupportTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/unittests/Support/CSKYTargetParserTest.cpp

 //===-------- CSKYTargetParser.cpp - CSKY Target Parser -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/CSKYTargetParser.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/CSKYAttributes.h"
 #include "llvm/Support/FormatVariadic.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "gtest/gtest.h"
 #include <string>
 
 using namespace llvm;
 
 namespace {
 
 std::string FormatExtensionFlags(uint64_t Flags) {

llvm/unittests/TargetSupport/CMakeLists.txt

+set(LLVM_LINK_COMPONENTS
+  TargetSupport
+  )
+
+add_llvm_unittest(TargetSupportTests
+  TargetParserTest.cpp
+  )
+
+target_link_libraries(TargetSupportTests PRIVATE LLVMTestingSupport)
+
+target_include_directories(TargetSupportTests PRIVATE ${LLVM_LIBRARY_DIR}/TargetSupport/)

llvm/unittests/TargetSupport/TargetParserTest.cpp

 //===----------- TargetParser.cpp - Target Parser -------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/AArch64TargetParser.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/FormatVariadic.h"
-#include "llvm/Support/TargetParser.h"
+#include "llvm/TargetSupport/TargetParser.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
 #include <string>
 
 using namespace llvm;
 
 namespace {
 const char *ARMArch[] = {

llvm/utils/TableGen/CMakeLists.txt

add_tablegen(llvm-tblgen LLVM
   X86DisassemblerTables.cpp
   X86EVEX2VEXTablesEmitter.cpp
   X86FoldTablesEmitter.cpp
   X86MnemonicTables.cpp
   X86ModRMFilters.cpp
   X86RecognizableInstr.cpp
   WebAssemblyDisassemblerEmitter.cpp
   CTagsEmitter.cpp
+  RISCVTargetDefEmitter.cpp
   )
 target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel)
 set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")

llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

+//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This tablegen backend emits an assembly printer for the current target.
+// Note that this is currently fairly skeletal, but will grow over time.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/TableGen/Record.h"
+
+namespace llvm {
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
+  const auto &Map = RK.getDefs();
+
+  OS << "#ifndef PROC\n"
+     << "#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)\n"
+     << "#endif\n\n";
+
+  OS << "PROC(INVALID, {\"invalid\"}, FK_INVALID, {\"\"})\n";
+  // Iterate on all definition records.
+  for (auto &Def : Map) {
+    const auto &Record = Def.second;
+    if (Record->isSubClassOf("RISCVProcessorModelPROC"))
+      OS << "PROC(" << Record->getValueAsString("Enum") << ", "
+         << "{\"" << Record->getValueAsString("Name") << "\"}, "
+         << Record->getValueAsString("EnumFeatures") << ", "
+         << "{\"" << Record->getValueAsString("DefaultMarch") << "\"})\n";
+  }
+  OS << "\n#undef PROC\n";
+  OS << "\n";
+  OS << "#ifndef TUNE_PROC\n"
+     << "#define TUNE_PROC(ENUM, NAME)\n"
+     << "#endif\n\n";
+  OS << "TUNE_PROC(GENERIC, \"generic\")\n";
+  for (auto &Def : Map) {
+    const auto &Record = Def.second;
+    if (Record->isSubClassOf("RISCVProcessorModelTUNE_PROC"))
+      OS << "TUNE_PROC(" << Record->getValueAsString("Enum") << ", "
+         << "\"" << Record->getValueAsString("Name") << "\")\n";
+  }
+
+  OS << "\n#undef TUNE_PROC\n";
+}
+} // namespace llvm

llvm/utils/TableGen/TableGen.cpp

enum ActionType {
   GenX86FoldTables,
   GenX86MnemonicTables,
   GenRegisterBank,
   GenExegesis,
   GenAutomata,
   GenDirectivesEnumDecl,
   GenDirectivesEnumImpl,
   GenDXILOperation,
+  GenRISCVTargetDef,
 };
 
 namespace llvm {
 cl::opt<bool> EmitLongStrLiterals(
     "long-string-literals",
     cl::desc("when emitting large string tables, prefer string literals over "
              "comma-separated char literals. This can be a readability and "
              "compile-time performance win, but upsets some compilers"),
cl::values(
         clEnumValN(GenExegesis, "gen-exegesis",
                    "Generate llvm-exegesis tables"),
         clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"),
         clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl",
                    "Generate directive related declaration code (header file)"),
         clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
                    "Generate directive related implementation code"),
         clEnumValN(GenDXILOperation, "gen-dxil-operation",
-                   "Generate DXIL operation information")));
-
+                   "Generate DXIL operation information"),
+        clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
+                   "Generate the list of CPU for RISCV")));
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
                            cl::cat(PrintEnumsCat));
 
 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   switch (Action) {
   case PrintRecords:
case GenDirectivesEnumDecl:
     EmitDirectivesDecl(Records, OS);
     break;
   case GenDirectivesEnumImpl:
     EmitDirectivesImpl(Records, OS);
     break;
   case GenDXILOperation:
     EmitDXILOperation(Records, OS);
     break;
+  case GenRISCVTargetDef:
+    EmitRISCVTargetDef(Records, OS);
+    break;
   }
 
   return false;
 }
 }
 
 int main(int argc, char **argv) {
   InitLLVM X(argc, argv);

llvm/utils/TableGen/TableGenBackends.h

 void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitX86MnemonicTables(RecordKeeper &RK, raw_ostream &OS);
 void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);
 void EmitExegesis(RecordKeeper &RK, raw_ostream &OS);
 void EmitAutomata(RecordKeeper &RK, raw_ostream &OS);
 void EmitDirectivesDecl(RecordKeeper &RK, raw_ostream &OS);
 void EmitDirectivesImpl(RecordKeeper &RK, raw_ostream &OS);
 void EmitDXILOperation(RecordKeeper &RK, raw_ostream &OS);
-
+void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS);
 } // End llvm namespace
 
 #endif