nhaehnle (Nicolai Hähnle)
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User Since
Oct 9 2015, 4:06 AM (144 w, 6 d)

Recent Activity

Mon, Jun 25

nhaehnle updated the diff for D48431: AMDGPU: Force skip over s_sendmsg and exp instructions.

Factor out SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty

Mon, Jun 25, 3:45 AM
nhaehnle added inline comments to D47702: DAG: ComputeNumSignBits from load range metadata.
Mon, Jun 25, 12:50 AM
nhaehnle added inline comments to D47702: DAG: ComputeNumSignBits from load range metadata.
Mon, Jun 25, 12:49 AM
nhaehnle added a comment to D48431: AMDGPU: Force skip over s_sendmsg and exp instructions.

We really need to invert how this pass works

Mon, Jun 25, 12:21 AM

Thu, Jun 21

nhaehnle created D48431: AMDGPU: Force skip over s_sendmsg and exp instructions.
Thu, Jun 21, 7:14 AM

Jun 19 2018

nhaehnle updated the diff for D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.

Rebased.

Jun 19 2018, 2:22 AM
nhaehnle updated the diff for D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.

Rebased.

Jun 19 2018, 2:21 AM
nhaehnle updated the diff for D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Rebased.

Jun 19 2018, 2:21 AM
nhaehnle updated the diff for D48014: AMDGPU: Use generic tables instead of SearchableTable.

Rebased.

Jun 19 2018, 2:20 AM
nhaehnle added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 19 2018, 12:17 AM
nhaehnle updated the diff for D48013: TableGen/SearchableTables: Support more generic enums and tables.

Preserve the case in preprocessor guards for GenericEnum and GenericTable.

Jun 19 2018, 12:15 AM

Jun 18 2018

nhaehnle added a comment to D48013: TableGen/SearchableTables: Support more generic enums and tables.

Ping. Does this look alright?

Jun 18 2018, 2:38 AM

Jun 16 2018

nhaehnle added inline comments to D47909: Utilize new SDNode flag functionality to expand current support for fadd.
Jun 16 2018, 1:42 AM

Jun 15 2018

nhaehnle added a comment to D46756: [AMDGPU] Reworked SIFixWWMLiveness.

I've had some time to let this sink in now.

Jun 15 2018, 5:50 AM
nhaehnle accepted D48065: DAG: Fix creating concat_vectors with illegal type.

LGTM

Jun 15 2018, 4:25 AM
nhaehnle accepted D48198: AMDGPU/GlobalISel: Default to using TableGen'd instruction selector.

LGTM

Jun 15 2018, 3:45 AM
nhaehnle added inline comments to D47909: Utilize new SDNode flag functionality to expand current support for fadd.
Jun 15 2018, 3:41 AM
nhaehnle accepted D47918: Utilize new SDNode flag functionality to expand current support for fma.

We do have tests for those in AMDGPU, with -enable-unsafe-fp-math. We don't have systematic tests with the new contract/reassoc bits. At least the Mesa frontend doesn't generate those anyway at the moment.

Jun 15 2018, 3:23 AM
nhaehnle added a comment to D47383: [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor.

Thanks. I feel like some of this could perhaps be improved with a computeKnownBits if there is a 64-bit uniform base and a 32-bit non-uniform offset, but that doesn't have to be part of this change.

Jun 15 2018, 3:09 AM
nhaehnle accepted D47700: DivergenceAnalysis: added debug output.

I guess it would be nice to have something like opt's -analyze output in an llc flow as well, but I don't think we do, so I think this is fine.

Jun 15 2018, 2:48 AM
nhaehnle accepted D47980: [InstCombine] Fold (x << y) >> y -> x & (-1 >> y).
Jun 15 2018, 2:42 AM

Jun 14 2018

nhaehnle added a dependent revision for D48167: AMDGPU: Remove old-style image intrinsics: D48168: AMDGPU: Remove redundant MIMG instruction variants.
Jun 14 2018, 6:25 AM
nhaehnle added a dependency for D48168: AMDGPU: Remove redundant MIMG instruction variants: D48167: AMDGPU: Remove old-style image intrinsics.
Jun 14 2018, 6:25 AM
nhaehnle created D48168: AMDGPU: Remove redundant MIMG instruction variants.
Jun 14 2018, 6:24 AM
nhaehnle added a dependency for D48167: AMDGPU: Remove old-style image intrinsics: D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.
Jun 14 2018, 6:23 AM
nhaehnle added a dependent revision for D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded: D48167: AMDGPU: Remove old-style image intrinsics.
Jun 14 2018, 6:23 AM
nhaehnle created D48167: AMDGPU: Remove old-style image intrinsics.
Jun 14 2018, 6:22 AM
nhaehnle added dependencies for D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded: D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering, D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 14 2018, 6:22 AM
nhaehnle added a dependent revision for D48013: TableGen/SearchableTables: Support more generic enums and tables: D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.
Jun 14 2018, 6:22 AM
nhaehnle added a dependent revision for D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering: D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.
Jun 14 2018, 6:22 AM
nhaehnle created D48165: InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded.
Jun 14 2018, 6:18 AM
nhaehnle added inline comments to D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.
Jun 14 2018, 5:39 AM
nhaehnle updated the diff for D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.

Address review comments

Jun 14 2018, 5:36 AM
nhaehnle added a comment to D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Probably good to mention that this patch relies on https://reviews.llvm.org/D48013

Jun 14 2018, 4:53 AM
nhaehnle added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 14 2018, 4:50 AM
nhaehnle updated the diff for D48013: TableGen/SearchableTables: Support more generic enums and tables.
  • Address review comments
  • Fix formatting
  • Fix IsContiguous optimization for non-primary search indices
Jun 14 2018, 4:50 AM
nhaehnle added a comment to D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.

I'm assuming that I can submit this as-is soon. I'm holding off for now so that I can submit all MIMG-related changes in this stack at once.

Jun 14 2018, 4:37 AM
nhaehnle updated the diff for D47431: TableGen: Allow foreach in multiclass to depend on template args.

Address review comments. Going to submit later today.

Jun 14 2018, 4:34 AM
nhaehnle added inline comments to D47431: TableGen: Allow foreach in multiclass to depend on template args.
Jun 14 2018, 4:33 AM

Jun 11 2018

nhaehnle added a comment to D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Sorry for the lack of context.

Jun 11 2018, 7:52 AM
nhaehnle added a dependency for D48018: AMDGPU: Convert test cases to the dimension-aware intrinsics: D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.
Jun 11 2018, 5:51 AM
nhaehnle added a dependent revision for D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering: D48018: AMDGPU: Convert test cases to the dimension-aware intrinsics.
Jun 11 2018, 5:51 AM
nhaehnle created D48018: AMDGPU: Convert test cases to the dimension-aware intrinsics.
Jun 11 2018, 5:51 AM
nhaehnle added a dependency for D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering: D48016: AMDGPU: Refactor MIMG instruction TableGen using generic tables.
Jun 11 2018, 5:50 AM
nhaehnle added a dependent revision for D48016: AMDGPU: Refactor MIMG instruction TableGen using generic tables: D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.
Jun 11 2018, 5:50 AM
nhaehnle created D48017: AMDGPU: Select MIMG instructions manually in SITargetLowering.
Jun 11 2018, 5:50 AM
nhaehnle added a dependent revision for D48014: AMDGPU: Use generic tables instead of SearchableTable: D48016: AMDGPU: Refactor MIMG instruction TableGen using generic tables.
Jun 11 2018, 5:49 AM
nhaehnle created D48016: AMDGPU: Refactor MIMG instruction TableGen using generic tables.
Jun 11 2018, 5:49 AM
nhaehnle added a dependency for D48016: AMDGPU: Refactor MIMG instruction TableGen using generic tables: D48014: AMDGPU: Use generic tables instead of SearchableTable.
Jun 11 2018, 5:49 AM
nhaehnle added a dependency for D48015: ARM,AArch64: Use generic tables instead of SearchableTable: D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 5:49 AM
nhaehnle added a dependent revision for D48013: TableGen/SearchableTables: Support more generic enums and tables: D48015: ARM,AArch64: Use generic tables instead of SearchableTable.
Jun 11 2018, 5:49 AM
nhaehnle created D48015: ARM,AArch64: Use generic tables instead of SearchableTable.
Jun 11 2018, 5:49 AM
nhaehnle added a dependent revision for D48011: AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM): D48014: AMDGPU: Use generic tables instead of SearchableTable.
Jun 11 2018, 5:46 AM
nhaehnle added dependencies for D48014: AMDGPU: Use generic tables instead of SearchableTable: D48011: AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM), D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 5:46 AM
nhaehnle added a dependent revision for D48013: TableGen/SearchableTables: Support more generic enums and tables: D48014: AMDGPU: Use generic tables instead of SearchableTable.
Jun 11 2018, 5:46 AM
nhaehnle created D48014: AMDGPU: Use generic tables instead of SearchableTable.
Jun 11 2018, 5:45 AM
nhaehnle created D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 5:44 AM
nhaehnle added a dependency for D48011: AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM): D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.
Jun 11 2018, 4:52 AM
nhaehnle added a dependent revision for D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand: D48011: AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM).
Jun 11 2018, 4:52 AM
nhaehnle created D48011: AMDGPU: Pass AMDGPUSampleVariant to MIMG_{Sampler,Gather}(_WQM).
Jun 11 2018, 4:51 AM
nhaehnle accepted D48005: [NFC][AMDGPU] Add tests for all the various IR patterns equivalent to extracting low bits..
Jun 11 2018, 3:01 AM · Restricted Project
nhaehnle requested changes to D47980: [InstCombine] Fold (x << y) >> y -> x & (-1 >> y).
Jun 11 2018, 3:00 AM
nhaehnle added inline comments to D47980: [InstCombine] Fold (x << y) >> y -> x & (-1 >> y).
Jun 11 2018, 2:59 AM

Jun 5 2018

nhaehnle retitled D47761: AMDGPU: Add implicit def of SCC to kill and indirect pseudos from AMDGPU: Add implicit use of SCC to kill and indirect pseudos to AMDGPU: Add implicit def of SCC to kill and indirect pseudos.
Jun 5 2018, 12:16 AM
nhaehnle created D47761: AMDGPU: Add implicit def of SCC to kill and indirect pseudos.
Jun 5 2018, 12:12 AM

Jun 4 2018

nhaehnle added inline comments to D47566: AMDHSA: Code object v3 updates.
Jun 4 2018, 1:26 PM
nhaehnle added a comment to D47601: AMDGPU: Add 64-bit relative variant kind.

Sorry, I somehow managed to miss the REL64 definition. It's fine.

Jun 4 2018, 1:24 PM
nhaehnle added a comment to D47727: [WebAssembly] Fix .td files after rL333900.

My apologies. I thought I was testing all targets, but clearly I wasn't, and I didn't see buildbot failures.

Jun 4 2018, 12:43 PM
nhaehnle updated the diff for D47431: TableGen: Allow foreach in multiclass to depend on template args.

Address a review comment

Jun 4 2018, 12:23 PM
nhaehnle added inline comments to D47431: TableGen: Allow foreach in multiclass to depend on template args.
Jun 4 2018, 12:19 PM
nhaehnle added a comment to D47431: TableGen: Allow foreach in multiclass to depend on template args.

Ping.

Jun 4 2018, 7:49 AM
nhaehnle added inline comments to D47430: TableGen: Streamline the semantics of NAME.
Jun 4 2018, 7:30 AM
nhaehnle added inline comments to D47566: AMDHSA: Code object v3 updates.
Jun 4 2018, 7:19 AM
nhaehnle added a comment to D47601: AMDGPU: Add 64-bit relative variant kind.

What is this actually needed for? Having a relative relocation in a data segment doesn't seem that useful?

Jun 4 2018, 7:15 AM
nhaehnle added a comment to D47601: AMDGPU: Add 64-bit relative variant kind.

What is this actually needed for? Having a relative relocation in a data segment doesn't seem that useful?

Jun 4 2018, 7:09 AM
nhaehnle accepted D47664: [AMDGPU] Factored out common part of GCNRPTracker::reset().
Jun 4 2018, 7:05 AM
nhaehnle accepted D47661: [AMDGPU] Small refactoring in the scheduler.
Jun 4 2018, 7:04 AM
nhaehnle added a comment to D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.
In D47434#1118807, @dp wrote:

Regarding partial register updates: would there be any performance benefit from supporting this feature for MIMG? I.e. cannot we just ignore this feature and handle upper bits as undefined?

Jun 4 2018, 7:03 AM

May 30 2018

nhaehnle added a comment to D46054: [TableGen] Add a general-purpose JSON backend..

And by the way, I do agree with your rationale for why !name is very useful to have in JSON. The C++ backends can (and do) use Record::getName() for the same functionality.

May 30 2018, 6:37 AM
nhaehnle added a comment to D46054: [TableGen] Add a general-purpose JSON backend..

There are arguments both for !key + !name and for !name + !anonymous, although thinking about it for a minute or two I weakly prefer !name + !anonymous because it matches the representation in C++. It makes it easier for people to move between JSON and C++.

May 30 2018, 6:36 AM
nhaehnle added a comment to D47432: TableGen/DAGPatterns: Allow bit constants in addition to int constants.

I agree on the test case, unfortunately it requires a lot of setup to make the backend do anything useful at all.

May 30 2018, 6:12 AM
nhaehnle added a comment to D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.

I was thinking of actually moving the opposite direction for these. For modeling partial register updates, I think having operands for all of these is unmanageable. The problem is worse for ALU instructions with the zero high bit control bit. I think the same issues apply here. What is the behavior for the high bits if only 1 or 3 components are enabled?

IIRC the high bits are preserved except when ECC is enabled.

Okay, so modeling partial register updates. That would require us to add a $vdst_orig tied operand, right? Is there anything else, or any reason why we couldn't just do that unconditionally (but as an undef use), whether D16 or not?

Actually, can we have a VGPR32_LO/HI as the vdata register class for modeling the fact that the upper bits are preserved?

I'm not sure. I've only looked at this a little bit before but it certainly needs experimentation. My guess is the tied operand will be necessary

May 30 2018, 6:08 AM
nhaehnle added a dependency for D47530: TableGen: some LangRef doc fixes: D47430: TableGen: Streamline the semantics of NAME.
May 30 2018, 4:22 AM
nhaehnle added a dependent revision for D47430: TableGen: Streamline the semantics of NAME: D47530: TableGen: some LangRef doc fixes.
May 30 2018, 4:22 AM
nhaehnle created D47530: TableGen: some LangRef doc fixes.
May 30 2018, 4:22 AM
nhaehnle added a comment to D47430: TableGen: Streamline the semantics of NAME.

Thank you for the review!

May 30 2018, 4:21 AM
nhaehnle updated the diff for D47430: TableGen: Streamline the semantics of NAME.

Address review comments.

May 30 2018, 4:21 AM
nhaehnle updated the summary of D47430: TableGen: Streamline the semantics of NAME.
May 30 2018, 4:21 AM
nhaehnle added inline comments to D47525: [TableGen] Make DAGInstruction own Pattern to avoid leaking it..
May 30 2018, 4:08 AM

May 29 2018

nhaehnle added inline comments to D47429: TableGen: add some more helpful error messages.
May 29 2018, 8:55 AM
nhaehnle updated the diff for D47429: TableGen: add some more helpful error messages.

Fix typo.

May 29 2018, 8:54 AM
nhaehnle added a comment to D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.

I was thinking of actually moving the opposite direction for these. For modeling partial register updates, I think having operands for all of these is unmanageable. The problem is worse for ALU instructions with the zero high bit control bit. I think the same issues apply here. What is the behavior for the high bits if only 1 or 3 components are enabled?

IIRC the high bits are preserved except when ECC is enabled.

Okay, so modeling partial register updates. That would require us to add a $vdst_orig tied operand, right? Is there anything else, or any reason why we couldn't just do that unconditionally (but as an undef use), whether D16 or not?

May 29 2018, 8:40 AM
nhaehnle added a comment to D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.

I was thinking of actually moving the opposite direction for these. For modeling partial register updates, I think having operands for all of these is unmanageable. The problem is worse for ALU instructions with the zero high bit control bit. I think the same issues apply here. What is the behavior for the high bits if only 1 or 3 components are enabled?

May 29 2018, 8:37 AM
nhaehnle added a reviewer for D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand: dstuttard.
May 29 2018, 2:37 AM

May 27 2018

nhaehnle added a comment to D46756: [AMDGPU] Reworked SIFixWWMLiveness.

Sorry I didn't get to this earlier, but would you mind holding off on this a little bit? I'd like to think this through.

May 27 2018, 2:15 PM
nhaehnle accepted D47426: [AMDGPU] Fixed build warning.

It's an intrinsic vs. unsigned warning. LGTM.

May 27 2018, 2:05 PM
nhaehnle added a dependency for D47432: TableGen/DAGPatterns: Allow bit constants in addition to int constants: D47431: TableGen: Allow foreach in multiclass to depend on template args.
May 27 2018, 1:56 PM
nhaehnle added a dependent revision for D47431: TableGen: Allow foreach in multiclass to depend on template args: D47432: TableGen/DAGPatterns: Allow bit constants in addition to int constants.
May 27 2018, 1:56 PM
nhaehnle added a dependent revision for D47433: AMDGPU: Make various NamedOperands upper case: D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.
May 27 2018, 1:55 PM
nhaehnle added a dependency for D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand: D47433: AMDGPU: Make various NamedOperands upper case.
May 27 2018, 1:55 PM