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piotr (Piotr Sobczak)
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User Since
Dec 4 2018, 6:02 AM (99 w, 3 d)

Recent Activity

Thu, Oct 22

piotr added inline comments to D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.
Thu, Oct 22, 11:43 PM · Restricted Project
piotr committed rG7ae0033ca881: [AMDGPU] Fix expansion of i16 MULH (authored by piotr).
[AMDGPU] Fix expansion of i16 MULH
Thu, Oct 22, 8:06 AM
piotr closed D89965: [AMDGPU] Fix expansion of i16 MULH.
Thu, Oct 22, 8:06 AM · Restricted Project
piotr added a comment to D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Ping.

Thu, Oct 22, 7:59 AM · Restricted Project
piotr added a reviewer for D89965: [AMDGPU] Fix expansion of i16 MULH: arsenm.
Thu, Oct 22, 7:57 AM · Restricted Project
piotr requested review of D89965: [AMDGPU] Fix expansion of i16 MULH.
Thu, Oct 22, 7:56 AM · Restricted Project

Wed, Oct 21

piotr added a comment to D80485: [DAGCombiner][PowerPC] Remove isMulhCheaperThanMulShift TLI hook. Use isOperationLegalOrCustom directly instead..

Hi! This commit causes problems for AMDGPU backend - see attached file

. Any ideas before I start investigating this in detail?

LLVM ERROR: Cannot select: t56: i16 = mulhs t42, Constant:i16<-32509>

t42: i16 = truncate t67
  t67: i32 = add t66, t28
    t66: i32 = add t37, t34
      t37: i32 = shl nuw nsw t12, Constant:i32<13>
        t12: i32,ch = CopyFromReg t0, Register:i32 %5
          t11: i32 = Register %5
        t36: i32 = Constant<13>
      t34: i32 = shl nuw nsw t10, Constant:i32<7>
        t10: i32,ch = CopyFromReg t0, Register:i32 %4
          t9: i32 = Register %4
        t26: i32 = Constant<7>
    t28: i32 = add t16, t27
      t16: i32,ch = CopyFromReg t0, Register:i32 %7
        t15: i32 = Register %7
      t27: i32 = shl t8, Constant:i32<7>
        t8: i32,ch = CopyFromReg t0, Register:i32 %3
          t7: i32 = Register %3
        t26: i32 = Constant<7>
t52: i16 = Constant<-32509>

Hi, I agree with the suggestion by @dmgreen. Could you see if that works?

Wed, Oct 21, 2:53 AM · Restricted Project

Tue, Oct 20

piotr added a comment to D80485: [DAGCombiner][PowerPC] Remove isMulhCheaperThanMulShift TLI hook. Use isOperationLegalOrCustom directly instead..

Hi! This commit causes problems for AMDGPU backend - see attached file

. Any ideas before I start investigating this in detail?

Tue, Oct 20, 8:08 AM · Restricted Project

Mon, Oct 19

piotr committed rGc872faf6e091: [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7 (authored by piotr).
[AMDGPU] Do not generate S_CMP_LG_U64 on gfx7
Mon, Oct 19, 5:45 AM
piotr closed D89536: [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7.
Mon, Oct 19, 5:45 AM · Restricted Project

Fri, Oct 16

piotr added a reviewer for D89536: [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7: rampitec.
Fri, Oct 16, 3:47 AM · Restricted Project
piotr added a comment to D89536: [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7.

Related to D78091.

Fri, Oct 16, 3:46 AM · Restricted Project
piotr added reviewers for D89536: [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7: arsenm, alex-t.
Fri, Oct 16, 3:42 AM · Restricted Project
piotr requested review of D89536: [AMDGPU] Do not generate S_CMP_LG_U64 on gfx7.
Fri, Oct 16, 3:40 AM · Restricted Project

Thu, Oct 15

piotr updated the diff for D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Renamed variable to avoid a multiline assignment.

Thu, Oct 15, 7:13 AM · Restricted Project
piotr updated the diff for D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Good spot - I looked at the shader database and indeed the pattern with two connected setcc is frequent enough to special case it so I updated the patch.

Thu, Oct 15, 7:07 AM · Restricted Project

Fri, Oct 9

piotr updated the diff for D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Invert the condition.

Fri, Oct 9, 3:54 PM · Restricted Project

Tue, Oct 6

piotr added a comment to D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Ah now I see what you meant, sorry.

Tue, Oct 6, 7:47 AM · Restricted Project
piotr added a comment to D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Ping.

Tue, Oct 6, 5:19 AM · Restricted Project

Sep 23 2020

piotr committed rG8d7fd73c3a8c: [AMDGPU] Fix merging m0 inits (authored by piotr).
[AMDGPU] Fix merging m0 inits
Sep 23 2020, 12:15 AM
piotr closed D87882: [AMDGPU] Fix merging m0 inits.
Sep 23 2020, 12:15 AM · Restricted Project

Sep 22 2020

piotr added a comment to D87882: [AMDGPU] Fix merging m0 inits.
bb.1:
  ..
  TO_inst   (inits m0)
  ...       (uses m0)
  FROM_inst (clobbers m0)
  ...
  S_CBRANCH_VCCZ %bb.1, undef
  S_BRANCH %bb.2
Sep 22 2020, 6:47 AM · Restricted Project
piotr added inline comments to D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.
Sep 22 2020, 6:18 AM · Restricted Project
piotr updated the diff for D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

Simplified test and added 5 more.

Sep 22 2020, 6:14 AM · Restricted Project

Sep 20 2020

piotr added a comment to D87882: [AMDGPU] Fix merging m0 inits.

Doesn't loop block self dominate?

You mean, why the condition "MDT.dominates(From, To)" returns false if From and To are in the same BB? Inside that function there is a bb dominance check if the instructions are in different blocks, but if the instructions are in the same block the code checks whether From comes before To.

The bug I am trying to fix is simplified in the test m0-in-loop-0 where before my patch SI_INIT from line 333 was incorrectly removed. Although "m0 = COPY" comes after SI_INIT in that bb, this is a loop and in the second iteration DS_WRITE would see a clobbered m0, so SI_INIT has to be preserved.

That sounds like a bug in the dominate() to me.

Sep 20 2020, 11:43 PM · Restricted Project

Sep 18 2020

piotr added a comment to D87882: [AMDGPU] Fix merging m0 inits.

Doesn't loop block self dominate?

Sep 18 2020, 1:43 PM · Restricted Project

Sep 17 2020

piotr added reviewers for D87882: [AMDGPU] Fix merging m0 inits: rampitec, kerbowa, arsenm.
Sep 17 2020, 10:14 PM · Restricted Project
piotr requested review of D87882: [AMDGPU] Fix merging m0 inits.
Sep 17 2020, 10:13 PM · Restricted Project
piotr added inline comments to D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.
Sep 17 2020, 7:46 AM · Restricted Project

Sep 11 2020

piotr retitled D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB from [AMDGPU] Fix a miscompile in add combine to [AMDGPU] Fix a miscompile with S_ADD/S_SUB.
Sep 11 2020, 2:41 AM · Restricted Project
piotr updated the diff for D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.

I think you are right - I moved the fix to the better place.

Sep 11 2020, 2:39 AM · Restricted Project

Aug 31 2020

piotr added a reviewer for D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB: arsenm.
Aug 31 2020, 8:30 AM · Restricted Project
piotr requested review of D86878: [AMDGPU] Fix a miscompile with S_ADD/S_SUB.
Aug 31 2020, 8:30 AM · Restricted Project

Aug 27 2020

piotr committed rG4e9d207117f6: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK (authored by piotr).
[AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK
Aug 27 2020, 1:23 AM
piotr closed D86541: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK.
Aug 27 2020, 1:23 AM · Restricted Project

Aug 26 2020

piotr updated the diff for D86541: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK.

Switched to SIInstrInfo::fixImplicitOperands, thanks.

Aug 26 2020, 6:51 AM · Restricted Project
piotr updated the diff for D86541: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK.

As suggested, moved the code to buildShrunkInst where the instruction is created.

Aug 26 2020, 3:09 AM · Restricted Project

Aug 25 2020

piotr retitled D86541: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK from Preserve the vcc/vcc_lo when shrinking V_CNDMASK to Preserve vcc_lo when shrinking V_CNDMASK.
Aug 25 2020, 7:34 AM · Restricted Project
piotr added a reviewer for D86541: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK: arsenm.
Aug 25 2020, 7:32 AM · Restricted Project
piotr requested review of D86541: [AMDGPU] Preserve vcc_lo when shrinking V_CNDMASK.
Aug 25 2020, 7:31 AM · Restricted Project

Aug 11 2020

piotr added a comment to D84214: AMDGPU: Implement copy to scc with s_bitcmp1_b32.

Yes, this patch is not safe in general, because in some cases isel produces patterns where all bits of an SCC source are significant.

Aug 11 2020, 8:30 AM · Restricted Project

Aug 9 2020

piotr committed rG62d8b8a2253c: Fix 64-bit copy to SCC (authored by piotr).
Fix 64-bit copy to SCC
Aug 9 2020, 11:51 AM
piotr closed D85207: Fix 64-bit copy to SCC.
Aug 9 2020, 11:51 AM · Restricted Project

Aug 4 2020

piotr updated subscribers of D85207: Fix 64-bit copy to SCC.

@alex-t for awareness, as the code I am changing here was mentioned in https://reviews.llvm.org/D82194#2117180.

Aug 4 2020, 6:31 AM · Restricted Project
piotr added a reviewer for D85207: Fix 64-bit copy to SCC: arsenm.
Aug 4 2020, 6:25 AM · Restricted Project
piotr requested review of D85207: Fix 64-bit copy to SCC.
Aug 4 2020, 6:22 AM · Restricted Project

Jul 27 2020

piotr committed rG590dd73c6ebd: [AMDGPU] Make generating cache invalidating instructions optional (authored by piotr).
[AMDGPU] Make generating cache invalidating instructions optional
Jul 27 2020, 12:53 AM
piotr closed D84448: [AMDGPU] Make generating cache invalidating instructions optional.
Jul 27 2020, 12:53 AM · Restricted Project

Jul 24 2020

piotr updated the diff for D84448: [AMDGPU] Make generating cache invalidating instructions optional.

Renamed the option and variable.

Jul 24 2020, 8:08 AM · Restricted Project

Jul 23 2020

piotr added a reviewer for D84448: [AMDGPU] Make generating cache invalidating instructions optional: nhaehnle.
Jul 23 2020, 10:29 AM · Restricted Project
Herald added a project to D84448: [AMDGPU] Make generating cache invalidating instructions optional: Restricted Project.
Jul 23 2020, 10:28 AM · Restricted Project

Jul 21 2020

piotr added a comment to D84214: AMDGPU: Implement copy to scc with s_bitcmp1_b32.

Hmm, I am getting Vulkan CTS failures with this patch. I'll try to gather more information.

Jul 21 2020, 9:35 AM · Restricted Project
piotr added a comment to D84223: [AMDGPU] Don't combine memory intrs to v3i16.

Looks good to me as a stop-gap solution.

Jul 21 2020, 3:51 AM · Restricted Project

Jul 2 2020

piotr added inline comments to D81675: SILoadStoreOptimizer: add support for GFX10 image instructions.
Jul 2 2020, 12:29 AM · Restricted Project
piotr added a comment to D81675: SILoadStoreOptimizer: add support for GFX10 image instructions.

Excellent test coverage, thank you for doing that.

Jul 2 2020, 12:29 AM · Restricted Project

Jul 1 2020

piotr added inline comments to D81675: SILoadStoreOptimizer: add support for GFX10 image instructions.
Jul 1 2020, 1:02 AM · Restricted Project

Jun 25 2020

piotr added a comment to D82194: [AMDGPU] Enable compare operations to be selected by divergence.

Heads-up, this change slightly conflicts textually with my change to select s_cselect which I just recommitted following a bug-fix in 0045786f146e78afee49eee053dc29ebc842fee1.

Jun 25 2020, 3:04 AM · Restricted Project
piotr closed D82370: [AMDGPU] Rework SCC copy.
Jun 25 2020, 2:08 AM · Restricted Project
piotr committed rG0045786f146e: [AMDGPU] Select s_cselect (authored by piotr).
[AMDGPU] Select s_cselect
Jun 25 2020, 1:57 AM

Jun 24 2020

piotr updated the diff for D82370: [AMDGPU] Rework SCC copy.

Reworded comment, added a TODO.

Jun 24 2020, 1:02 AM · Restricted Project

Jun 23 2020

piotr added inline comments to D82370: [AMDGPU] Rework SCC copy.
Jun 23 2020, 8:31 AM · Restricted Project
piotr added a reviewer for D82370: [AMDGPU] Rework SCC copy: arsenm.
Jun 23 2020, 5:17 AM · Restricted Project
piotr created D82370: [AMDGPU] Rework SCC copy.
Jun 23 2020, 5:17 AM · Restricted Project

Jun 19 2020

piotr committed rG6d9565d6d554: Revert "[AMDGPU] Select s_cselect" (authored by piotr).
Revert "[AMDGPU] Select s_cselect"
Jun 19 2020, 8:06 AM
piotr added a reverting change for rG4067de569f11: [AMDGPU] Select s_cselect: rG6d9565d6d554: Revert "[AMDGPU] Select s_cselect".
Jun 19 2020, 8:06 AM
piotr committed rG4067de569f11: [AMDGPU] Select s_cselect (authored by piotr).
[AMDGPU] Select s_cselect
Jun 19 2020, 7:33 AM
piotr closed D81925: [AMDGPU] Select s_cselect.
Jun 19 2020, 7:33 AM · Restricted Project

Jun 18 2020

piotr added inline comments to D81925: [AMDGPU] Select s_cselect.
Jun 18 2020, 3:21 PM · Restricted Project
piotr updated the diff for D81925: [AMDGPU] Select s_cselect.

Added MIR test to test undef SCC, added minor tweaks in lowerSelect and rebased.

Jun 18 2020, 3:21 PM · Restricted Project
piotr added inline comments to D81925: [AMDGPU] Select s_cselect.
Jun 18 2020, 8:40 AM · Restricted Project
piotr updated the diff for D81925: [AMDGPU] Select s_cselect.

Addressed review comments.

Jun 18 2020, 8:40 AM · Restricted Project

Jun 16 2020

piotr added reviewers for D81925: [AMDGPU] Select s_cselect: arsenm, nhaehnle.
Jun 16 2020, 4:23 AM · Restricted Project
piotr created D81925: [AMDGPU] Select s_cselect.
Jun 16 2020, 4:23 AM · Restricted Project

May 18 2020

piotr accepted D78860: [AMDGPU] Fixed incorrect PAL metadata register naming.

LGTM

May 18 2020, 7:29 AM · Restricted Project

May 14 2020

piotr added a comment to D79037: [StructurizeCFG] Fix region nodes ordering.

- this can possibly be simplified even more, but it takes ages to cut down.

May 14 2020, 6:57 AM · Restricted Project
piotr added a comment to D79037: [StructurizeCFG] Fix region nodes ordering.

Hi, This commit makes some compilations go into an infinite loop. I will try to prepare a reproducer.

May 14 2020, 3:42 AM · Restricted Project

Apr 24 2020

piotr committed rG7631af3af279: [AMDGPU] Skip generating cache invalidating instructions on AMDPAL (authored by piotr).
[AMDGPU] Skip generating cache invalidating instructions on AMDPAL
Apr 24 2020, 5:22 AM
piotr closed D78800: [AMDGPU] Skip generating cache invalidating instructions on AMDPAL.
Apr 24 2020, 5:22 AM · Restricted Project
piotr added a reviewer for D78800: [AMDGPU] Skip generating cache invalidating instructions on AMDPAL: nhaehnle.
Apr 24 2020, 2:06 AM · Restricted Project
piotr created D78800: [AMDGPU] Skip generating cache invalidating instructions on AMDPAL.
Apr 24 2020, 1:34 AM · Restricted Project

Apr 20 2020

piotr committed rGc48ceaf37b0b: Revert "[AMDGPU] Set the CostPerUse value for vgpr registers." (authored by piotr).
Revert "[AMDGPU] Set the CostPerUse value for vgpr registers."
Apr 20 2020, 2:07 PM
piotr added a reverting change for rG728b878de689: [AMDGPU] Set the CostPerUse value for vgpr registers.: rGc48ceaf37b0b: Revert "[AMDGPU] Set the CostPerUse value for vgpr registers.".
Apr 20 2020, 2:07 PM
piotr added a comment to D76417: [AMDGPU] Set a cost model for vgpr registers..

The patch has caused vgpr count to go up significantly in real-world graphics content. Agreed with @cdevadas to revert for now.

Apr 20 2020, 2:05 PM · Restricted Project

Mar 19 2020

piotr committed rG4d8a72027706: [NFC] Simplify test (authored by piotr).
[NFC] Simplify test
Mar 19 2020, 7:00 AM
piotr added inline comments to D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes.
Mar 19 2020, 6:59 AM · Restricted Project

Mar 18 2020

piotr committed rGd1a7bfca7436: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes (authored by piotr).
[AMDGPU] Fix AMDGPUUnifyDivergentExitNodes
Mar 18 2020, 9:15 AM
piotr closed D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes.
Mar 18 2020, 9:15 AM · Restricted Project
piotr added inline comments to D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes.
Mar 18 2020, 9:14 AM · Restricted Project
piotr updated the diff for D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes.

Fix formatting.

Mar 18 2020, 8:08 AM · Restricted Project
piotr added a comment to D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes.

See D71192#1895125 for more context.

Mar 18 2020, 8:08 AM · Restricted Project
piotr added reviewers for D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes: nhaehnle, arsenm, cwabbott.
Mar 18 2020, 8:08 AM · Restricted Project
piotr created D76364: [AMDGPU] Fix AMDGPUUnifyDivergentExitNodes.
Mar 18 2020, 7:36 AM · Restricted Project

Feb 27 2020

piotr added a comment to D71192: AMDGPU: Fix AMDGPUUnifyDivergentExitNodes with no normal returns.

The reported example comes from one of graphicsfuzz CTS tests, so I think it is fine to treat it as an unrealistic corner case where performance is not critical.

Feb 27 2020, 9:05 AM · Restricted Project

Feb 21 2020

piotr added a comment to D71192: AMDGPU: Fix AMDGPUUnifyDivergentExitNodes with no normal returns.

Hi @cwabbott,
This commit causes a GPU hang on amdvlk in one test, due to the missing "done" bit on the normal export. I think in the attached case the patch incorrectly classifies the export as being in an infinite loop.

Feb 21 2020, 4:17 AM · Restricted Project

Jan 30 2020

piotr committed rGdd7148822bdc: [InstCombine][AMDGPU] Trim components of s_buffer_load (authored by piotr).
[InstCombine][AMDGPU] Trim components of s_buffer_load
Jan 30 2020, 1:50 AM
piotr closed D71785: [InstCombine][AMDGPU] Trim components of s_buffer_load.
Jan 30 2020, 1:49 AM · Restricted Project

Jan 29 2020

piotr updated the diff for D71785: [InstCombine][AMDGPU] Trim components of s_buffer_load.

Silenced clang-tidy warnings.

Jan 29 2020, 4:37 AM · Restricted Project
piotr updated the diff for D71785: [InstCombine][AMDGPU] Trim components of s_buffer_load.

Addressed review comments.

Jan 29 2020, 2:49 AM · Restricted Project

Jan 17 2020

piotr added a comment to D71785: [InstCombine][AMDGPU] Trim components of s_buffer_load.

I intend to merge the patch soon, based on the fact that the patch was reviewed in D70315. Compared to that version, 3 problematic cases were removed and tests updated.

Jan 17 2020, 7:46 AM · Restricted Project

Jan 10 2020

piotr added a comment to D71785: [InstCombine][AMDGPU] Trim components of s_buffer_load.

Ping.

Jan 10 2020, 2:11 AM · Restricted Project