[SelectionDAG] Do not second-guess alignment for alloca

[asavonic]

Summary

Alignment of an alloca in IR can be lower than the preferred alignment
on purpose, but this override essentially treats the preferred
alignment as the minimum alignment.

The patch changes this behavior to always use the specified
alignment. If alignment is not set explicitly in LLVM IR, it is set to
DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign.

Tests are changed as well: explicit alignment is increased to match
the preferred alignment if it changes output, or omitted when it is
hard to determine the right value (e.g. for pointers, some structs, or
weird types).

[asavonic]

A similar issue was discussed and fixed in D79532, where promotion of alignment caused stack realignment.
This patch now removes promotion of alignment, so we always use the specified alignment.

[efriedma]

Given we're de-emphasizing the type of allocas, this probably makes sense? We should be careful that this doesn't have unexpected effects, though; decreasing the alignment of an alloca could affect code generation. (For example, see D134282.)

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

130–131

Outdated comment?

llvm/test/CodeGen/AArch64/preferred-alignment.ll

10

Please explicitly specify alignment where possible.

I though the preferred alignment of i8 is 1? I can't see how this change has any practical effect.

[asavonic]

• Removed an outdated comment
• Added another testcase to AArch64/preferred-alignment.ll

[asavonic]

In D135462#3843425, @efriedma wrote:

Given we're de-emphasizing the type of allocas, this probably makes sense? We should be careful that this doesn't have unexpected effects, though; decreasing the alignment of an alloca could affect code generation. (For example, see D134282.)

Yes, this can cause some issues (as indicated by test changes), because alignment on alloca suddenly becomes more important.
Unfortunately, I don't see any other way how we can support alignment that is lower than the preferred alignment.

llvm/test/CodeGen/AArch64/preferred-alignment.ll

10

Apparently all 3 allocas have preferred alignment of 4.

It sound like the test is supposed to verify the preferred alignment. If we keep explicit alignment, it will take precedence over the preferred alignment.

So I suggest to have two tests: one where alignment is implicit, and another where alignment is set to whatever value we expect the preferred alignment to be.

[nikic]

This makes sense to me. InstCombine will still raise the alignment based on load/stores so long as it does not require stack realignment.

[asavonic]

• Rebased.

[asavonic]

@efriedma, can you please check this patch again?

[efriedma]

LGTM

[ronlieb]

hello , this commit is breaking our buildbot : could you address please ? https://lab.llvm.org/buildbot/#/builders/193

[asavonic]

In D135462#3998037, @ronlieb wrote:

hello , this commit is breaking our buildbot : could you address please ? https://lab.llvm.org/buildbot/#/builders/193

It sounds like the frontend does not set the right alignment in IR:

Libomptarget message: explicit extension not allowed: host address specified is 0x00007fff01df78a0 (12 bytes), but device allocation maps to host at 0x00007fff01df78a4 (8 bytes)

@ronlieb, do you know who can help with this on OpenMP side?

[ronlieb]

@jhuber6 please help with this one ? thanks

[arsenm]

Thanks, I've wanted to fix this for a long time. I have alignment decreasing optimizations I would like to perform

[asavonic]

I checked OpenMP tests, and the difference is pretty much what was expected. This is what we have as an input (the patch does not change the IR):

// x86_64-pc-linux-gnu :: mapping/ompx_hold/struct.c
struct S {
  int i;
  int j;
} s;
// CHECK: presence of s, s.i, s.j: 0, 0, 0
CHECK_PRESENCE(s, s.i, s.j);

IR:

%s = alloca %struct.S, align 4
%call = call i32 @omp_get_default_device()
%call1 = call i32 @omp_target_is_present(ptr noundef %s, i32 noundef %call)

The assembly is different: we keep alignment of 4 and do not increase it to the preferred value of 8.
Before the patch:

leaq    -16(%rbp), %rdi
callq   omp_target_is_present@PLT

After the patch:

leaq    -12(%rbp), %rdi
callq   omp_target_is_present@PLT

Libomptarget message: explicit extension not allowed: host address specified is 0x00007fff03109220 (12 bytes), but device allocation maps to host at 0x00007fff03109224 (8 bytes)

If I explicitly set __attribute__((aligned(8))) to the declaration of s, assembly before and after the patch becomes equivalent, so the problem should go away. Apparently there is some discrepancy in alignment that the frontend (or the OpenMP runtime) expects, but it is not obvious where we need to fix this.

[jhuber6]

In D135462#4006016, @asavonic wrote:

I checked OpenMP tests, and the difference is pretty much what was expected. This is what we have as an input (the patch does not change the IR):

// x86_64-pc-linux-gnu :: mapping/ompx_hold/struct.c
struct S {
  int i;
  int j;
} s;
// CHECK: presence of s, s.i, s.j: 0, 0, 0
CHECK_PRESENCE(s, s.i, s.j);

IR:

%s = alloca %struct.S, align 4
%call = call i32 @omp_get_default_device()
%call1 = call i32 @omp_target_is_present(ptr noundef %s, i32 noundef %call)

The assembly is different: we keep alignment of 4 and do not increase it to the preferred value of 8.
Before the patch:

leaq    -16(%rbp), %rdi
callq   omp_target_is_present@PLT

After the patch:

leaq    -12(%rbp), %rdi
callq   omp_target_is_present@PLT

Libomptarget message: explicit extension not allowed: host address specified is 0x00007fff03109220 (12 bytes), but device allocation maps to host at 0x00007fff03109224 (8 bytes)

If I explicitly set __attribute__((aligned(8))) to the declaration of s, assembly before and after the patch becomes equivalent, so the problem should go away. Apparently there is some discrepancy in alignment that the frontend (or the OpenMP runtime) expects, but it is not obvious where we need to fix this.

The error you get comes from the associated pointer we find extending before or after where we expect it to. My guess is that we think the device-side address is also four bytes, but is actually eight causing the discrepancy. Device in this case being the x86_64 code we generated for offloading, you should be able to see both using flags like here https://godbolt.org/z/EGzq7Tef4. I'm not sure why OpenMP seems to have a different preferred alignment. Total spitballing, but all the arguments to a target kernel in OpenMP are just treated as uintptr_t, might be always rounding up to 8 on the device side and this patch makes us not respect that anymore.

[asavonic]

It appears that the issue is caused by libomptarget mapping code that adds padding if the begin address does not have alignment of 8 (search for "alignment" in omptarget.cpp). The problem is that the padding is not applied consistently, so we may have a mapping without the padding (size == 8), and then get a request for a mapping with the padding (size == 12). Notice that we don't have Using a padding of 4 bytes for begin address for the first mapping, and we have it for the same exact pointer for the second mapping.

check: parent DynRefCount=1 is not sufficient for transfer
Libomptarget --> Entering data begin region for device -1 with 1 mappings
[...]
Libomptarget --> Entry  0: Base=0x00007ffc9b2581e4, Begin=0x00007ffc9b2581e4, Size=8, Type=0x2003, Name=unknown
Libomptarget --> Looking up mapping(HstPtrBegin=0x00007ffc9b2581e4, Size=8)...
Libomptarget --> Creating new map entry with HstPtrBase=0x00007ffc9b2581e4, HstPtrBegin=0x00007ffc9b2581e4, TgtPtrBegin=0x0000561d0739b390, Size=8, DynRefCount=0, HoldRefCount=1, Name=unknown
Libomptarget --> Moving 8 bytes (hst:0x00007ffc9b2581e4) -> (tgt:0x0000561d0739b390)
[...]
Libomptarget --> Entering target region for device -1 with entry point 0x0000561d059ca298
[...]
Libomptarget --> Entry  0: Base=0x00007ffc9b2581e4, Begin=0x00007ffc9b2581e4, Size=8, Type=0x20, Name=unknown
Libomptarget --> Entry  1: Base=0x00007ffc9b2581e4, Begin=0x00007ffc9b2581e4, Size=4, Type=0x1000000000002, Name=unknown
Libomptarget --> Entry  2: Base=0x00007ffc9b2581e4, Begin=0x00007ffc9b2581e8, Size=4, Type=0x1000000000002, Name=unknown
Libomptarget --> loop trip count is 0.
Libomptarget --> Using a padding of 4 bytes for begin address 0x00007ffc9b2581e4
Libomptarget --> Looking up mapping(HstPtrBegin=0x00007ffc9b2581e0, Size=12)...
Libomptarget --> WARNING: Pointer is not mapped but section extends into already mapped data
Libomptarget message: explicit extension not allowed: host address specified is 0x00007ffc9b2581e0 (12 bytes), but device allocation maps to host at 0x00007ffc9b2581e4 (8 bytes)

I'm not sure how to fix this issue. The obvious solution is to pass the padding value to DeviceTy::getTargetPointer, and ignore it if we already have a mapping without it (since alignment requirements are already satisfied, right?). Another option is to apply padding more consistently, but I don't know enough about OpenMP to figure out what exactly is wrong with the current implementation.

@grokos, @Hahnfeld, do you have any suggestions how to fix this issue? The handling of alignment was added in D44186.

[Hahnfeld]

Hi @asavonic, after reading through the comments here and peeking into D44186, I think your analysis is correct: libomptarget assumes that it can pad the start address of every member to 8 bytes and stay within the requested size, which isn't true anymore. I'm not sure if it would be possible to "fix up" this mistake by increasing the padding requirements in the IR generated by the Clang frontend (do we control all allocas and can they also be passed in by other parts of code?). I guess the better approach would indeed be to correct the implementation in the runtime library. That said, I haven't looked into the OpenMP offloading code for quite some time, more active members include @jdoerfert @jhuber6 @ronlieb (all of which have been pinged already...)

From the outside, and remembering many discussions and changes around alignment of struct members, a viable approach may be to disable the padding code in libomptarget and see which cases actually break. I wouldn't be super surprised if some / most of the complexity isn't actually needed anymore and is dealt with (more correctly) in the frontend.

[lkail]

Is there any progress with this patch? This patch can fix our downstream test failure which is caused by insistent alignment between IR and backend, thus affects alias analysis.

[asavonic]

In D135462#4112048, @lkail wrote:

Is there any progress with this patch? This patch can fix our downstream test failure which is caused by insistent alignment between IR and backend, thus affects alias analysis.

Yes, the regression in OpenMP was fixed, and I plan to land this patch today.

[asavonic]

The patch is merged (again). Please let me know if it causes any regressions for in-tree targets or tests.

[alexfh]

In D135462#4115559, @asavonic wrote:

The patch is merged (again). Please let me know if it causes any regressions for in-tree targets or tests.

An early heads up: we started seeing some test failures after this commit, but I can't yet tell whether the commit or the code is at fault.

[alexfh]

In D135462#4125805, @alexfh wrote:

In D135462#4115559, @asavonic wrote:

The patch is merged (again). Please let me know if it causes any regressions for in-tree targets or tests.

An early heads up: we started seeing some test failures after this commit, but I can't yet tell whether the commit or the code is at fault.

The only data point so far is that failures are happening on AArch64, which is alignment-sensitive.

[alexfh]

In D135462#4125826, @alexfh wrote:

In D135462#4125805, @alexfh wrote:

In D135462#4115559, @asavonic wrote:

The patch is merged (again). Please let me know if it causes any regressions for in-tree targets or tests.

An early heads up: we started seeing some test failures after this commit, but I can't yet tell whether the commit or the code is at fault.

The only data point so far is that failures are happening on AArch64, which is alignment-sensitive.

False alarm. All the problems we've seen so far are due to UB in the code.

[zjaffal]

Hello this commit is causing a compiler crash for the following example:
https://llvm.godbolt.org/z/xajYWoa8K

[jrtc27]

In D135462#4347294, @zjaffal wrote:

Hello this commit is causing a compiler crash for the following example:
https://llvm.godbolt.org/z/xajYWoa8K

That seems to generate MIR where there are adjacent scaled and unscaled 32-bit stores of wzr, but AArch64LoadStoreOpt::mergeNarrowZeroStores looks pretty broken if you mix scaled-ness, as it determines IsScaled based on just one of the instructions and then uses that to determine what the immediate means. Either those need to be skipped over or the function needs to learn how to handle that mix.

[mstorsjo]

I've bisected a broken test in libcxx for the mingw/x86_64 target down to this commit - see https://github.com/llvm/llvm-project/issues/64253 for a full bug report including a reduced reproducer.

[efriedma]

I've bisected a broken test in libcxx for the mingw/x86_64 target down to this commit - see https://github.com/llvm/llvm-project/issues/64253 for a full bug report including a reduced reproducer.

Most likely exposing an issue elsewhere. All this patch does is change the alignment of allocas, so most likely there's some unrelated problem related to or exposed by the stack layout. (Or maybe some other optimization is making bad assumptions about alloca alignment, but that's unlikely given the way the APIs in question work.) Probably using opt-bisect-limit to bisect the exact optimization in question would help narrow down the issue.

[mstorsjo]

In D135462#4548436, @efriedma wrote:

I've bisected a broken test in libcxx for the mingw/x86_64 target down to this commit - see https://github.com/llvm/llvm-project/issues/64253 for a full bug report including a reduced reproducer.

Most likely exposing an issue elsewhere. All this patch does is change the alignment of allocas, so most likely there's some unrelated problem related to or exposed by the stack layout. (Or maybe some other optimization is making bad assumptions about alloca alignment, but that's unlikely given the way the APIs in question work.) Probably using opt-bisect-limit to bisect the exact optimization in question would help narrow down the issue.

Thanks, I'll try to look into that and see if I can pinpoint anything. The surprising thing here though, is that the error occurs in unoptimized builds, while when building with optimizations enabled, the code turns out to work just right.

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
 
   // Initialize the mapping of values to registers.  This is only set up for
   // instruction values that are used outside of the block that defines
   // them.
   const Align StackAlign = TFI->getStackAlign();
   for (const BasicBlock &BB : *Fn) {
     for (const Instruction &I : BB) {
       if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
         Type *Ty = AI->getAllocatedType();
-        Align TyPrefAlign = MF->getDataLayout().getPrefTypeAlign(Ty);
-        // The "specified" alignment is the alignment written on the alloca,
-        // or the preferred alignment of the type if none is specified.
-        //
-        // (Unspecified alignment on allocas will be going away soon.)
-        Align SpecifiedAlign = AI->getAlign();
-
-        // If the preferred alignment of the type is higher than the specified
-        // alignment of the alloca, promote the alignment, as long as it doesn't
-        // require realigning the stack.
-        //
-        // FIXME: Do we really want to second-guess the IR in isel?
-        Align Alignment =
-            std::max(std::min(TyPrefAlign, StackAlign), SpecifiedAlign);
+        Align Alignment = AI->getAlign();
 
         // Static allocas can be folded into the initial stack frame
         // adjustment. For targets that don't realign the stack, don't
         // do this if there is an extra alignment requirement.
         if (AI->isStaticAlloca() &&
             (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
           uint64_t TySize =

llvm/test/CodeGen/AArch64/preferred-alignment.ll

 ; RUN: llc -mtriple=aarch64 -O0 -fast-isel < %s | FileCheck %s
 
 ; Function Attrs: nounwind
 define i32 @foo() #0 {
 entry:
-  %c = alloca i8, align 1
+  %c = alloca i8
 ; CHECK:  add x0, sp, #12
-  %s = alloca i16, align 2
+  %s = alloca i16
 ; CHECK-NEXT: add x1, sp, #8
-  %i = alloca i32, align 4
+  %i = alloca i32
 ; CHECK-NEXT: add x2, sp, #4
   %call = call i32 @bar(ptr %c, ptr %s, ptr %i)
   %0 = load i8, ptr %c, align 1
   %conv = zext i8 %0 to i32
   %add = add nsw i32 %call, %conv
   %1 = load i16, ptr %s, align 2
   %conv1 = sext i16 %1 to i32
   %add2 = add nsw i32 %add, %conv1

llvm/test/CodeGen/AArch64/seh-finally.ll

 ; CHECK-LABEL: simple_seh
 ; CHECK: add     x29, sp, #16
 ; CHECK: mov     x0, #-2
 ; CHECK: stur    x0, [x29, #16]
 ; CHECK: .set .Lsimple_seh$frame_escape_0, -8
 ; CHECK: ldur    w0, [x29, #-8]
 ; CHECK: bl      foo
 
-  %o = alloca %struct.S, align 4
+  %o = alloca %struct.S, align 8
   call void (...) @llvm.localescape(ptr %o)
   %0 = load i32, ptr %o, align 4
   invoke void @foo(i32 %0) #5
           to label %invoke.cont unwind label %ehcleanup
 
 invoke.cont:                                      ; preds = %entry
   %1 = call ptr @llvm.localaddress()
   call void @fin_simple_seh(i8 0, ptr %1)

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

 ; HSA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[0:3], [[SP]] offset:4
 
 ; MESA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[36:39], [[SP]]{{$}}
 ; MESA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:4
 
 ; GCN-NEXT: s_swappc_b64
 ; GCN-NOT: [[SP]]
 define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {
-  %val = alloca { i8, i32 }, align 4, addrspace(5)
+  %val = alloca { i8, i32 }, align 8, addrspace(5)
   %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 0
   %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 1
   store i8 3, ptr addrspace(5) %gep0
   store i32 8, ptr addrspace(5) %gep1
   call void @external_void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 }) %val)
   ret void
 }
 

 ; GCN: s_swappc_b64
 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16
 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:20
 ; GCN-NOT: s_sub_u32 [[SP]]
 
 ; GCN: buffer_store_byte [[LOAD_OUT_VAL0]], off
 ; GCN: buffer_store_dword [[LOAD_OUT_VAL1]], off
 define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
-  %in.val = alloca { i8, i32 }, align 4, addrspace(5)
-  %out.val = alloca { i8, i32 }, align 4, addrspace(5)
+  %in.val = alloca { i8, i32 }, align 8, addrspace(5)
+  %out.val = alloca { i8, i32 }, align 8, addrspace(5)
   %in.gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %in.val, i32 0, i32 0
   %in.gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %in.val, i32 0, i32 1
   store i8 3, ptr addrspace(5) %in.gep0
   store i32 8, ptr addrspace(5) %in.gep1
   call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(ptr addrspace(5) %out.val, ptr addrspace(5) byval({ i8, i32 }) %in.val)
   %out.gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %out.val, i32 0, i32 0
   %out.gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %out.val, i32 0, i32 1
   %out.val0 = load i8, ptr addrspace(5) %out.gep0

llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll

 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
 ; GFX9-MUBUF-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SHIFT]]
 
 ; GFX9-FLATSCR:      v_mov_b32_e32 [[SP:v[0-9]+]], s32
 ; GFX9-FLATSCR-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SP]]
 
 ; GCN: ds_write_b32 v{{[0-9]+}}, [[PTR]]
 define void @alloca_ptr_nonentry_block(i32 %arg0) #0 {
-  %alloca0 = alloca { i8, i32 }, align 4, addrspace(5)
+  %alloca0 = alloca { i8, i32 }, align 8, addrspace(5)
   %cmp = icmp eq i32 %arg0, 0
   br i1 %cmp, label %bb, label %ret
 
 bb:
   %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %alloca0, i32 0, i32 0
   %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %alloca0, i32 0, i32 1
   %load1 = load volatile i32, ptr addrspace(5) %gep1
   store volatile ptr addrspace(5) %gep1, ptr addrspace(3) undef

llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

 ; GFX10-FLATSCR-NEXT:    global_store_dwordx4 v[4:5], v[8:11], off offset:16
 ; GFX10-FLATSCR-NEXT:    global_store_dwordx4 v[4:5], v[0:3], off
 ; GFX10-FLATSCR-NEXT:    s_endpgm
 entry:
   %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
   %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
 
 ; allocate enough scratch to go beyond 2^12 addressing
-  %scratch = alloca <1280 x i32>, align 8, addrspace(5)
+  %scratch = alloca <1280 x i32>, align 16, addrspace(5)
 
 ; load VGPR data
   %aptr = getelementptr <64 x i32>, ptr addrspace(1) %in, i32 %tid
   %a = load <64 x i32>, ptr addrspace(1) %aptr
 
 ; make sure scratch is used
   %x = extractelement <64 x i32> %a, i32 0
   %sptr0 = getelementptr <1280 x i32>, ptr addrspace(5) %scratch, i32 %x, i32 0

llvm/test/CodeGen/ARM/ssp-data-layout.ll

 ; large array is assigned to the stack properly as a large object.
 ; CHECK: struct_with_protectable_arrays:
 ; CHECK: bl get_struct_small_char
 ; CHECK: strb r0, [sp, #68]
 ; CHECK: bl end_struct_small_char
 ; CHECK: bl get_struct_large_char2
 ; CHECK: strb r0, [sp, #106]
 ; CHECK: bl end_struct_large_char2
-  %a = alloca %struct.struct_small_char, align 1
-  %b = alloca %struct.struct_large_char2, align 1
+  %a = alloca %struct.struct_small_char, align 4
+  %b = alloca %struct.struct_large_char2, align 4
   %d1 = alloca %struct.struct_large_nonchar, align 8
   %d2 = alloca %struct.struct_small_nonchar, align 2
   %call = call signext i8 @get_struct_small_char()
   store i8 %call, ptr %a, align 1
   call void @end_struct_small_char()
   %call1 = call signext i8 @get_struct_large_char2()
   %foo2 = getelementptr inbounds %struct.struct_large_char2, ptr %b, i32 0, i32 1
   store i8 %call1, ptr %foo2, align 1

llvm/test/CodeGen/BPF/pr57872.ll

 ; CHECK-NEXT:    *(u8 *)(r10 - 86) = r2
 ; CHECK-NEXT:    r1 = *(u8 *)(r1 + 0)
 ; CHECK-NEXT:    *(u8 *)(r10 - 87) = r1
 ; CHECK-NEXT:    r1 = r10
 ; CHECK-NEXT:    r1 += -88
 ; CHECK-NEXT:    call bar
 ; CHECK-NEXT:    exit
 entry:
-  %event = alloca %struct.event, align 1
+  %event = alloca %struct.event, align 8
   %hostname = getelementptr inbounds %struct.event, ptr %event, i64 0, i32 1
   %0 = load ptr, ptr %g, align 8
   call void @llvm.memcpy.p0.p0.i64(ptr noundef nonnull align 1 dereferenceable(84) %hostname, ptr noundef nonnull align 1 dereferenceable(84) %0, i64 84, i1 false)
   call void @bar(ptr noundef nonnull %event)
   ret void
 }
 
 declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #2
 declare void @bar(ptr noundef)

llvm/test/CodeGen/BPF/undef.ll

 ; CHECK-DAG: *(u16 *)(r10 + 0) = r1
 ; CHECK-DAG: *(u16 *)(r10 + 26) = r1
 
 ; CHECK: r2 = r10
 ; CHECK: r2 += -8
 ; CHECK: r1 = routing
 ; CHECK: call bpf_map_lookup_elem
 ; CHECK: exit
-  %key = alloca %struct.routing_key_2, align 1
+  %key = alloca %struct.routing_key_2, align 8
   store i8 5, ptr %key, align 1
   %1 = getelementptr inbounds %struct.routing_key_2, ptr %key, i64 0, i32 0, i64 1
   store i8 6, ptr %1, align 1
   %2 = getelementptr inbounds %struct.routing_key_2, ptr %key, i64 0, i32 0, i64 2
   store i8 7, ptr %2, align 1
   %3 = getelementptr inbounds %struct.routing_key_2, ptr %key, i64 0, i32 0, i64 3
   store i8 8, ptr %3, align 1
   %4 = getelementptr inbounds %struct.routing_key_2, ptr %key, i64 0, i32 0, i64 4

llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s -verify-machineinstrs | FileCheck %s
 
 %struct.x = type { i32 }
 
 @i = common global i32 0, align 4
 
 define i32 @foobar(i32 signext %x) {
 entry:
 ; CHECK-LABEL: foobar:
   %retval = alloca i32, align 4
   %x.addr = alloca i32, align 4
-  %a = alloca %struct.x, align 4
-  %c = alloca ptr, align 4
+  %a = alloca %struct.x, align 8
+  %c = alloca ptr, align 8
   store i32 %x, ptr %x.addr, align 4
   %0 = load i32, ptr %x.addr, align 4
   store i32 %0, ptr %a, align 4
   store ptr %a, ptr %c, align 4
   %1 = load ptr, ptr %c, align 4
   %2 = load i32, ptr %1, align 4
   store i32 %2, ptr @i, align 4
   %3 = load i32, ptr %retval
 ; CHECK:        addiu   $[[A_ADDR:[0-9]+]], $sp, 8
 ; CHECK-DAG:    lw      $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
 ; CHECK-DAG:    sw      $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
 ; CHECK-DAG:    lw      $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
 ; CHECK-DAG:    lw      $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
 ; CHECK-DAG:    sw      $[[A_X]], 0($[[I_ADDR]])
   ret i32 %3
 }

llvm/test/CodeGen/Mips/atomic64.ll

 ; MIPS64EB-NEXT:    move $3, $4
 ; MIPS64EB-NEXT:    scd $3, 0($1)
 ; MIPS64EB-NEXT:    beqz $3, .LBB6_1
 ; MIPS64EB-NEXT:    nop
 ; MIPS64EB-NEXT:  # %bb.2: # %entry
 ; MIPS64EB-NEXT:    jr $ra
 ; MIPS64EB-NEXT:    daddiu $sp, $sp, 16
 entry:
-  %newval.addr = alloca i64, align 4
+  %newval.addr = alloca i64, align 8
   store i64 %newval, ptr %newval.addr, align 4
   %tmp = load i64, ptr %newval.addr, align 4
   %0 = atomicrmw xchg ptr @x, i64 %tmp monotonic
   ret i64 %0
 
 }
 
 define i64 @AtomicCmpSwap64(i64 signext %oldval, i64 signext %newval) nounwind {

 ; MIPS64EB-NEXT:    move $3, $5
 ; MIPS64EB-NEXT:    scd $3, 0($1)
 ; MIPS64EB-NEXT:    beqz $3, .LBB7_1
 ; MIPS64EB-NEXT:    nop
 ; MIPS64EB-NEXT:  .LBB7_3: # %entry
 ; MIPS64EB-NEXT:    jr $ra
 ; MIPS64EB-NEXT:    daddiu $sp, $sp, 16
 entry:
-  %newval.addr = alloca i64, align 4
+  %newval.addr = alloca i64, align 8
   store i64 %newval, ptr %newval.addr, align 4
   %tmp = load i64, ptr %newval.addr, align 4
   %0 = cmpxchg ptr @x, i64 %oldval, i64 %tmp monotonic monotonic
   %1 = extractvalue { i64, i1 } %0, 0
   ret i64 %1
 
 }

llvm/test/CodeGen/Mips/cconv/byval.ll

 ; N64-NEXT:    daddu $sp, $sp, $1
 ; N64-NEXT:    lui $1, 1
 ; N64-NEXT:    daddu $1, $sp, $1
 ; N64-NEXT:    ld $ra, -8($1) # 8-byte Folded Reload
 ; N64-NEXT:    lui $1, 1
 ; N64-NEXT:    jr $ra
 ; N64-NEXT:    daddu $sp, $sp, $1
 entry:
-  %a = alloca %struct.S1, align 4
+  %a = alloca %struct.S1, align 8
   call void @f2(ptr byval(%struct.S1) align 4 %a)
   ret void
 }
 
 declare dso_local void @f2(ptr byval(%struct.S1) align 4) #1
 
 ; O32-SDAG-LABEL: Initial selection DAG: %bb.0 'g2:entry'
 ; O32-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i32<{{.*}}>

 ; N64-NEXT:    lui $1, 1
 ; N64-NEXT:    daddu $1, $sp, $1
 ; N64-NEXT:    ld $ra, 8($1) # 8-byte Folded Reload
 ; N64-NEXT:    lui $1, 1
 ; N64-NEXT:    daddiu $1, $1, 16
 ; N64-NEXT:    jr $ra
 ; N64-NEXT:    daddu $sp, $sp, $1
 entry:
-  %a.addr = alloca ptr, align 4
-  %byval-temp = alloca %struct.S1, align 4
+  %a.addr = alloca ptr
+  %byval-temp = alloca %struct.S1, align 8
   store ptr %a, ptr %a.addr, align 4
   %0 = load ptr, ptr %a.addr, align 4
   call void @llvm.memcpy.p0.p0.i32(ptr align 4 %byval-temp, ptr align 1 %0, i32 65520, i1 false)
   call void @f2(ptr byval(%struct.S1) align 4 %byval-temp)
   ret void
 }
 
 ; O32-SDAG-LABEL: Initial selection DAG: %bb.0 'g3:entry'

 ; N64-NEXT:    sd $4, 16($sp)
 ; N64-NEXT:    jal memcpy
 ; N64-NEXT:    ori $6, $zero, 65520
 ; N64-NEXT:    addiu $2, $zero, 4
 ; N64-NEXT:    ld $ra, 24($sp) # 8-byte Folded Reload
 ; N64-NEXT:    jr $ra
 ; N64-NEXT:    daddiu $sp, $sp, 32
 entry:
-  %a.addr = alloca ptr, align 4
-  %b.addr = alloca ptr, align 4
+  %a.addr = alloca ptr
+  %b.addr = alloca ptr
   store ptr %a, ptr %a.addr, align 4
   store ptr %b, ptr %b.addr, align 4
   %0 = load ptr, ptr %a.addr, align 4
   %1 = load ptr, ptr %b.addr, align 4
   call void @llvm.memcpy.p0.p0.i32(ptr align 1 %0, ptr align 1 %1, i32 65520, i1 false)
   ret i32 4
 }
 
 declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) #2

llvm/test/CodeGen/Mips/cconv/return-struct.ll

 ; N64-LE-NEXT:    daddiu $1, $1, %hi(struct_2byte)
 ; N64-LE-NEXT:    dsll $1, $1, 16
 ; N64-LE-NEXT:    lhu $1, %lo(struct_2byte)($1)
 ; N64-LE-NEXT:    sh $1, 8($sp)
 ; N64-LE-NEXT:    lh $2, 8($sp)
 ; N64-LE-NEXT:    jr $ra
 ; N64-LE-NEXT:    daddiu $sp, $sp, 16
 entry:
-        %retval = alloca {i8,i8}, align 1
+        %retval = alloca {i8,i8}, align 8
         call void @llvm.memcpy.p0.p0.i64(ptr %retval, ptr @struct_2byte, i64 2, i1 false)
         %0 = load volatile {i16}, ptr %retval
         ret {i16} %0
 }
 
 ; Ensure that structures bigger than 32-bits but smaller than 64-bits are
 ; also returned in the upper bits on big endian targets. Previously, these were
 ; missed by the CCPromoteToType and the shift didn't happen.

llvm/test/CodeGen/Mips/largeimmprinting.ll

 
 ; 64:  lui     $[[R0:[0-9]+]], 1
 ; 64:  daddiu  $[[R0]], $[[R0]], 32
 ; 64:  dsubu   $sp, $sp, $[[R0]]
 ; 64:  lui     $[[R1:[0-9]+]], 1
 ; 64:  daddu   $[[R1]], $sp, $[[R1]]
 ; 64:  sd      $ra, 24($[[R1]])
 
-  %agg.tmp = alloca %struct.S1, align 1
+  %agg.tmp = alloca %struct.S1, align 8
   call void @llvm.memcpy.p0.p0.i32(ptr align 1 %agg.tmp, ptr align 1 @s1, i32 65536, i1 false)
   call void @f2(ptr byval(%struct.S1) %agg.tmp) nounwind
   ret void
 }
 
 declare void @f2(ptr byval(%struct.S1))
 
 declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind

llvm/test/CodeGen/Mips/o32_cc_byval.ll

 ; CHECK-NEXT:    move $gp, $16
 ; CHECK-NEXT:    lw $16, 48($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    lw $17, 52($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    lw $18, 56($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    lw $ra, 60($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $sp, $sp, 64
 entry:
-  %agg.tmp10 = alloca %struct.S3, align 4
+  %agg.tmp10 = alloca %struct.S3, align 8
   call void @callee1(float 2.000000e+01, ptr byval(%struct.S1) @f1.s1) nounwind
   call void @callee2(ptr byval(%struct.S2) @f1.s2) nounwind
   store i8 11, ptr %agg.tmp10, align 4
   call void @callee3(float 2.100000e+01, ptr byval(%struct.S3) %agg.tmp10, ptr byval(%struct.S1) @f1.s1) nounwind
   ret void
 }
 
 declare void @callee1(float, ptr byval(%struct.S1))

llvm/test/CodeGen/NVPTX/lower-byval-args.ll

bb:
   %load = load i8, ptr addrspace(101) %asc, align 4
   store i8 %load, ptr %out, align 4
   ret void
 }
 
 
 ; Verify that if the pointer escapes, then we do fall back onto using a temp copy.
 ; CHECK-LABEL: .visible .entry pointer_escapes
-; CHECK: .local .align 8 .b8     __local_depot{{.*}}
+; CHECK: .local .align 4 .b8     __local_depot{{.*}}
 ; CHECK64: ld.param.u64    [[result_addr:%rd[0-9]+]], [{{.*}}_param_0]
 ; CHECK64: add.u64         %[[copy_addr:rd[0-9]+]], %SPL, 0;
 ; CHECK32: ld.param.u32    [[result_addr:%r[0-9]+]], [{{.*}}_param_0]
 ; CHECK32: add.u32         %[[copy_addr:r[0-9]+]], %SPL, 0;
 ; CHECK-DAG: ld.param.u32    %{{.*}}, [pointer_escapes_param_1+12];
 ; CHECK-DAG: ld.param.u32    %{{.*}}, [pointer_escapes_param_1+8];
 ; CHECK-DAG: ld.param.u32    %{{.*}}, [pointer_escapes_param_1+4];
 ; CHECK-DAG: ld.param.u32    %{{.*}}, [pointer_escapes_param_1];

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

 %struct.S4 = type { [4 x i8] }
 %struct.S4A = type { i32 }
 
 @gS4 = external global %struct.S4, align 1
 
 define void @call_test_byval_4Byte() {
 entry:
   %s0 = alloca %struct.S0, align 8
-  %s4a = alloca %struct.S4A, align 4
+  %s4a = alloca %struct.S4A, align 8
   %call = call signext i32 @test_byval_4Byte(ptr byval(%struct.S4) align 1 @gS4, ptr byval(%struct.S0) align 1 %s0, ptr byval(%struct.S4A) align 4 %s4a)
   ret void
 }
 
 ; CHECK-LABEL: name: call_test_byval_4Byte{{.*}}
 
 ; 32BIT:       ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT:  renamable $r[[REG:[0-9]+]] = LWZtoc @gS4, $r2 :: (load (s32) from got)

 ; ASM64-DAG:      std 4, 56(1)
 ; ASM64-DAG:      std 6, 72(1)
 ; ASM64-NEXT:     blr
 
 %struct.F = type { float, float, float }
 
 define i32 @call_test_byval_homogeneous_float_struct() {
 entry:
-  %s = alloca %struct.F, align 4
+  %s = alloca %struct.F, align 8
   call void @llvm.memset.p0.i32(ptr align 4 %s, i8 0, i32 12, i1 false)
   %call = call i32 @test_byval_homogeneous_float_struct(ptr byval(%struct.F) align 4 %s)
   ret i32 %call
 }
 
 declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
 
 declare i32 @test_byval_homogeneous_float_struct(ptr byval(%struct.F) align 4)

llvm/test/CodeGen/PowerPC/aix-sret-param.ll

 ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec \
 ; RUN: --verify-machineinstrs < %s | FileCheck --check-prefixes=ASM,ASM64 %s
 
 %struct.S = type { i8 }
 %struct.T = type { double, i32, i32, i32, float }
 
 define void @test1() {
 entry:
-  %s = alloca %struct.S, align 4
+  %s = alloca %struct.S, align 8
   call void @foo(ptr sret(%struct.S) %s)
   ret void
 }
 
 define void @test2() {
 entry:
   %t = alloca %struct.T, align 8
   call void @bar(ptr sret(%struct.T) %t)

llvm/test/CodeGen/PowerPC/byval.ll

 ; CHECK-NEXT:    ld 3, 40(1)
 ; CHECK-NEXT:    bl foo1
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 80
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
-  %x = alloca %struct, align 4
+  %x = alloca %struct, align 8
   call void @foo(ptr %x)
   %r = call i32 @foo1(ptr byval(%struct) %x)
   ret i32 %r
 }

llvm/test/CodeGen/PowerPC/structsinregs.ll

 @caller2.p3 = private unnamed_addr constant %struct.t3 <{ i16 4, i8 8 }>, align 1
 @caller2.p4 = private unnamed_addr constant { i32 } { i32 16 }, align 1
 @caller2.p5 = private unnamed_addr constant %struct.t5 <{ i32 32, i8 64 }>, align 1
 @caller2.p6 = private unnamed_addr constant %struct.t6 <{ i32 128, i16 256 }>, align 1
 @caller2.p7 = private unnamed_addr constant %struct.t7 <{ i32 512, i16 1024, i8 -3 }>, align 1
 
 define i32 @caller1() nounwind {
 entry:
-  %p1 = alloca %struct.s1, align 1
-  %p2 = alloca %struct.s2, align 2
-  %p3 = alloca %struct.s3, align 2
-  %p4 = alloca %struct.s4, align 4
-  %p5 = alloca %struct.s5, align 4
-  %p6 = alloca %struct.s6, align 4
-  %p7 = alloca %struct.s7, align 4
+  %p1 = alloca %struct.s1
+  %p2 = alloca %struct.s2
+  %p3 = alloca %struct.s3
+  %p4 = alloca %struct.s4
+  %p5 = alloca %struct.s5
+  %p6 = alloca %struct.s6
+  %p7 = alloca %struct.s7
   call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr @caller1.p1, i64 1, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %p2, ptr align 2 @caller1.p2, i64 2, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr align 2 %p3, ptr align 2 @caller1.p3, i64 4, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p4, ptr align 4 @caller1.p4, i64 4, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p5, ptr align 4 @caller1.p5, i64 8, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p6, ptr align 4 @caller1.p6, i64 8, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p7, ptr align 4 @caller1.p7, i64 8, i1 false)
   %call = call i32 @callee1(ptr byval(%struct.s1) %p1, ptr byval(%struct.s2) %p2, ptr byval(%struct.s3) %p3, ptr byval(%struct.s4) %p4, ptr byval(%struct.s5) %p5, ptr byval(%struct.s6) %p6, ptr byval(%struct.s7) %p7)

 ; CHECK-DAG: lwz {{[0-9]+}}, 76(1)
 ; CHECK-DAG: lwz {{[0-9]+}}, 80(1)
 ; CHECK-DAG: lwz {{[0-9]+}}, 88(1)
 ; CHECK-DAG: lwz {{[0-9]+}}, 96(1)
 }
 
 define i32 @caller2() nounwind {
 entry:
-  %p1 = alloca %struct.t1, align 1
-  %p2 = alloca %struct.t2, align 1
-  %p3 = alloca %struct.t3, align 1
-  %p4 = alloca %struct.t4, align 1
-  %p5 = alloca %struct.t5, align 1
-  %p6 = alloca %struct.t6, align 1
-  %p7 = alloca %struct.t7, align 1
+  %p1 = alloca %struct.t1
+  %p2 = alloca %struct.t2
+  %p3 = alloca %struct.t3
+  %p4 = alloca %struct.t4
+  %p5 = alloca %struct.t5
+  %p6 = alloca %struct.t6
+  %p7 = alloca %struct.t7
   call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr @caller2.p1, i64 1, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr %p2, ptr @caller2.p2, i64 2, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr %p3, ptr @caller2.p3, i64 3, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr %p4, ptr @caller2.p4, i64 4, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr %p5, ptr @caller2.p5, i64 5, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr %p6, ptr @caller2.p6, i64 6, i1 false)
   call void @llvm.memcpy.p0.p0.i64(ptr %p7, ptr @caller2.p7, i64 7, i1 false)
   %call = call i32 @callee2(ptr byval(%struct.t1) %p1, ptr byval(%struct.t2) %p2, ptr byval(%struct.t3) %p3, ptr byval(%struct.t4) %p4, ptr byval(%struct.t5) %p5, ptr byval(%struct.t6) %p6, ptr byval(%struct.t7) %p7)

llvm/test/CodeGen/PowerPC/varargs-struct-float.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 < %s | FileCheck %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 %struct.Sf1 = type { float }
 
 define void @foo(float inreg %s.coerce) nounwind {
 entry:
-  %s = alloca %struct.Sf1, align 4
+  %s = alloca %struct.Sf1, align 8
   store float %s.coerce, ptr %s, align 1
   %0 = load float, ptr %s, align 1
   call void (i32, ...) @testvaSf1(i32 1, float inreg %0)
   ret void
 }
 
 ; CHECK: stfs {{[0-9]+}}, 116(1)
 ; CHECK: lwz 4, 116(1)
 ; CHECK: bl
 
 declare void @testvaSf1(i32, ...)

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

 ; RV32I-WITHFP-NEXT:    sw a2, -32(s0)
 ; RV32I-WITHFP-NEXT:    sw a3, -28(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -40
 ; RV32I-WITHFP-NEXT:    call callee_large_struct@plt
 ; RV32I-WITHFP-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 48
 ; RV32I-WITHFP-NEXT:    ret
-  %ls = alloca %struct.large, align 4
+  %ls = alloca %struct.large, align 8
   store i32 1, ptr %ls
   %b = getelementptr inbounds %struct.large, ptr %ls, i32 0, i32 1
   store i32 2, ptr %b
   %c = getelementptr inbounds %struct.large, ptr %ls, i32 0, i32 2
   store i32 3, ptr %c
   %d = getelementptr inbounds %struct.large, ptr %ls, i32 0, i32 3
   store i32 4, ptr %d
   %1 = call i32 @callee_large_struct(ptr byval(%struct.large) align 4 %ls)

llvm/test/CodeGen/RISCV/frame.ll

 ; RV32I-WITHFP-NEXT:    sw zero, -32(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -28
 ; RV32I-WITHFP-NEXT:    call test1@plt
 ; RV32I-WITHFP-NEXT:    li a0, 0
 ; RV32I-WITHFP-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 32
 ; RV32I-WITHFP-NEXT:    ret
-  %key = alloca %struct.key_t, align 4
+  %key = alloca %struct.key_t, align 8
   call void @llvm.memset.p0.i64(ptr align 4 %key, i8 0, i64 20, i1 false)
   %1 = getelementptr inbounds %struct.key_t, ptr %key, i64 0, i32 1, i64 0
   call void @test1(ptr %1)
   ret i32 0
 }
 
 declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1)
 
 declare void @test1(ptr)

llvm/test/CodeGen/RISCV/mem64.ll

 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    sb zero, 0(a0)
 ; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    call snork@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 bb:
-  %tmp = alloca %struct.quux, align 4
+  %tmp = alloca %struct.quux, align 8
   %tmp1 = getelementptr inbounds %struct.quux, ptr %tmp, i64 0, i32 1
   %tmp2 = getelementptr inbounds %struct.quux, ptr %tmp, i64 0, i32 1, i64 %arg
   store i8 0, ptr %tmp2, align 1
   call void @snork(ptr %tmp1)
   ret void
 }
 
 declare void @snork(ptr)

llvm/test/CodeGen/RISCV/vararg.ll

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, s0, 12
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lw a0, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va, align 4
   %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
   store ptr %argp.next, ptr %va, align 4
   %1 = load i32, ptr %argp.cur, align 4
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i32
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }
 
 ; Ensure the adjustment when restoring the stack pointer using the frame
 ; pointer is correct

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    call notdead@plt
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    mv a0, s1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, s0, -32
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i32
   %2 = alloca i8, i32 %1
   call void @notdead(ptr %2)
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }
 

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    srliw a0, a0, 3
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 3
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld a0, 0(a0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load i32, ptr %va, align 4
   %1 = add i32 %argp.cur, 7
   %2 = and i32 %1, -8
   %argp.cur.aligned = inttoptr i32 %1 to ptr
   %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
   store ptr %argp.next, ptr %va, align 4
   %3 = inttoptr i32 %2 to ptr

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 16(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, double
   call void @llvm.va_end(ptr %va)
   %2 = bitcast double %1 to i64
   ret i64 %2
 }
 
 define void @va2_caller() nounwind {

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    srliw a0, a0, 3
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 3
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld a0, 0(a0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a0, a1, a0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 80
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load i32, ptr %va, align 4
   %1 = add i32 %argp.cur, 7
   %2 = and i32 %1, -8
   %argp.cur.aligned = inttoptr i32 %1 to ptr
   %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8
   store ptr %argp.next, ptr %va, align 4
   %3 = inttoptr i32 %2 to ptr

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 0(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a3, s0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a0, a1, a2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a3, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 80
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, double
   call void @llvm.va_end(ptr %va)
   %2 = bitcast double %1 to i64
   %3 = add i64 %b, %2
   ret i64 %3
 }
 

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a1, a1, s1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add a1, a1, a2
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addw a0, a1, a0
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 112
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %vargs = alloca ptr, align 4
-  %wargs = alloca ptr, align 4
+  %vargs = alloca ptr
+  %wargs = alloca ptr
   call void @llvm.va_start(ptr %vargs)
   %1 = va_arg ptr %vargs, i32
   call void @llvm.va_copy(ptr %wargs, ptr %vargs)
   %2 = load ptr, ptr %wargs, align 4
   call void @notdead(ptr %2)
   %3 = va_arg ptr %vargs, i32
   %4 = va_arg ptr %vargs, i32
   %5 = va_arg ptr %vargs, i32

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, 0(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, s0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 96
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %1 = va_arg ptr %va, i32
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }
 
 ; TODO: improve constant materialization of stack addresses
 

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a1, 24414
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a1, a1, -1680
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    add sp, sp, a1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld ra, 1960(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ld s0, 1952(sp) # 8-byte Folded Reload
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi sp, sp, 2032
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    ret
   %large = alloca [ 100000000 x i8 ]
-  %va = alloca ptr, align 4
+  %va = alloca ptr
   call void @llvm.va_start(ptr %va)
   %argp.cur = load ptr, ptr %va, align 4
   %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4
   store ptr %argp.next, ptr %va, align 4
   %1 = load i32, ptr %argp.cur, align 4
   call void @llvm.va_end(ptr %va)
   ret i32 %1
 }

llvm/test/CodeGen/Thumb2/mve-stack.ll

 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    vstrw.32 q0, [sp, #8]
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #16
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [4 x i32], align 2
+  %d = alloca [4 x i32], align 4
   %g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2
   store <4 x i32> zeroinitializer, ptr %g, align 2
   call arm_aapcs_vfpcc void @func(ptr %d)
   ret void
 }
 
 define arm_aapcs_vfpcc void @vstrh16() {
 ; CHECK-LABEL: vstrh16:

 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    vstrh.16 q0, [sp, #2]
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #16
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [16 x i8], align 2
+  %d = alloca [16 x i8], align 4
   %g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2
   store <16 x i8> zeroinitializer, ptr %g, align 2
   call arm_aapcs_vfpcc void @func(ptr %d)
   ret void
 }
 
 define arm_aapcs_vfpcc void @vstrh32() {
 ; CHECK-LABEL: vstrh32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    vmov.i32 q0, #0x6
 ; CHECK-NEXT:    vstrh.32 q0, [r0, #4]
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [4 x i16], align 2
+  %d = alloca [4 x i16], align 4
   %g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2
   store <4 x i16> <i16 6, i16 6, i16 6, i16 6>, ptr %g, align 2
   call arm_aapcs_vfpcc void @func(ptr %d)
   ret void
 }
 
 define arm_aapcs_vfpcc void @vstrb32() {
 ; CHECK-LABEL: vstrb32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    add r0, sp, #4
 ; CHECK-NEXT:    vmov.i32 q0, #0x6
 ; CHECK-NEXT:    vstrb.32 q0, [r0, #2]
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [4 x i8], align 2
+  %d = alloca [4 x i8], align 4
   %g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2
   store <4 x i8> <i8 6, i8 6, i8 6, i8 6>, ptr %g, align 2
   call arm_aapcs_vfpcc void @func(ptr %d)
   ret void
 }
 
 define arm_aapcs_vfpcc void @vstrb16() {
 ; CHECK-LABEL: vstrb16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    vstrb.16 q0, [r0, #2]
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [8 x i8], align 2
+  %d = alloca [8 x i8], align 4
   %g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2
   store <8 x i8> zeroinitializer, ptr %g, align 2
   call arm_aapcs_vfpcc void @func(ptr %d)
   ret void
 }
 
 
 define arm_aapcs_vfpcc <4 x i32> @vldrw32() {
 ; CHECK-LABEL: vldrw32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    .pad #16
 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    vldrw.u32 q0, [sp, #8]
 ; CHECK-NEXT:    add sp, #16
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [4 x i32], align 2
+  %d = alloca [4 x i32], align 4
   call arm_aapcs_vfpcc void @func(ptr %d)
   %g = getelementptr inbounds [4 x i32], ptr %d, i32 0, i32 2
   %l = load <4 x i32>, ptr %g, align 2
   ret <4 x i32> %l
 }
 
 define arm_aapcs_vfpcc <8 x i16> @vldrh16() {
 ; CHECK-LABEL: vldrh16:

 ; CHECK-NEXT:    .pad #16
 ; CHECK-NEXT:    sub sp, #16
 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    vldrh.u16 q0, [sp, #2]
 ; CHECK-NEXT:    add sp, #16
 ; CHECK-NEXT:    pop {r7, pc}
 entry:
-  %d = alloca [16 x i8], align 2
+  %d = alloca [16 x i8], align 4
   call arm_aapcs_vfpcc void @func(ptr %d)
   %g = getelementptr inbounds [16 x i8], ptr %d, i32 0, i32 2
   %l = load <16 x i8>, ptr %g, align 2
   ret <16 x i8> %l
 }
 
 define arm_aapcs_vfpcc <4 x i16> @vldrh32() {
 ; CHECK-LABEL: vldrh32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    mov r4, sp
 ; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    vldrh.u32 q0, [r4, #4]
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
-  %d = alloca [4 x i16], align 2
+  %d = alloca [4 x i16], align 4
   call arm_aapcs_vfpcc void @func(ptr %d)
   %g = getelementptr inbounds [4 x i16], ptr %d, i32 0, i32 2
   %l = load <4 x i16>, ptr %g, align 2
   ret <4 x i16> %l
 }
 
 define arm_aapcs_vfpcc <4 x i8> @vldrb32() {
 ; CHECK-LABEL: vldrb32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    add r4, sp, #4
 ; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    vldrb.u32 q0, [r4, #2]
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
-  %d = alloca [4 x i8], align 2
+  %d = alloca [4 x i8], align 4
   call arm_aapcs_vfpcc void @func(ptr %d)
   %g = getelementptr inbounds [4 x i8], ptr %d, i32 0, i32 2
   %l = load <4 x i8>, ptr %g, align 2
   ret <4 x i8> %l
 }
 
 define arm_aapcs_vfpcc <8 x i8> @vldrb16() {
 ; CHECK-LABEL: vldrb16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    .pad #8
 ; CHECK-NEXT:    sub sp, #8
 ; CHECK-NEXT:    mov r4, sp
 ; CHECK-NEXT:    mov r0, r4
 ; CHECK-NEXT:    bl func
 ; CHECK-NEXT:    vldrb.u16 q0, [r4, #2]
 ; CHECK-NEXT:    add sp, #8
 ; CHECK-NEXT:    pop {r4, pc}
 entry:
-  %d = alloca [8 x i8], align 2
+  %d = alloca [8 x i8], align 4
   call arm_aapcs_vfpcc void @func(ptr %d)
   %g = getelementptr inbounds [8 x i8], ptr %d, i32 0, i32 2
   %l = load <8 x i8>, ptr %g, align 2
   ret <8 x i8> %l
 }
 
 declare dso_local arm_aapcs_vfpcc void @func(...)

llvm/test/CodeGen/VE/Scalar/atomic_cmp_swap.ll

 ; CHECK-NEXT:    brne.w 0, %s2, .LBB33_2
 ; CHECK-NEXT:  # %bb.1: # %bb7
 ; CHECK-NEXT:    st1b %s1, (, %s0)
 ; CHECK-NEXT:  .LBB33_2: # %bb9
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic", align 1
+  %i = alloca %"struct.std::__1::atomic", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %i)
   %i3 = zext i1 %arg1 to i8
   %i4 = load i8, ptr %arg, align 1
   %i5 = cmpxchg weak volatile ptr %i, i8 %i4, i8 %i3 monotonic monotonic, align 1
   %i6 = extractvalue { i8, i1 } %i5, 1
   br i1 %i6, label %bb9, label %bb7
 
 bb7:                                              ; preds = %bb

 ; CHECK-NEXT:    brne.w 0, %s2, .LBB34_2
 ; CHECK-NEXT:  # %bb.1: # %bb6
 ; CHECK-NEXT:    st1b %s1, (, %s0)
 ; CHECK-NEXT:  .LBB34_2: # %bb8
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic.0", align 1
+  %i = alloca %"struct.std::__1::atomic.0", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %i)
   %i3 = load i8, ptr %arg, align 1
   %i4 = cmpxchg weak volatile ptr %i, i8 %i3, i8 %arg1 monotonic monotonic, align 1
   %i5 = extractvalue { i8, i1 } %i4, 1
   br i1 %i5, label %bb8, label %bb6
 
 bb6:                                              ; preds = %bb
   %i7 = extractvalue { i8, i1 } %i4, 0

 ; CHECK-NEXT:    brne.w 0, %s2, .LBB35_2
 ; CHECK-NEXT:  # %bb.1: # %bb6
 ; CHECK-NEXT:    st1b %s1, (, %s0)
 ; CHECK-NEXT:  .LBB35_2: # %bb8
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic.5", align 1
+  %i = alloca %"struct.std::__1::atomic.5", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %i)
   %i3 = load i8, ptr %arg, align 1
   %i4 = cmpxchg weak volatile ptr %i, i8 %i3, i8 %arg1 monotonic monotonic, align 1
   %i5 = extractvalue { i8, i1 } %i4, 1
   br i1 %i5, label %bb8, label %bb6
 
 bb6:                                              ; preds = %bb
   %i7 = extractvalue { i8, i1 } %i4, 0

 ; CHECK-NEXT:    brne.w 0, %s2, .LBB36_2
 ; CHECK-NEXT:  # %bb.1: # %bb7
 ; CHECK-NEXT:    st2b %s1, (, %s0)
 ; CHECK-NEXT:  .LBB36_2: # %bb9
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic.10", align 2
+  %i = alloca %"struct.std::__1::atomic.10", align 8
   call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %i)
   %i4 = load i16, ptr %arg, align 2
   %i5 = cmpxchg weak volatile ptr %i, i16 %i4, i16 %arg1 monotonic monotonic, align 2
   %i6 = extractvalue { i16, i1 } %i5, 1
   br i1 %i6, label %bb9, label %bb7
 
 bb7:                                              ; preds = %bb
   %i8 = extractvalue { i16, i1 } %i5, 0

 ; CHECK-NEXT:    brne.w 0, %s2, .LBB37_2
 ; CHECK-NEXT:  # %bb.1: # %bb7
 ; CHECK-NEXT:    st2b %s1, (, %s0)
 ; CHECK-NEXT:  .LBB37_2: # %bb9
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic.15", align 2
+  %i = alloca %"struct.std::__1::atomic.15", align 8
   call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %i)
   %i4 = load i16, ptr %arg, align 2
   %i5 = cmpxchg weak volatile ptr %i, i16 %i4, i16 %arg1 monotonic monotonic, align 2
   %i6 = extractvalue { i16, i1 } %i5, 1
   br i1 %i6, label %bb9, label %bb7
 
 bb7:                                              ; preds = %bb
   %i8 = extractvalue { i16, i1 } %i5, 0

 ; CHECK-NEXT:    breq.w %s1, %s3, .LBB38_2
 ; CHECK-NEXT:  # %bb.1: # %bb7
 ; CHECK-NEXT:    stl %s1, (, %s0)
 ; CHECK-NEXT:  .LBB38_2: # %bb9
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic.20", align 4
+  %i = alloca %"struct.std::__1::atomic.20", align 8
   call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %i)
   %i4 = load i32, ptr %arg, align 4
   %i5 = cmpxchg weak volatile ptr %i, i32 %i4, i32 %arg1 monotonic monotonic, align 4
   %i6 = extractvalue { i32, i1 } %i5, 1
   br i1 %i6, label %bb9, label %bb7
 
 bb7:                                              ; preds = %bb
   %i8 = extractvalue { i32, i1 } %i5, 0

 ; CHECK-NEXT:    breq.w %s1, %s3, .LBB39_2
 ; CHECK-NEXT:  # %bb.1: # %bb7
 ; CHECK-NEXT:    stl %s1, (, %s0)
 ; CHECK-NEXT:  .LBB39_2: # %bb9
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
 bb:
-  %i = alloca %"struct.std::__1::atomic.25", align 4
+  %i = alloca %"struct.std::__1::atomic.25", align 8
   call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %i)
   %i4 = load i32, ptr %arg, align 4
   %i5 = cmpxchg weak volatile ptr %i, i32 %i4, i32 %arg1 monotonic monotonic, align 4
   %i6 = extractvalue { i32, i1 } %i5, 1
   br i1 %i6, label %bb9, label %bb7
 
 bb7:                                              ; preds = %bb
   %i8 = extractvalue { i32, i1 } %i5, 0

llvm/test/CodeGen/VE/Scalar/atomic_load.ll

 ; CHECK-NEXT:    lea %s0, _Z6fun_i1RNSt3__16atomicIbEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z6fun_i1RNSt3__16atomicIbEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld1b.zx %s0, 248(, %s11)
 ; CHECK-NEXT:    and %s0, 1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic", align 1
+  %1 = alloca %"struct.std::__1::atomic", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
   call void @_Z6fun_i1RNSt3__16atomicIbEE(ptr nonnull align 1 dereferenceable(1) %1)
   %2 = load atomic i8, ptr %1 monotonic, align 1
   %3 = and i8 %2, 1
   %4 = icmp ne i8 %3, 0
   call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
   ret i1 %4
 }

 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, _Z6fun_i8RNSt3__16atomicIcEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z6fun_i8RNSt3__16atomicIcEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld1b.sx %s0, 248(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic.0", align 1
+  %1 = alloca %"struct.std::__1::atomic.0", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
   call void @_Z6fun_i8RNSt3__16atomicIcEE(ptr nonnull align 1 dereferenceable(1) %1)
   %2 = load atomic i8, ptr %1 monotonic, align 1
   call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
   ret i8 %2
 }
 
 declare void @_Z6fun_i8RNSt3__16atomicIcEE(ptr nonnull align 1 dereferenceable(1))
 
 ; Function Attrs: mustprogress
 define zeroext i8 @_Z26atomic_load_relaxed_stk_u8v() {
 ; CHECK-LABEL: _Z26atomic_load_relaxed_stk_u8v:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, _Z6fun_u8RNSt3__16atomicIhEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z6fun_u8RNSt3__16atomicIhEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld1b.zx %s0, 248(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic.5", align 1
+  %1 = alloca %"struct.std::__1::atomic.5", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1)
   call void @_Z6fun_u8RNSt3__16atomicIhEE(ptr nonnull align 1 dereferenceable(1) %1)
   %2 = load atomic i8, ptr %1 monotonic, align 1
   call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1)
   ret i8 %2
 }
 
 declare void @_Z6fun_u8RNSt3__16atomicIhEE(ptr nonnull align 1 dereferenceable(1))
 
 ; Function Attrs: mustprogress
 define signext i16 @_Z27atomic_load_relaxed_stk_i16v() {
 ; CHECK-LABEL: _Z27atomic_load_relaxed_stk_i16v:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, _Z7fun_i16RNSt3__16atomicIsEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z7fun_i16RNSt3__16atomicIsEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld2b.sx %s0, 248(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic.10", align 2
+  %1 = alloca %"struct.std::__1::atomic.10", align 8
   call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %1)
   call void @_Z7fun_i16RNSt3__16atomicIsEE(ptr nonnull align 2 dereferenceable(2) %1)
   %2 = load atomic i16, ptr %1 monotonic, align 2
   call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %1)
   ret i16 %2
 }
 
 declare void @_Z7fun_i16RNSt3__16atomicIsEE(ptr nonnull align 2 dereferenceable(2))
 
 ; Function Attrs: mustprogress
 define zeroext i16 @_Z27atomic_load_relaxed_stk_u16v() {
 ; CHECK-LABEL: _Z27atomic_load_relaxed_stk_u16v:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, _Z7fun_u16RNSt3__16atomicItEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z7fun_u16RNSt3__16atomicItEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld2b.zx %s0, 248(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic.15", align 2
+  %1 = alloca %"struct.std::__1::atomic.15", align 8
   call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %1)
   call void @_Z7fun_u16RNSt3__16atomicItEE(ptr nonnull align 2 dereferenceable(2) %1)
   %2 = load atomic i16, ptr %1 monotonic, align 2
   call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %1)
   ret i16 %2
 }
 
 declare void @_Z7fun_u16RNSt3__16atomicItEE(ptr nonnull align 2 dereferenceable(2))
 
 ; Function Attrs: mustprogress
 define signext i32 @_Z27atomic_load_relaxed_stk_i32v() {
 ; CHECK-LABEL: _Z27atomic_load_relaxed_stk_i32v:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, _Z7fun_i32RNSt3__16atomicIiEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z7fun_i32RNSt3__16atomicIiEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ldl.sx %s0, 248(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic.20", align 4
+  %1 = alloca %"struct.std::__1::atomic.20", align 8
   call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1)
   call void @_Z7fun_i32RNSt3__16atomicIiEE(ptr nonnull align 4 dereferenceable(4) %1)
   %2 = load atomic i32, ptr %1 monotonic, align 4
   call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1)
   ret i32 %2
 }
 
 declare void @_Z7fun_i32RNSt3__16atomicIiEE(ptr nonnull align 4 dereferenceable(4))
 
 ; Function Attrs: mustprogress
 define zeroext i32 @_Z27atomic_load_relaxed_stk_u32v() {
 ; CHECK-LABEL: _Z27atomic_load_relaxed_stk_u32v:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, _Z7fun_u32RNSt3__16atomicIjEE@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, _Z7fun_u32RNSt3__16atomicIjEE@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, 248(, %s11)
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ldl.zx %s0, 248(, %s11)
 ; CHECK-NEXT:    or %s11, 0, %s9
-  %1 = alloca %"struct.std::__1::atomic.25", align 4
+  %1 = alloca %"struct.std::__1::atomic.25", align 8
   call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %1)
   call void @_Z7fun_u32RNSt3__16atomicIjEE(ptr nonnull align 4 dereferenceable(4) %1)
   %2 = load atomic i32, ptr %1 monotonic, align 4
   call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %1)
   ret i32 %2
 }
 
 declare void @_Z7fun_u32RNSt3__16atomicIjEE(ptr nonnull align 4 dereferenceable(4))

llvm/test/CodeGen/VE/Scalar/atomic_swap.ll

 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    or %s1, 1, (0)1
 ; CHECK-NEXT:    lea %s2, 8(, %s11)
 ; CHECK-NEXT:    ts1am.w %s0, (%s2), %s1
 ; CHECK-NEXT:    and %s0, 1, %s0
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic", align 1
+  %2 = alloca %"struct.std::__1::atomic", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
   %3 = zext i1 %0 to i8
   %4 = atomicrmw volatile xchg ptr %2, i8 %3 monotonic
   %5 = and i8 %4, 1
   %6 = icmp ne i8 %5, 0
   call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
   ret i1 %6
 }

 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    or %s1, 1, (0)1
 ; CHECK-NEXT:    lea %s2, 8(, %s11)
 ; CHECK-NEXT:    ts1am.w %s0, (%s2), %s1
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic.0", align 1
+  %2 = alloca %"struct.std::__1::atomic.0", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
   %3 = atomicrmw volatile xchg ptr %2, i8 %0 monotonic
   call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
   ret i8 %3
 }
 
 ; Function Attrs: nofree nounwind mustprogress
 define zeroext i8 @_Z26atomic_swap_relaxed_stk_u8h(i8 zeroext %0) {
 ; CHECK-LABEL: _Z26atomic_swap_relaxed_stk_u8h:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    or %s1, 1, (0)1
 ; CHECK-NEXT:    lea %s2, 8(, %s11)
 ; CHECK-NEXT:    ts1am.w %s0, (%s2), %s1
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic.5", align 1
+  %2 = alloca %"struct.std::__1::atomic.5", align 8
   call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %2)
   %3 = atomicrmw volatile xchg ptr %2, i8 %0 monotonic
   call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %2)
   ret i8 %3
 }
 
 ; Function Attrs: nofree nounwind mustprogress
 define signext i16 @_Z27atomic_swap_relaxed_stk_i16s(i16 signext %0) {
 ; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i16s:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    or %s1, 3, (0)1
 ; CHECK-NEXT:    lea %s2, 8(, %s11)
 ; CHECK-NEXT:    ts1am.w %s0, (%s2), %s1
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic.10", align 2
+  %2 = alloca %"struct.std::__1::atomic.10", align 8
   call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %2)
   %3 = atomicrmw volatile xchg ptr %2, i16 %0 monotonic
   call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %2)
   ret i16 %3
 }
 
 ; Function Attrs: nofree nounwind mustprogress
 define zeroext i16 @_Z27atomic_swap_relaxed_stk_u16t(i16 zeroext %0) {
 ; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u16t:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    or %s1, 3, (0)1
 ; CHECK-NEXT:    lea %s2, 8(, %s11)
 ; CHECK-NEXT:    ts1am.w %s0, (%s2), %s1
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic.15", align 2
+  %2 = alloca %"struct.std::__1::atomic.15", align 8
   call void @llvm.lifetime.start.p0(i64 2, ptr nonnull %2)
   %3 = atomicrmw volatile xchg ptr %2, i16 %0 monotonic
   call void @llvm.lifetime.end.p0(i64 2, ptr nonnull %2)
   ret i16 %3
 }
 
 ; Function Attrs: nofree nounwind mustprogress
 define signext i32 @_Z27atomic_swap_relaxed_stk_i32i(i32 signext %0) {
 ; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_i32i:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    ts1am.w %s0, 8(%s11), 15
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic.20", align 4
+  %2 = alloca %"struct.std::__1::atomic.20", align 8
   call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
   %3 = atomicrmw volatile xchg ptr %2, i32 %0 monotonic
   call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
   ret i32 %3
 }
 
 ; Function Attrs: nofree nounwind mustprogress
 define zeroext i32 @_Z27atomic_swap_relaxed_stk_u32j(i32 zeroext %0) {
 ; CHECK-LABEL: _Z27atomic_swap_relaxed_stk_u32j:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    ts1am.w %s0, 8(%s11), 15
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.l %s11, 16, %s11
 ; CHECK-NEXT:    b.l.t (, %s10)
-  %2 = alloca %"struct.std::__1::atomic.25", align 4
+  %2 = alloca %"struct.std::__1::atomic.25", align 8
   call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %2)
   %3 = atomicrmw volatile xchg ptr %2, i32 %0 monotonic
   call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %2)
   ret i32 %3
 }
 
 ; Function Attrs: nofree nounwind mustprogress
 define i64 @_Z27atomic_swap_relaxed_stk_i64l(i64 %0) {

llvm/test/CodeGen/WebAssembly/PR40172.ll

 
 ; CHECK:  i32.sub $[[BASE:[0-9]+]]=,
 ; CHECK:  local.copy $[[ARG:[0-9]+]]=, $0{{$}}
 ; CHECK:  i32.const $[[A0:[0-9]+]]=, 1{{$}}
 ; CHECK:  i32.and $[[A1:[0-9]+]]=, $[[ARG]], $[[A0]]{{$}}
 ; CHECK:  i32.store8 8($[[BASE]]), $[[A1]]{{$}}
 
 define void @test(i8 %byte) {
-  %t = alloca { i8, i8 }, align 1
+  %t = alloca { i8, i8 }, align 8
   %x4 = and i8 %byte, 1
   %x5 = icmp eq i8 %x4, 1
   %x6 = and i8 %byte, 2
   %x7 = icmp eq i8 %x6, 2
   %x9 = zext i1 %x5 to i8
   store i8 %x9, ptr %t, align 1
   %x10 = getelementptr inbounds { i8, i8 }, ptr %t, i32 0, i32 1
   %x11 = zext i1 %x7 to i8
   store i8 %x11, ptr %x10, align 1
   ret void
 }

llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll

 
 @.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
 @.str.1 = private unnamed_addr constant [2 x i8] c"+\00", align 1
 @.str.2 = private unnamed_addr constant [2 x i8] c"-\00", align 1
 
 ; Function Attrs: uwtable
 define void @_Z3barii(i32 %param1, i32 %param2) #0 !dbg !24 {
 entry:
-  %var1 = alloca %struct.AAA3, align 1
-  %var2 = alloca %struct.AAA3, align 1
+  %var1 = alloca %struct.AAA3, align 8
+  %var2 = alloca %struct.AAA3, align 8
   tail call void @llvm.dbg.value(metadata i32 %param1, i64 0, metadata !29, metadata !46), !dbg !47
   tail call void @llvm.dbg.value(metadata i32 %param2, i64 0, metadata !30, metadata !46), !dbg !48
   tail call void @llvm.dbg.value(metadata ptr null, i64 0, metadata !31, metadata !46), !dbg !49
   %tobool = icmp eq i32 %param2, 0, !dbg !50
   br i1 %tobool, label %if.end, label %if.then, !dbg !52
 
 if.then:                                          ; preds = %entry
   %call = tail call ptr @_Z5i2stri(i32 %param2), !dbg !53

llvm/test/CodeGen/X86/fast-isel-call.ll

 ; CHECK:   movl $100, 8(%esp)
 ; CHECK:   calll {{.*}}memcpy
 }
 
 ; STDERR-NOT: FastISel missed call:   call x86_thiscallcc void @thiscallfun
 %struct.S = type { i8 }
 define void @test5() {
 entry:
-  %s = alloca %struct.S, align 1
+  %s = alloca %struct.S, align 8
 ; CHECK-LABEL: test5:
 ; CHECK: subl $12, %esp
 ; CHECK: leal 8(%esp), %ecx
 ; CHECK: movl $43, (%esp)
 ; CHECK: calll {{.*}}thiscallfun
 ; CHECK: addl $8, %esp
   call x86_thiscallcc void @thiscallfun(ptr %s, i32 43)
   ret void

llvm/test/CodeGen/X86/load-local-v3i129.ll

 ; SLOW-SHLD-NEXT:    movq -40(%rsp), %rax
 ; SLOW-SHLD-NEXT:    andq $-4, %rax
 ; SLOW-SHLD-NEXT:    orq $1, %rax
 ; SLOW-SHLD-NEXT:    movq %rax, -40(%rsp)
 ; SLOW-SHLD-NEXT:    orq $-2, -56(%rsp)
 ; SLOW-SHLD-NEXT:    movq $-1, -48(%rsp)
 ; SLOW-SHLD-NEXT:    retq
 Entry:
-  %y = alloca <3 x i129>, align 4
+  %y = alloca <3 x i129>, align 16
   %L = load <3 x i129>, ptr %y
   %I1 = insertelement <3 x i129> %L, i129 340282366920938463463374607431768211455, i32 1
   store <3 x i129> %I1, ptr %y
   ret void
 }

llvm/test/CodeGen/X86/pr44140.ll

 ; CHECK-NEXT:    addq $584, %rsp # imm = 0x248
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 start:
   %dummy0 = alloca [22 x i64], align 8
   %dummy1 = alloca [22 x i64], align 8
   %dummy2 = alloca [22 x i64], align 8
 
-  %data = alloca <2 x i64>, align 8
+  %data = alloca <2 x i64>, align 16
 
   br label %fake-loop
 
 fake-loop:                                        ; preds = %fake-loop, %start
   %dummy0.cast = bitcast [22 x i64]* %dummy0 to i8*
   %dummy1.cast = bitcast [22 x i64]* %dummy1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 8 %dummy1.cast, i8* nonnull align 8 %dummy0.cast, i64 176, i1 false)
 

llvm/test/CodeGen/X86/ssp-data-layout.ll

 
 ; CHECK: call{{l|q}} get_struct_small_nonchar
 ; CHECK: movw %ax, -128(
 ; CHECK: call{{l|q}} end_struct_small_nonchar
   %x = alloca i32, align 4
   %y = alloca i32, align 4
   %z = alloca i32, align 4
   %ptr = alloca i32, align 4
-  %small2 = alloca [2 x i16], align 2
+  %small2 = alloca [2 x i16], align 4
   %large2 = alloca [8 x i32], align 16
-  %small = alloca [2 x i8], align 1
-  %large = alloca [8 x i8], align 1
-  %a = alloca %struct.struct_large_char, align 1
-  %b = alloca %struct.struct_small_char, align 1
+  %small = alloca [2 x i8], align 2
+  %large = alloca [8 x i8], align 8
+  %a = alloca %struct.struct_large_char, align 8
+  %b = alloca %struct.struct_small_char, align 8
   %c = alloca %struct.struct_large_nonchar, align 8
-  %d = alloca %struct.struct_small_nonchar, align 2
+  %d = alloca %struct.struct_small_nonchar, align 8
   %call = call i32 @get_scalar1()
   store i32 %call, ptr %x, align 4
   call void @end_scalar1()
   %call1 = call i32 @get_scalar2()
   store i32 %call1, ptr %y, align 4
   call void @end_scalar2()
   %call2 = call i32 @get_scalar3()
   store i32 %call2, ptr %z, align 4

 ; CHECK: movw %ax, -112(
 ; CHECK: call{{l|q}} end_struct_small_nonchar
   %x = alloca i32, align 4
   %y = alloca i32, align 4
   %z = alloca i32, align 4
   %ptr = alloca i32, align 4
   %small2 = alloca [2 x i16], align 2
   %large2 = alloca [8 x i32], align 16
-  %small = alloca [2 x i8], align 1
-  %large = alloca [8 x i8], align 1
-  %a = alloca %struct.struct_large_char, align 1
-  %b = alloca %struct.struct_small_char, align 1
+  %small = alloca [2 x i8], align 2
+  %large = alloca [8 x i8], align 8
+  %a = alloca %struct.struct_large_char, align 8
+  %b = alloca %struct.struct_small_char, align 8
   %c = alloca %struct.struct_large_nonchar, align 8
-  %d = alloca %struct.struct_small_nonchar, align 2
+  %d = alloca %struct.struct_small_nonchar, align 8
   %call = call i32 @get_scalar1()
   store i32 %call, ptr %x, align 4
   call void @end_scalar1()
   %call1 = call i32 @get_scalar2()
   store i32 %call1, ptr %y, align 4
   call void @end_scalar2()
   %call2 = call i32 @get_scalar3()
   store i32 %call2, ptr %z, align 4

 
 ; CHECK: call{{l|q}} get_struct_small_nonchar
 ; CHECK: movw %ax, -112(
 ; CHECK: call{{l|q}} end_struct_small_nonchar
   %x = alloca i32, align 4
   %y = alloca i32, align 4
   %z = alloca i32, align 4
   %ptr = alloca i32, align 4
-  %small2 = alloca [2 x i16], align 2
+  %small2 = alloca [2 x i16], align 4
   %large2 = alloca [8 x i32], align 16
-  %small = alloca [2 x i8], align 1
-  %large = alloca [8 x i8], align 1
-  %a = alloca %struct.struct_large_char, align 1
-  %b = alloca %struct.struct_small_char, align 1
+  %small = alloca [2 x i8], align 2
+  %large = alloca [8 x i8], align 8
+  %a = alloca %struct.struct_large_char, align 8
+  %b = alloca %struct.struct_small_char, align 8
   %c = alloca %struct.struct_large_nonchar, align 8
-  %d = alloca %struct.struct_small_nonchar, align 2
+  %d = alloca %struct.struct_small_nonchar, align 8
   %call = call i32 @get_scalar1()
   store i32 %call, ptr %x, align 4
   call void @end_scalar1()
   %call1 = call i32 @get_scalar2()
   store i32 %call1, ptr %y, align 4
   call void @end_scalar2()
   %call2 = call i32 @get_scalar3()
   store i32 %call2, ptr %z, align 4

llvm/test/CodeGen/X86/win-cleanuppad.ll

 
 declare i32 @__CxxFrameHandler3(...)
 
 ; Function Attrs: nounwind
 declare x86_thiscallcc void @"\01??1Dtor@@QAE@XZ"(ptr) #1
 
 define void @nested_cleanup() #0 personality ptr @__CxxFrameHandler3 {
 entry:
-  %o1 = alloca %struct.Dtor, align 1
-  %o2 = alloca %struct.Dtor, align 1
+  %o1 = alloca %struct.Dtor, align 8
+  %o2 = alloca %struct.Dtor, align 8
   invoke void @f(i32 1)
           to label %invoke.cont unwind label %cleanup.outer
 
 invoke.cont:                                      ; preds = %entry
   invoke void @f(i32 2)
           to label %invoke.cont.1 unwind label %cleanup.inner
 
 invoke.cont.1:                                    ; preds = %invoke.cont

llvm/test/CodeGen/X86/x86-mixed-alignment-dagcombine.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -mtriple=x86_64-apple-macosx10.9.0  -mcpu=core2 -mattr=+64bit,+sse2 < %s | FileCheck %s
 
 ; DAGCombine may choose to rewrite 2 loads feeding a select as a select of
 ; addresses feeding a load. This test ensures that when it does that it creates
 ; a load with alignment equivalent to the most restrictive source load.
 
 declare void @sink(<2 x double>)
 
 define void @test1(i1 %cmp) align 2 {
 ; CHECK-LABEL: test1:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    subq $40, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT:    movq %rsp, %rcx
+; CHECK-NEXT:    movq %rsp, %rax
+; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-NEXT:    cmovneq %rax, %rcx
 ; CHECK-NEXT:    movups (%rcx), %xmm0
 ; CHECK-NEXT:    callq _sink
 ; CHECK-NEXT:    addq $40, %rsp
 ; CHECK-NEXT:    retq
   %1 = alloca  <2 x double>, align 16
   %2 = alloca  <2 x double>, align 8
 
   %val = load <2 x double>, ptr %1, align 16
   %val2 = load <2 x double>, ptr %2, align 8
   %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
   call void @sink(<2 x double> %val3)
   ret void
 }
 
 define void @test2(i1 %cmp) align 2 {
 ; CHECK-LABEL: test2:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    subq $40, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
-; CHECK-NEXT:    movq %rsp, %rcx
+; CHECK-NEXT:    movq %rsp, %rax
+; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-NEXT:    cmovneq %rax, %rcx
 ; CHECK-NEXT:    movaps (%rcx), %xmm0
 ; CHECK-NEXT:    callq _sink
 ; CHECK-NEXT:    addq $40, %rsp
 ; CHECK-NEXT:    retq
   %1 = alloca  <2 x double>, align 16
   %2 = alloca  <2 x double>, align 8
 
   %val = load <2 x double>, ptr %1, align 16
   %val2 = load <2 x double>, ptr %2, align 16
   %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
   call void @sink(<2 x double> %val3)
   ret void
 }

llvm/test/DebugInfo/AArch64/frameindices.ll

entry:
   call void @_Z2f91A(%struct.A* %agg.tmp.i), !dbg !65
   call void @llvm.lifetime.end(i64 24, i8* %1), !dbg !66
   ret void, !dbg !67
 }
 
 define void @_Z3f16v() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg !68 {
 entry:
   %agg.tmp.i.i = alloca %struct.A, align 8
-  %d = alloca %struct.B, align 1
+  %d = alloca %struct.B, align 8
   %agg.tmp.sroa.2 = alloca [15 x i8], align 1
   %agg.tmp.sroa.4 = alloca [7 x i8], align 1
   tail call void @llvm.dbg.declare(metadata [15 x i8]* %agg.tmp.sroa.2, metadata !56, metadata !74), !dbg !75
   tail call void @llvm.dbg.declare(metadata [7 x i8]* %agg.tmp.sroa.4, metadata !56, metadata !77), !dbg !75
   tail call void @llvm.dbg.declare(metadata %struct.A* undef, metadata !72, metadata !37), !dbg !78
   %0 = load i64, i64* @a, align 8, !dbg !79, !tbaa !40
   tail call void @llvm.dbg.value(metadata %struct.B* %d, metadata !73, metadata !37), !dbg !80
   %call = call %struct.B* @_ZN1BC1El(%struct.B* %d, i64 %0), !dbg !80

llvm/test/DebugInfo/NVPTX/dbg-declare-alloca.ll

 ; CHECK-NEXT: .b8 0                                // End Of Children Mark
 ; CHECK-NEXT: }
 
 %struct.Foo = type { i32 }
 
 ; Function Attrs: noinline nounwind uwtable
 define void @use_dbg_declare() #0 !dbg !7 {
 entry:
-  %o = alloca %struct.Foo, align 4
+  %o = alloca %struct.Foo, align 8
   call void @llvm.dbg.declare(metadata ptr %o, metadata !10, metadata !15), !dbg !16
   call void @escape_foo(ptr %o), !dbg !17
   ret void, !dbg !18
 }
 
 ; Function Attrs: nounwind readnone speculatable
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 

llvm/test/DebugInfo/X86/dbg-addr.ll

 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64--linux"
 
 %struct.Foo = type { i32 }
 
 ; Function Attrs: noinline nounwind uwtable
 define void @use_dbg_addr() #0 !dbg !7 {
 entry:
-  %o = alloca %struct.Foo, align 4
+  %o = alloca %struct.Foo, align 8
   call void @llvm.dbg.addr(metadata ptr %o, metadata !10, metadata !15), !dbg !16
   call void @escape_foo(ptr %o), !dbg !17
   ret void, !dbg !18
 }
 
 define void @test_dbg_addr_and_dbg_val_undef() #0 !dbg !117 {
 entry:
-  %o = alloca %struct.Foo, align 4
+  %o = alloca %struct.Foo, align 8
   call void @llvm.dbg.addr(metadata ptr %o, metadata !1110, metadata !1115), !dbg !1116
   call void @escape_foo(ptr %o), !dbg !1117
   call void @llvm.dbg.value(metadata ptr undef, metadata !1110, metadata !1115), !dbg !1116
   ret void, !dbg !1118
 }
 
 ; Function Attrs: nounwind readnone speculatable
 declare void @llvm.dbg.addr(metadata, metadata, metadata) #1

llvm/test/DebugInfo/X86/dbg-declare-alloca.ll

 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64--linux"
 
 %struct.Foo = type { i32 }
 
 ; Function Attrs: noinline nounwind uwtable
 define void @use_dbg_declare() #0 !dbg !7 {
 entry:
-  %o = alloca %struct.Foo, align 4
+  %o = alloca %struct.Foo, align 8
   call void @llvm.dbg.declare(metadata ptr %o, metadata !10, metadata !15), !dbg !16
   call void @escape_foo(ptr %o), !dbg !17
   ret void, !dbg !18
 }
 
 ; Function Attrs: nounwind readnone speculatable
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 

llvm/test/DebugInfo/X86/sret.ll

entry:
   %0 = load i32, ptr %m_int, align 4, !dbg !88
   ret i32 %0, !dbg !88
 }
 
 ; Function Attrs: uwtable
 define void @_ZN1B9AInstanceEv(ptr noalias sret(%class.A) %agg.result, ptr %this) #2 align 2 !dbg !53 {
 entry:
   %this.addr = alloca ptr, align 8
-  %nrvo = alloca i1
+  %nrvo = alloca i1, align 1
   %cleanup.dest.slot = alloca i32
   store ptr %this, ptr %this.addr, align 8
   call void @llvm.dbg.declare(metadata ptr %this.addr, metadata !89, metadata !DIExpression()), !dbg !91
   %this1 = load ptr, ptr %this.addr
   store i1 false, ptr %nrvo, !dbg !92
   call void @llvm.dbg.declare(metadata ptr %agg.result, metadata !93, metadata !DIExpression()), !dbg !92
   call void @_ZN1AC1Ei(ptr %agg.result, i32 12), !dbg !92
   store i1 true, ptr %nrvo, !dbg !94

 }
 
 ; Function Attrs: uwtable
 define i32 @main(i32 %argc, ptr %argv) #2 personality ptr @__gxx_personality_v0 !dbg !54 {
 entry:
   %retval = alloca i32, align 4
   %argc.addr = alloca i32, align 4
   %argv.addr = alloca ptr, align 8
-  %b = alloca %class.B, align 1
+  %b = alloca %class.B, align 8
   %return_val = alloca i32, align 4
   %temp.lvalue = alloca %class.A, align 8
   %exn.slot = alloca ptr
   %ehselector.slot = alloca i32
   %a = alloca %class.A, align 8
   %cleanup.dest.slot = alloca i32
   store i32 0, ptr %retval
   store i32 %argc, ptr %argc.addr, align 4

 
 declare void @_ZSt9terminatev()
 
 ; Function Attrs: uwtable
 define linkonce_odr void @_ZN1AD0Ev(ptr %this) unnamed_addr #2 align 2 personality ptr @__gxx_personality_v0 !dbg !61 {
 entry:
   %this.addr = alloca ptr, align 8
   %exn.slot = alloca ptr
-  %ehselector.slot = alloca i32
+  %ehselector.slot = alloca i32, align 4
   store ptr %this, ptr %this.addr, align 8
   call void @llvm.dbg.declare(metadata ptr %this.addr, metadata !126, metadata !DIExpression()), !dbg !127
   %this1 = load ptr, ptr %this.addr
   invoke void @_ZN1AD2Ev(ptr %this1)
           to label %invoke.cont unwind label %lpad, !dbg !128
 
 invoke.cont:                                      ; preds = %entry
   call void @_ZdlPv(ptr %this1) #7, !dbg !129

llvm/test/DebugInfo/assignment-tracking/X86/nested-loop-frags.ll

 target triple = "x86_64-unknown-linux-gnu"
 
 @g_a = dso_local local_unnamed_addr global i32 0, align 4, !dbg !0
 @g_b = dso_local local_unnamed_addr global i32 0, align 4, !dbg !5
 @g_c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !8
 
 define dso_local noundef i32 @_Z3funii(i32 noundef %a, i32 noundef %b) local_unnamed_addr #0 !dbg !17 {
 entry:
-  %a.addr = alloca i64, align 4, !DIAssignID !58 ; VAR:a
+  %a.addr = alloca i64, align 8, !DIAssignID !58 ; VAR:a
   call void @llvm.dbg.assign(metadata i1 undef, metadata !21, metadata !DIExpression(), metadata !58, metadata ptr %a.addr, metadata !DIExpression()), !dbg !27 ; VAR:a
-  %b.addr = alloca i64, align 4, !DIAssignID !64 ; VAR:b
+  %b.addr = alloca i64, align 8, !DIAssignID !64 ; VAR:b
   call void @llvm.dbg.assign(metadata i1 undef, metadata !22, metadata !DIExpression(), metadata !64, metadata ptr %b.addr, metadata !DIExpression()), !dbg !27 ; VAR:b
-  %c.addr = alloca i64, align 4, !DIAssignID !68 ; VAR:c
+  %c.addr = alloca i64, align 8, !DIAssignID !68 ; VAR:c
   call void @llvm.dbg.assign(metadata i1 undef, metadata !67, metadata !DIExpression(), metadata !68, metadata ptr %c.addr, metadata !DIExpression()), !dbg !27 ; VAR:c
-  %d.addr = alloca i64, align 4, !DIAssignID !73 ; VAR:d
+  %d.addr = alloca i64, align 8, !DIAssignID !73 ; VAR:d
   call void @llvm.dbg.assign(metadata i1 undef, metadata !72, metadata !DIExpression(), metadata !73, metadata ptr %d.addr, metadata !DIExpression()), !dbg !27 ; VAR:d
-  %e.addr = alloca i64, align 4, !DIAssignID !76 ; VAR:e
+  %e.addr = alloca i64, align 8, !DIAssignID !76 ; VAR:e
   call void @llvm.dbg.assign(metadata i1 undef, metadata !75, metadata !DIExpression(), metadata !76, metadata ptr %e.addr, metadata !DIExpression()), !dbg !27 ; VAR:e
-  ;%f.addr = alloca i64, align 4, !DIAssignID !80 ; VAR:f
+  ;%f.addr = alloca i64, align 8, !DIAssignID !80 ; VAR:f
   ;call void @llvm.dbg.assign(metadata i1 undef, metadata !79, metadata !DIExpression(), metadata !80, metadata ptr %f.addr, metadata !DIExpression()), !dbg !27 ; VAR:f
   store i64 1, ptr %a.addr, !DIAssignID !70 ; VAR:a
   call void @llvm.dbg.assign(metadata i64 1, metadata !21, metadata !DIExpression(), metadata !70, metadata ptr %a.addr, metadata !DIExpression()), !dbg !27 ; VAR:a
   store i64 2, ptr %b.addr, !DIAssignID !71 ; VAR:b
   call void @llvm.dbg.assign(metadata i32 2, metadata !22, metadata !DIExpression(), metadata !71, metadata ptr %b.addr, metadata !DIExpression()), !dbg !27 ; VAR:b
   store i32 9, ptr %e.addr, !DIAssignID !78 ; VAR:e
   call void @llvm.dbg.assign(metadata i32 9, metadata !75, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 32), metadata !78, metadata ptr %e.addr, metadata !DIExpression()), !dbg !27 ; VAR:e
   store i32 3, ptr %a.addr, !DIAssignID !63 ; VAR:a