[RISCV] [1/2] Add intrinsic for Zbb extension

[LevyHsu]

Summary

Head files are included in the second patch in case the name needs to be changed.

RV32 / 64:
orc.b

__builtin_riscv_orc_b_32
__builtin_riscv_orc_b_64

_rv_orc_b
_rv32_orc_b
_rv64_orc_b

[craig.topper]

Please upload the patch using arcanist or using -U999999 when generating the diff.

[LevyHsu]

1. Generated with git format-patch -o patches/ -2 HEAD -U999999
2. clang/lib/Sema/SemaChecking.cpp
   • Rewrote CheckRISCVBuiltinFunctionCall
3. clang/lib/CodeGen/CGBuiltin.cpp
   • IntrinsicTypes = {ResultType};
4. llvm/include/llvm/IR/IntrinsicsRISCV.td
   • The second llvm_any_ty has been changed to LLVMMatchType<0>
5. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
   • ANY_EXTEND both op0 and op 0 then truncate back to i32 when orc32b under RV64
6. llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
   • Added corresponding testcases.

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

21

Can we select between the 32 and 64 bit version in the header based on __riscv_xlen so we only need 2 builtins, rather than 3?

22

All RISCV builtins should start with "__builtin_riscv_". I don't think we should use riscv32/riscv64 here. Especially since the 32-bit version is available on RV64. So I think these should be named

builtin_riscv_orc_b_32 and builtin_riscv_orc_b_64.

23

Ideally this would be "experimental-zbb,64bit" but I'm not sure that the frontend knows about "64bit".

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4205

"LHS" stands for "left hand side", but operand 0 is the intrinsic ID which should already be i64. Only operand 1 needs to be extended. So just do

SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
SDValue Res = DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), NewOp1);

[LevyHsu]

1. llvm/lib/Target/RISCV/RISCVISelLowering.cpp
   • Fixed mishandling on op0
2. clang/include/clang/Basic/BuiltinsRISCV.def clang/lib/CodeGen/CGBuiltin.cpp
   • Reduce port to 2 versions for 32/64 only.
3. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
   • Remove extra tests

[craig.topper]

clang/lib/Sema/SemaChecking.cpp

3418

LLVM coding style does not allow _ in variable names.

3427

Drop the else. Since the if has a continue, control flow won't reach here if the 'if' is true.

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

26

Why _2?

[LevyHsu]

1. clang/lib/Sema/SemaChecking.cpp
   • Fixed var name & loop
2. clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
   • renamed function

[craig.topper]

I think this looks good to me. Anyone else have any comments?

[Jim]

llvm/include/llvm/IR/IntrinsicsRISCV.td

26

How about put it between Atomics and Vector to follow canonical order?

[asb]

Can I just check the reasoning on the naming? I see that the bitmanip 0.93 spec proposes _{rv,rv32,rv64}_{opname} intrinsics. Does the __builtin__{riscv,riscv32,riscv64}_opname format match what GCC are doing / planning to do here? Precedent for RVV, for other archs, or something else?

Just trying to determine to what these names are an open item of discussion vs matching something else.

EDIT: I see Craig commented on this point in https://reviews.llvm.org/D99009#2660456

[craig.topper]

In D99320#2661285, @asb wrote:

Can I just check the reasoning on the naming? I see that the bitmanip 0.93 spec proposes _{rv,rv32,rv64}_{opname} intrinsics. Does the __builtin__{riscv,riscv32,riscv64}_opname format match what GCC are doing / planning to do here? Precedent for RVV, for other archs, or something else?

Just trying to determine to what these names are an open item of discussion vs matching something else.

EDIT: I see Craig commented on this point in https://reviews.llvm.org/D99009#2660456

Yeah the big open for naming is the name of the intrinsic header. Whether it should be rvintrin.h or riscv_intrinsic.h.

The builtins in this patch are

builtin_riscv_orc_b_32
builtin_riscv_orc_b_64

I've update the description summary to reflect this since it change during development.

The Zbr patch uses the following without a 32/64 suffix.
__builtin_riscv_crc32_b/w/d/q

There's a difference because orc.b needs to be available for 32-bit on RV32 and RV64 per the spec so we have two builtins. crc32.b intrinsics in the spec are defined only for xlen so we have a single builtin.

@kito-cheng do you know how gcc will name builtins?

[kito-cheng]

Created an issue for continue discuses on riscv-c-api-doc
https://github.com/riscv/riscv-c-api-doc/issues/19

[craig.topper]

I'm going to approve this. If we need to change the builtin names in the future that's easy enough to do.

clang/include/clang/Basic/BuiltinsRISCV.def

 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+// Zbb extension
+TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
+TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb")
+
 // Zbr extension
 TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
 TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Basic/DiagnosticSemaKinds.td

 def err_tcb_conflicting_attributes : Error<
   "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
 def warn_tcb_enforcement_violation : Warning<
   "calling %0 is a violation of trusted computing base '%1'">,
   InGroup<DiagGroup<"tcb-enforcement">>;
 
 // RISC-V builtin required extension warning
 def err_riscv_builtin_requires_extension : Error<
-  "builtin requires %0 extension support to be enabled">;
+  "builtin requires '%0' extension support to be enabled">;
 } // end of sema component.

clang/lib/CodeGen/CGBuiltin.cpp

Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
 
+  // Zbb
+  case RISCV::BI__builtin_riscv_orc_b_32:
+  case RISCV::BI__builtin_riscv_orc_b_64:
+    ID = Intrinsic::riscv_orc_b;
+    IntrinsicTypes = {ResultType};
+    break;
+
   // Zbr
   case RISCV::BI__builtin_riscv_crc32_b:
     ID = Intrinsic::riscv_crc32_b;
     IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_crc32_h:
     ID = Intrinsic::riscv_crc32_h;
     IntrinsicTypes = {ResultType};
#include "clang/Basic/riscv_vector_builtin_cg.inc"
   case RISCV::BI__builtin_riscv_crc32c_w:
     ID = Intrinsic::riscv_crc32c_w;
     IntrinsicTypes = {ResultType};
     break;
   case RISCV::BI__builtin_riscv_crc32c_d:
     ID = Intrinsic::riscv_crc32c_d;
     IntrinsicTypes = {ResultType};
     break;
-  default: {
+  default:
     llvm_unreachable("unexpected builtin ID");
-    return nullptr;
-  } // default
   }
 
   assert(ID != Intrinsic::not_intrinsic);
 
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
   return Builder.CreateCall(F, Ops, "");
 }

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
   return false;
 }
 
 bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
                                          unsigned BuiltinID,
                                          CallExpr *TheCall) {
   // CodeGenFunction can also detect this, but this gives a better error
   // message.
   bool FeatureMissing = false;
   SmallVector<StringRef> ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
   Features.split(ReqFeatures, ',');
 
   // Check if each required feature is included
   for (auto &I : ReqFeatures) {
     if (TI.hasFeature(I))
       continue;
-    // Make message like "experimental-zbr" to "Zbr"
+    // Convert features like "zbr" and "experimental-zbr" to "Zbr".
     I.consume_front("experimental-");
     std::string FeatureStr = I.str();
     FeatureStr[0] = std::toupper(FeatureStr[0]);
 
     // Error message
     FeatureMissing = true;
     Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
         << TheCall->getSourceRange() << StringRef(FeatureStr);

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBB
+
+// RV32ZBB-LABEL: @orc_b_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT:    ret i32 [[TMP1]]
+//
+int orc_b_32(int a) {
+  return __builtin_riscv_orc_b_32(a);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBB
+
+// RV64ZBB-LABEL: @orc_b_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT:    ret i32 [[TMP1]]
+//
+int orc_b_32(int a) {
+  return __builtin_riscv_orc_b_32(a);
+}
+
+// RV64ZBB-LABEL: @orc_b_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT:    ret i64 [[TMP1]]
+//
+long orc_b_64(long a) {
+  return __builtin_riscv_orc_b_64(a);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

 //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines all of the RISCV-specific intrinsics.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
-// RISC-V Bitmanip (Bit Manipulation) Extension
-// Zbr extension part
-
-let TargetPrefix = "riscv" in {
-
-    class BitMan_GPR_Intrinsics
-        : Intrinsic<[llvm_any_ty],
-                    [LLVMMatchType<0>],
-                    [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-
-    def int_riscv_crc32_b : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32_h : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32_w : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32_d : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32c_b : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32c_h : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32c_w : BitMan_GPR_Intrinsics;
-    def int_riscv_crc32c_d : BitMan_GPR_Intrinsics;
-
-} // TargetPrefix = "riscv"
-
-//===----------------------------------------------------------------------===//
 // Atomics
 
 // Atomic Intrinsics have multiple versions for different access widths, which
 // all follow one of the following signatures (depending on how many arguments
 // they require). We carefully instantiate only specific versions of these for
 // specific integer widths, rather than using `llvm_anyint_ty`.
 //
 // In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the
 // canonical names, and the intrinsics used in the code will have a name
 // suffixed with the pointer type they are specialised for (denoted `<p>` in the
 // names below), in order to avoid type conflicts.
 
 let TargetPrefix = "riscv" in {
 
   // T @llvm.<name>.T.<p>(any*, T, T, T imm);
   class MaskedAtomicRMWFourArg<LLVMType itype>
       : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype],
                   [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<3>>]>;
   // T @llvm.<name>.T.<p>(any*, T, T, T, T imm);
   class MaskedAtomicRMWFiveArg<LLVMType itype>
       : Intrinsic<[itype], [llvm_anyptr_ty, itype, itype, itype, itype],
let TargetPrefix = "riscv" in {
   defm int_riscv_masked_atomicrmw_umin : MaskedAtomicRMWFourArgIntrinsics;
 
   // @llvm.riscv.masked.cmpxchg.{i32,i64}.<p>(...)
   defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
 
 } // TargetPrefix = "riscv"
 
 //===----------------------------------------------------------------------===//
+// Bitmanip (Bit Manipulation) Extension
+
+let TargetPrefix = "riscv" in {
+
+  class BitManipGPRIntrinsics
+      : Intrinsic<[llvm_any_ty],
+                  [LLVMMatchType<0>],
+                  [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+
+  // Zbb
+  def int_riscv_orc_b : BitManipGPRIntrinsics;
+
+  // Zbr
+  def int_riscv_crc32_b : BitManipGPRIntrinsics;
+  def int_riscv_crc32_h : BitManipGPRIntrinsics;
+  def int_riscv_crc32_w : BitManipGPRIntrinsics;
+  def int_riscv_crc32_d : BitManipGPRIntrinsics;
+  def int_riscv_crc32c_b : BitManipGPRIntrinsics;
+  def int_riscv_crc32c_h : BitManipGPRIntrinsics;
+  def int_riscv_crc32c_w : BitManipGPRIntrinsics;
+  def int_riscv_crc32c_d : BitManipGPRIntrinsics;
+} // TargetPrefix = "riscv"
+
+//===----------------------------------------------------------------------===//
 // Vectors
 
 class RISCVVIntrinsic {
   // These intrinsics may accept illegal integer values in their llvm_any_ty
   // operand, so they have to be extended. If set to zero then the intrinsic
   // does not have any operand that must be extended.
   Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
   bits<4> SplatOperand = 0;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   if (!Subtarget.hasStdExtZbb()) {
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
   }
 
+  if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
+    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
+
   if (Subtarget.is64Bit()) {
     setOperationAction(ISD::ADD, MVT::i32, Custom);
     setOperationAction(ISD::SUB, MVT::i32, Custom);
     setOperationAction(ISD::SHL, MVT::i32, Custom);
     setOperationAction(ISD::SRA, MVT::i32, Custom);
     setOperationAction(ISD::SRL, MVT::i32, Custom);
 
     setOperationAction(ISD::UADDO, MVT::i32, Custom);
case ISD::EXTRACT_VECTOR_ELT: {
     break;
   }
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
     switch (IntNo) {
     default:
       llvm_unreachable(
           "Don't know how to custom type legalize this intrinsic!");
+    case Intrinsic::riscv_orc_b: {
+      SDValue Newop1 =
+          DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+      SDValue Res = 
+          DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), Newop1);
+      Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+      return;
+    }
     case Intrinsic::riscv_vmv_x_s: {
       EVT VT = N->getValueType(0);
       MVT XLenVT = Subtarget.getXLenVT();
       if (VT.bitsLT(XLenVT)) {
         // Simple case just extract using vmv.x.s and truncate.
         SDValue Extract = DAG.getNode(RISCVISD::VMV_X_S, DL,
                                       Subtarget.getXLenVT(), N->getOperand(1));
         Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, Extract));

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
                                (and GPR:$rs1, 0x000000000000FFFF)),
                            i32)),
           (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
                    (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
 
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr<int_riscv_orc_b, ORCB>;
+} // Predicates = [HasStdExtZbb]
+
 let Predicates = [HasStdExtZbr] in {
 def : PatGpr<int_riscv_crc32_b, CRC32B>;
 def : PatGpr<int_riscv_crc32_h, CRC32H>;
 def : PatGpr<int_riscv_crc32_w, CRC32W>;
 def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
 def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
 def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
 } // Predicates = [HasStdExtZbr]
 
 let Predicates = [HasStdExtZbr, IsRV64] in {
 def : PatGpr<int_riscv_crc32_d, CRC32D>;
 def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
 } // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    orc.b a0, a0
+; RV32IB-NEXT:    ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB:       # %bb.0:
+; RV32IBB-NEXT:    orc.b a0, a0
+; RV32IBB-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb32(i32 %a) nounwind {
+; RV64IB-LABEL: orcb32:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    orc.b a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBB-LABEL: orcb32:
+; RV64IBB:       # %bb.0:
+; RV64IBB-NEXT:    orc.b a0, a0
+; RV64IBB-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb64(i64 %a) nounwind {
+; RV64IB-LABEL: orcb64:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    orc.b a0, a0
+; RV64IB-NEXT:    ret
+;
+; RV64IBB-LABEL: orcb64:
+; RV64IBB:       # %bb.0:
+; RV64IBB-NEXT:    orc.b a0, a0
+; RV64IBB-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}