[RISCV] [1/2] Add intrinsic for Zbr extension

[LevyHsu]

Summary

Implementation for RISC-V Zbr extension intrinsic.

Head files are included in the second patch in case the name needs to be changed

RV32 / 64:

crc32b
crc32h
crc32w
crc32cb
crc32ch
crc32cw

RV64 Only:

crc32d
crc32cd

[jrtc27]

Please fix the style issues and update the patch with full context (see https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface, or use arc)

clang/include/clang/Basic/BuiltinsRISCV.def

20

Zbr

clang/include/clang/Basic/DiagnosticSemaKinds.td

11170

This will apply to non-experimental extensions too once V/B/K/etc get ratified

clang/lib/Sema/SemaChecking.cpp

3400

This new code assumes there's only one feature in the string

3405

Extension name should have an upper case first letter

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c

16–17

long crc32b(long a) { for all these

clang/test/Headers/rvintrin.c

5 ↗

(On Diff #332079)

This does nothing unless you add -verify to the Clang command line

llvm/include/llvm/IR/IntrinsicsRISCV.td

20

Space after comma

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

879

Space after comma

llvm/test/CodeGen/RISCV/rv32Zbr.ll

1 ↗

(On Diff #332079)

Lowercase z in the names of these files as it's a (sort of) -march string

[craig.topper]

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c

6

I don't think this include is needed. You're calling the __builtin names directly.

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c

6

Same here

clang/test/Headers/rvintrin.c

7 ↗

(On Diff #332079)

This should be in the D99008 patch

[craig.topper]

llvm/test/CodeGen/RISCV/rv32Zbr.ll

1 ↗

(On Diff #332079)

The bitmanip tests were already have all us "Zb*" in their file names. Should we match that or rename the existing tests?

[jrtc27]

llvm/test/CodeGen/RISCV/rv32Zbr.ll

1 ↗

(On Diff #332079)

:( ideally they'd be renamed IMO, but if not then yeah I guess this should stay as it is to match

[LevyHsu]

1. Fix format issue
2. SemaChecking.cpp should allow Diag to print all missing features now.

[craig.topper]

Please reupload the patch using something like "git diff -U99999". We should be able to expand the full diff here so that phabricator doesn't say "Context not available."

[craig.topper]

clang/lib/Sema/SemaChecking.cpp

3398

Variable names should start with a capital letter and use CamelCase.

3401

Features is already a StringRef, no need to cast it before calling split.

3404

Use a range-based for loop.

3405

Invert the condition and use a continue; Then we can reduce nesting for the rest of the code.

3415

Please fix formatting as the Pre-merge check suggests.

llvm/include/llvm/IR/IntrinsicsRISCV.td

29

Put crc32_d directly below crc32_w. So all the crc32_ are together and all the crc32c_ are together.

[craig.topper]

clang/lib/CodeGen/CGBuiltin.cpp

17865

With the llvm_any_ty change, you'll only need ResultType here.

llvm/include/llvm/IR/IntrinsicsRISCV.td

20

The second llvm_any_ty here should be LLVMMatchType<0> since the types need to be the same.

[LevyHsu]

1. clang/lib/Sema/SemaChecking.cpp
   • Rewrite Sema::CheckRISCVBuiltinFunctionCall
   • Coding style fix
2. llvm/include/llvm/IR/IntrinsicsRISCV.td
   • BitMan_GPR_Intrinsics's op1 now matches type of op0
   • Put crc32_d directly below crc32_w.
   • Coding style fix
3. llvm/lib/Target/RISCV/RISCVInstrInfoB.td
   • Coding style fix

[Jim]

clang/include/clang/Basic/BuiltinsRISCV.def

28

I don't know why it doesn't use rv* prefix directly?

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

28

I believe using builtin* is consistent with how intrinsics are handled on most targets in both clang and gcc. We wouldn't want the rv symbols declared unless the user has included rvintrin.h. There is some support for detecting that, see HEADER_BUILTIN in Builtins.def, but it's used rarely for target specific intrinsics.

[craig.topper]

I think this looks good to me. Anyone else have any comments?

[craig.topper]

LGTM. We can adjust the builtin names in the future if we need to do something different to match gcc.

[jrtc27]

clang/include/clang/Basic/DiagnosticSemaKinds.td

11190

This lost the quotes

clang/lib/Sema/SemaChecking.cpp

3427

both to improve the English and to be clear that this is for non-experimental feature strings too

llvm/include/llvm/IR/IntrinsicsRISCV.td

19

This file, like the rest of LLVM, uses a 2-space indent, not 4.

[craig.topper]

clang/include/clang/Basic/DiagnosticSemaKinds.td

11190

I will fix when I rebase Zbb on top of this

clang/lib/Sema/SemaChecking.cpp

3427

I will fix when I rebase Zbb on top of this

llvm/include/llvm/IR/IntrinsicsRISCV.td

19

I will fix when I rebase Zbb on top of this. I'll also move it below atomics.

[jrtc27]

Thanks, and good point re ordering

[thakis]

Looks like this doesn't build on windows: http://45.33.8.238/win/36271/step_4.txt

Please take a look and revert for now if it takes a while to fix.

[jrtc27]

In D99009#2666793, @thakis wrote:

Looks like this doesn't build on windows: http://45.33.8.238/win/36271/step_4.txt

Please take a look and revert for now if it takes a while to fix.

Hopefully fixed in 1bd4986e7cdc

[thakis]

In D99009#2666797, @jrtc27 wrote:

In D99009#2666793, @thakis wrote:

Looks like this doesn't build on windows: http://45.33.8.238/win/36271/step_4.txt

Please take a look and revert for now if it takes a while to fix.

Hopefully fixed in 1bd4986e7cdc

Yup, better now. Thanks for the fix!

clang/include/clang/Basic/BuiltinsRISCV.def

 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #include "clang/Basic/riscv_vector_builtins.inc"
 
+// Zbr extension
+TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
+TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Basic/DiagnosticSemaKinds.td

def warn_sycl_kernel_num_of_function_params : Warning<
   "function template with 'sycl_kernel' attribute must have a single parameter">,
   InGroup<IgnoredAttributes>;
 def warn_sycl_kernel_return_type : Warning<
   "function template with 'sycl_kernel' attribute must have a 'void' return type">,
   InGroup<IgnoredAttributes>;
 
 def err_ext_int_bad_size : Error<"%select{signed|unsigned}0 _ExtInt must "
                                  "have a bit size of at least %select{2|1}0">;
 def err_ext_int_max_size : Error<"%select{signed|unsigned}0 _ExtInt of bit "
                                  "sizes greater than %1 not supported">;
 
 // errors of expect.with.probability
 def err_probability_not_constant_float : Error<
    "probability argument to __builtin_expect_with_probability must be constant "
    "floating-point expression">;
 def err_probability_out_of_range : Error<
    "probability argument to __builtin_expect_with_probability is outside the "
    "range [0.0, 1.0]">;
 
 // TCB warnings
 def err_tcb_conflicting_attributes : Error<
   "attributes '%0(\"%2\")' and '%1(\"%2\")' are mutually exclusive">;
 def warn_tcb_enforcement_violation : Warning<
   "calling %0 is a violation of trusted computing base '%1'">,
   InGroup<DiagGroup<"tcb-enforcement">>;
 
-// RISC-V V-extension
-def err_riscvv_builtin_requires_v : Error<
-   "builtin requires 'V' extension support to be enabled">;
+// RISC-V builtin required extension warning
+def err_riscv_builtin_requires_extension : Error<
+  "builtin requires %0 extension support to be enabled">;
 } // end of sema component.

clang/lib/CodeGen/CGBuiltin.cpp

default: {
     return Call;
   } // default
   } // switch
 
   return nullptr;
 }
 
 Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
                                              const CallExpr *E,
                                              ReturnValueSlot ReturnValue) {
   SmallVector<Value *, 4> Ops;
   llvm::Type *ResultType = ConvertType(E->getType());
 
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
     Ops.push_back(EmitScalarExpr(E->getArg(i)));
 
   Intrinsic::ID ID = Intrinsic::not_intrinsic;
 
   // Required for overloaded intrinsics.
   llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;
   switch (BuiltinID) {
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
+
+  // Zbr
+  case RISCV::BI__builtin_riscv_crc32_b:
+    ID = Intrinsic::riscv_crc32_b;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_h:
+    ID = Intrinsic::riscv_crc32_h;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_w:
+    ID = Intrinsic::riscv_crc32_w;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32_d:
+    ID = Intrinsic::riscv_crc32_d;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_b:
+    ID = Intrinsic::riscv_crc32c_b;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_h:
+    ID = Intrinsic::riscv_crc32c_h;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_w:
+    ID = Intrinsic::riscv_crc32c_w;
+    IntrinsicTypes = {ResultType};
+    break;
+  case RISCV::BI__builtin_riscv_crc32c_d:
+    ID = Intrinsic::riscv_crc32c_d;
+    IntrinsicTypes = {ResultType};
+    break;
+  default: {
+    llvm_unreachable("unexpected builtin ID");
+    return nullptr;
+  } // default
   }
 
   assert(ID != Intrinsic::not_intrinsic);
 
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
   return Builder.CreateCall(F, Ops, "");
 }

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
   case llvm::AtomicOrderingCABI::acquire:
   case llvm::AtomicOrderingCABI::release:
   case llvm::AtomicOrderingCABI::acq_rel:
   case llvm::AtomicOrderingCABI::seq_cst:
     break;
   default: {
     return Diag(ArgExpr->getBeginLoc(),
                 diag::warn_atomic_op_has_invalid_memory_order)
            << ArgExpr->getSourceRange();
   }
   }
 
   Arg = TheCall->getArg(ScopeIndex);
   ArgExpr = Arg.get();
   Expr::EvalResult ArgResult1;
   // Check that sync scope is a constant literal
   if (!ArgExpr->EvaluateAsConstantExpr(ArgResult1, Context))
     return Diag(ArgExpr->getExprLoc(), diag::err_expr_not_string_literal)
            << ArgExpr->getType();
 
   return false;
 }
 
 bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
                                          unsigned BuiltinID,
                                          CallExpr *TheCall) {
   // CodeGenFunction can also detect this, but this gives a better error
   // message.
+  bool FeatureMissing = false;
+  SmallVector<StringRef> ReqFeatures;
   StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
-  if (Features.find("experimental-v") != StringRef::npos &&
-      !TI.hasFeature("experimental-v"))
-    return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v)
-           << TheCall->getSourceRange();
+  Features.split(ReqFeatures, ',');
 
-  return false;
+  // Check if each required feature is included
+  for (auto &I : ReqFeatures) {
+    if (TI.hasFeature(I))
+      continue;
+    // Make message like "experimental-zbr" to "Zbr"
+    I.consume_front("experimental-");
+    std::string FeatureStr = I.str();
+    FeatureStr[0] = std::toupper(FeatureStr[0]);
+
+    // Error message
+    FeatureMissing = true;
+    Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+        << TheCall->getSourceRange() << StringRef(FeatureStr);
+  }
+
+  return FeatureMissing;
 }
 
 bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID,
                                            CallExpr *TheCall) {
   if (BuiltinID == SystemZ::BI__builtin_tabort) {
     Expr *Arg = TheCall->getArg(0);
     if (Optional<llvm::APSInt> AbortCode = Arg->getIntegerConstantExpr(Context))
       if (AbortCode->getSExtValue() >= 0 && AbortCode->getSExtValue() < 256)

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbr.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbr -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZBR
+
+// RV32ZBR-LABEL: @crc32_b(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.b.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32_b(long a) {
+  return __builtin_riscv_crc32_b(a);
+}
+
+// RV32ZBR-LABEL: @crc32_h(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.h.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32_h(long a) {
+  return __builtin_riscv_crc32_h(a);
+}
+
+// RV32ZBR-LABEL: @crc32_w(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32.w.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32_w(long a) {
+  return __builtin_riscv_crc32_w(a);
+}
+
+// RV32ZBR-LABEL: @crc32c_b(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.b.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32c_b(long a) {
+  return __builtin_riscv_crc32c_b(a);
+}
+
+// RV32ZBR-LABEL: @crc32c_h(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.h.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32c_h(long a) {
+  return __builtin_riscv_crc32c_h(a);
+}
+
+// RV32ZBR-LABEL: @crc32c_w(
+// RV32ZBR-NEXT:  entry:
+// RV32ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBR-NEXT:    store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBR-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.crc32c.w.i32(i32 [[TMP0]])
+// RV32ZBR-NEXT:    ret i32 [[TMP1]]
+//
+long crc32c_w(long a) {
+  return __builtin_riscv_crc32c_w(a);
+}

clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbr.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbr -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZBR
+
+// RV64ZBR-LABEL: @crc32_b(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.b.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32_b(long a) {
+  return __builtin_riscv_crc32_b(a);
+}
+
+// RV64ZBR-LABEL: @crc32_h(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.h.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32_h(long a) {
+  return __builtin_riscv_crc32_h(a);
+}
+
+// RV64ZBR-LABEL: @crc32_w(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.w.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32_w(long a) {
+  return __builtin_riscv_crc32_w(a);
+}
+
+// RV64ZBR-LABEL: @crc32c_b(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.b.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32c_b(long a) {
+  return __builtin_riscv_crc32c_b(a);
+}
+
+// RV64ZBR-LABEL: @crc32c_h(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.h.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32c_h(long a) {
+  return __builtin_riscv_crc32c_h(a);
+}
+
+// RV64ZBR-LABEL: @crc32c_w(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.w.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32c_w(long a) {
+  return __builtin_riscv_crc32c_w(a);
+}
+
+// RV64ZBR-LABEL: @crc32_d(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32.d.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32_d(long a) {
+  return __builtin_riscv_crc32_d(a);
+}
+
+// RV64ZBR-LABEL: @crc32c_d(
+// RV64ZBR-NEXT:  entry:
+// RV64ZBR-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBR-NEXT:    store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBR-NEXT:    [[TMP1:%.*]] = call i64 @llvm.riscv.crc32c.d.i64(i64 [[TMP0]])
+// RV64ZBR-NEXT:    ret i64 [[TMP1]]
+//
+long crc32c_d(long a) {
+  return __builtin_riscv_crc32c_d(a);
+}

llvm/include/llvm/IR/IntrinsicsRISCV.td

 //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines all of the RISCV-specific intrinsics.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
+// RISC-V Bitmanip (Bit Manipulation) Extension
+// Zbr extension part
+
+let TargetPrefix = "riscv" in {
+
+    class BitMan_GPR_Intrinsics
+        : Intrinsic<[llvm_any_ty],
+                    [LLVMMatchType<0>],
+                    [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+
+    def int_riscv_crc32_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32_d : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_b : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_h : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_w : BitMan_GPR_Intrinsics;
+    def int_riscv_crc32c_d : BitMan_GPR_Intrinsics;
+
+} // TargetPrefix = "riscv"
+
+//===----------------------------------------------------------------------===//
 // Atomics
 
 // Atomic Intrinsics have multiple versions for different access widths, which
 // all follow one of the following signatures (depending on how many arguments
 // they require). We carefully instantiate only specific versions of these for
 // specific integer widths, rather than using `llvm_anyint_ty`.
 //
 // In fact, as these intrinsics take `llvm_anyptr_ty`, the given names are the

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 //
 // Naming convention: For 'generic' pattern classes, we use the naming
 // convention PatTy1Ty2. For pattern classes which offer a more complex
 // expansion, prefix the class name, e.g. BccPat.
 //===----------------------------------------------------------------------===//
 
 /// Generic pattern classes
 
+class PatGpr<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
 class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
     : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst>
     : Pat<(OpNode GPR:$rs1, simm12:$imm12), (Inst GPR:$rs1, simm12:$imm12)>;
 class PatGprUimmLog2XLen<SDPatternOperator OpNode, RVInstIShift Inst>
     : Pat<(OpNode GPR:$rs1, uimmlog2xlen:$shamt),
           (Inst GPR:$rs1, uimmlog2xlen:$shamt)>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def : Pat<(i64 (riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2)),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(i64 (riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2)),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(i64 (riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt)),
           (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
 def : Pat<(i64 (riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt)),
           (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(i64 (riscv_clzw GPR:$rs1)), (CLZW GPR:$rs1)>;
 def : Pat<(i64 (riscv_ctzw GPR:$rs1)), (CTZW GPR:$rs1)>;
 def : Pat<(i64 (ctpop (and GPR:$rs1, 0xFFFFFFFF))), (CPOPW GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
                                (and GPR:$rs1, 0x000000000000FFFF)),
                            i32)),
           (PACKW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
                    (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
           (PACKUW GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbp, IsRV64]
+
+let Predicates = [HasStdExtZbr] in {
+def : PatGpr<int_riscv_crc32_b, CRC32B>;
+def : PatGpr<int_riscv_crc32_h, CRC32H>;
+def : PatGpr<int_riscv_crc32_w, CRC32W>;
+def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
+def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
+def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
+} // Predicates = [HasStdExtZbr]
+
+let Predicates = [HasStdExtZbr, IsRV64] in {
+def : PatGpr<int_riscv_crc32_d, CRC32D>;
+def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
+} // Predicates = [HasStdExtZbr, IsRV64]

llvm/test/CodeGen/RISCV/rv32zbr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32ZBR
+
+declare i32 @llvm.riscv.crc32.b.i32(i32)
+
+define i32 @crc32b(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32b:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.b a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.h.i32(i32)
+
+define i32 @crc32h(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32h:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.h a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32.w.i32(i32)
+
+define i32 @crc32w(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32w:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32.w a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32.w.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.b.i32(i32)
+
+define i32 @crc32cb(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cb:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.b a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.h.i32(i32)
+
+define i32 @crc32ch(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32ch:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.h a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.h.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.crc32c.w.i32(i32)
+
+define i32 @crc32cw(i32 %a) nounwind {
+; RV32ZBR-LABEL: crc32cw:
+; RV32ZBR:       # %bb.0:
+; RV32ZBR-NEXT:    crc32c.w a0, a0
+; RV32ZBR-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.crc32c.w.i32(i32 %a)
+ ret i32 %tmp
+}

llvm/test/CodeGen/RISCV/rv64zbr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=experimental-zbr -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64ZBR
+
+declare i64 @llvm.riscv.crc32.b.i64(i64)
+
+define i64 @crc32b(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32b:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.b a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.h.i64(i64)
+
+define i64 @crc32h(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32h:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.h a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.w.i64(i64)
+
+define i64 @crc32w(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32w:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.w a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.b.i64(i64)
+
+define i64 @crc32cb(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cb:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.b a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.b.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.h.i64(i64)
+
+define i64 @crc32ch(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32ch:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.h a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.h.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.w.i64(i64)
+
+define i64 @crc32cw(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cw:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.w a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.w.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32.d.i64(i64)
+
+define i64 @crc32d(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32d:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32.d a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32.d.i64(i64 %a)
+ ret i64 %tmp
+}
+
+declare i64 @llvm.riscv.crc32c.d.i64(i64)
+
+define i64 @crc32cd(i64 %a) nounwind {
+; RV64ZBR-LABEL: crc32cd:
+; RV64ZBR:       # %bb.0:
+; RV64ZBR-NEXT:    crc32c.d a0, a0
+; RV64ZBR-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.crc32c.d.i64(i64 %a)
+ ret i64 %tmp
+}