[SelectionDAG] Support scalable-vector splats in more cases

[frasercrmck]

Summary

This patch adds support for scalable-vector splats in DAGCombiner's
isConstantOrConstantVector and ISD::matchUnaryPredicate functions,
which enable the SelectionDAG div/rem-by-constant optimizations for
scalable vector types.

It also fixes up one case where the UDIV optimization was generating a
SETCC without first consulting the target for its preferred SETCC result
type.

[frasercrmck]

@c-rhodes or @david-arm I've updated the AArch64 tests naively but I thought I'd tag you in case you don't intend to be shifting out all bits.

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

5034

In general, is isFixedLengthVector || isScalableVector a suitable replacement for isVector, or should we be more explicit/future-proof about the possibility of a third case?

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

5038

Is there only one element in Shifts and Factors? If I'm reading matchUnaryPredicate right it will only see the single operand of the SPLAT_VECTOR so only call BuildSDIVPattern once?

5329

I'm a bit surprised this didn't affect AVX512 on X86.

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

598

Is this test trying to test an oversized shift amount or just a bad choice of constant? I'm leaning towards bad constant choice the lsl tests don't have this issue?

[frasercrmck]

rebase on main

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

5038

Yes, that's how it's working. Is that strong enough a thing to rely upon, do you think?

5329

Should we double-check that AVX512 has tested this code path?

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

598

Yeah I'd imagine the latter too. I tried to tag some of the AArch64 team to see if they could help resolve this issue

[david-arm]

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

598

Oh yeah, sorry about this. We did discuss it and the problem is with our tests I think. We've created tests that are shifting by more than the element width. I think this change is fine and we'll create some better tests after your patch lands.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

5038

Can we put an assert on the size and everwhere else we access element 0 to make it clear we aren't dropping anything?

[frasercrmck]

• add in assertions

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

5038

Yep, done

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

5329

Looks like both operands to getSetCC are both constant vectors so this gets constant folded on non-scalable vectors. Then the getSelect will constant fold based on the condition being a constant. So maybe that's why AVX512 doesn't care.

[craig.topper]

LGTM

[huihuiz]

This is crashing SVE target lowering with "LLVM ERROR: Cannot select: t23: nxv4i32 = mulhu t9, t34"
Let me know if there is a way of fixing it?

Take below t.ll
Run: llc -O2 -mtriple=aarch64-linux-gnu -mattr=+sve < t.ll

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"

define void @test(<vscale x 4 x i32>* %in, <vscale x 4 x i32>* %out, <vscale x 4 x i1> %p) {
entry:
  %a = load <vscale x 4 x i32>, <vscale x 4 x i32>* %in, align 16
  %div = udiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
  call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %div, <vscale x 4 x i32>* %out, i32 4, <vscale x 4 x i1> %p)
  unreachable
}

declare void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>*, i32 immarg, <vscale x 4 x i1>)

[frasercrmck]

In D94501#2566853, @huihuiz wrote:

This is crashing SVE target lowering with "LLVM ERROR: Cannot select: t23: nxv4i32 = mulhu t9, t34"
Let me know if there is a way of fixing it?

Hi @huihuiz, thanks for raising this issue with me. You've probably seen D96849 by now.

Since I'm not familiar with AArch64 I thought the quickest and safest way to fix the issue would be to prevent these optimizations from taking place. The AArch64 team can work out if there's a way of supporting these nodes.

[huihuiz]

Thanks @frasercrmck for helping! Appreciate it!

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

static bool isConstantSplatVectorMaskForType(SDNode *N, EVT ScalarTy) {
 
   APInt Val;
   if (ISD::isConstantSplatVector(N, Val))
     return Val.getLimitedValue() == MaskForTy;
 
   return false;
 }
 
-// Determines if it is a constant integer or a build vector of constant
+// Determines if it is a constant integer or a splat/build vector of constant
 // integers (and undefs).
 // Do not permit build vector implicit truncation.
 static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
   if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
     return !(Const->isOpaque() && NoOpaques);
-  if (N.getOpcode() != ISD::BUILD_VECTOR)
+  if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR)
     return false;
   unsigned BitWidth = N.getScalarValueSizeInBits();
   for (const SDValue &Op : N->op_values()) {
     if (Op.isUndef())
       continue;
     ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
     if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
         (Const->isOpaque() && NoOpaques))

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 bool ISD::matchUnaryPredicate(SDValue Op,
                               std::function<bool(ConstantSDNode *)> Match,
                               bool AllowUndefs) {
   // FIXME: Add support for scalar UNDEF cases?
   if (auto *Cst = dyn_cast<ConstantSDNode>(Op))
     return Match(Cst);
 
   // FIXME: Add support for vector UNDEF cases?
-  if (ISD::BUILD_VECTOR != Op.getOpcode())
+  if (ISD::BUILD_VECTOR != Op.getOpcode() &&
+      ISD::SPLAT_VECTOR != Op.getOpcode())
     return false;
 
   EVT SVT = Op.getValueType().getScalarType();
   for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
     if (AllowUndefs && Op.getOperand(i).isUndef()) {
       if (!Match(nullptr))
         return false;
       continue;

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

auto BuildSDIVPattern = [&](ConstantSDNode *C) {
     return true;
   };
 
   // Collect all magic values from the build vector.
   if (!ISD::matchUnaryPredicate(Op1, BuildSDIVPattern))
     return SDValue();
 
   SDValue Shift, Factor;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     Shift = DAG.getBuildVector(ShVT, dl, Shifts);
     Factor = DAG.getBuildVector(VT, dl, Factors);
+  } else if (VT.isScalableVector()) {
+    assert(Shifts.size() == 1 && Factors.size() == 1 &&
+           "Expected matchUnaryPredicate to return one element for scalable "
+           "vectors");
+    Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]);
+    Factor = DAG.getSplatVector(VT, dl, Factors[0]);
   } else {
     Shift = Shifts[0];
     Factor = Factors[0];
   }
 
   SDValue Res = Op0;
 
   // Shift the value upfront if it is even, so the LSB is one.
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
   // Collect the shifts / magic values from each element.
   if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
     return SDValue();
 
   SDValue MagicFactor, Factor, Shift, ShiftMask;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
     Factor = DAG.getBuildVector(VT, dl, Factors);
     Shift = DAG.getBuildVector(ShVT, dl, Shifts);
     ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
+  } else if (VT.isScalableVector()) {
+    assert(MagicFactors.size() == 1 && Factors.size() == 1 &&
+           Shifts.size() == 1 && ShiftMasks.size() == 1 &&
+           "Expected matchUnaryPredicate to return one element for scalable "
+           "vectors");
+    MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]);
+    Factor = DAG.getSplatVector(VT, dl, Factors[0]);
+    Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]);
+    ShiftMask = DAG.getSplatVector(VT, dl, ShiftMasks[0]);
   } else {
     MagicFactor = MagicFactors[0];
     Factor = Factors[0];
     Shift = Shifts[0];
     ShiftMask = ShiftMasks[0];
   }
 
   // Multiply the numerator (operand 0) by the magic value.
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
   // Collect the shifts/magic values from each element.
   if (!ISD::matchUnaryPredicate(N1, BuildUDIVPattern))
     return SDValue();
 
   SDValue PreShift, PostShift, MagicFactor, NPQFactor;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     PreShift = DAG.getBuildVector(ShVT, dl, PreShifts);
     MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
     NPQFactor = DAG.getBuildVector(VT, dl, NPQFactors);
     PostShift = DAG.getBuildVector(ShVT, dl, PostShifts);
+  } else if (VT.isScalableVector()) {
+    assert(PreShifts.size() == 1 && MagicFactors.size() == 1 &&
+           NPQFactors.size() == 1 && PostShifts.size() == 1 &&
+           "Expected matchUnaryPredicate to return one for scalable vectors");
+    PreShift = DAG.getSplatVector(ShVT, dl, PreShifts[0]);
+    MagicFactor = DAG.getSplatVector(VT, dl, MagicFactors[0]);
+    NPQFactor = DAG.getSplatVector(VT, dl, NPQFactors[0]);
+    PostShift = DAG.getSplatVector(ShVT, dl, PostShifts[0]);
   } else {
     PreShift = PreShifts[0];
     MagicFactor = MagicFactors[0];
     PostShift = PostShifts[0];
   }
 
   SDValue Q = N0;
   Q = DAG.getNode(ISD::SRL, dl, VT, Q, PreShift);
if (UseNPQ) {
 
     Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
     Created.push_back(Q.getNode());
   }
 
   Q = DAG.getNode(ISD::SRL, dl, VT, Q, PostShift);
   Created.push_back(Q.getNode());
 
+  EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+
   SDValue One = DAG.getConstant(1, dl, VT);
-  SDValue IsOne = DAG.getSetCC(dl, VT, N1, One, ISD::SETEQ);
+  SDValue IsOne = DAG.getSetCC(dl, SetCCVT, N1, One, ISD::SETEQ);
   return DAG.getSelect(dl, VT, IsOne, N0, Q);
 }
 
 /// If all values in Values that *don't* match the predicate are same 'splat'
 /// value, then replace all values with that splat value.
 /// Else, if AlternativeReplacement was provided, then replace all values that
 /// do match predicate with AlternativeReplacement value.
 static void
if (AllDivisorsAreOnes)
     return SDValue();
 
   // If this is a srem by a powers-of-two (including INT_MIN), avoid the fold
   // since it can be best implemented as a bit test.
   if (AllDivisorsArePowerOfTwo)
     return SDValue();
 
   SDValue PVal, AVal, KVal, QVal;
-  if (VT.isVector()) {
+  if (VT.isFixedLengthVector()) {
     if (HadOneDivisor) {
       // Try to turn PAmts into a splat, since we don't care about the values
       // that are currently '0'. If we can't, just keep '0'`s.
       turnVectorIntoSplatVector(PAmts, isNullConstant);
       // Try to turn AAmts into a splat, since we don't care about the
       // values that are currently '-1'. If we can't, change them to '0'`s.
       turnVectorIntoSplatVector(AAmts, isAllOnesConstant,
                                 DAG.getConstant(0, DL, SVT));
       // Try to turn KAmts into a splat, since we don't care about the values
       // that are currently '-1'. If we can't, change them to '0'`s.
       turnVectorIntoSplatVector(KAmts, isAllOnesConstant,
                                 DAG.getConstant(0, DL, ShSVT));
     }
 
     PVal = DAG.getBuildVector(VT, DL, PAmts);
     AVal = DAG.getBuildVector(VT, DL, AAmts);
     KVal = DAG.getBuildVector(ShVT, DL, KAmts);
     QVal = DAG.getBuildVector(VT, DL, QAmts);
+  } else if (VT.isScalableVector()) {
+    assert(PAmts.size() == 1 && AAmts.size() == 1 && KAmts.size() == 1 &&
+           QAmts.size() == 1 &&
+           "Expected matchUnaryPredicate to return one element for scalable "
+           "vectors");
+    PVal = DAG.getSplatVector(VT, DL, PAmts[0]);
+    AVal = DAG.getSplatVector(VT, DL, AAmts[0]);
+    KVal = DAG.getSplatVector(ShVT, DL, KAmts[0]);
+    QVal = DAG.getSplatVector(VT, DL, QAmts[0]);
   } else {
     PVal = PAmts[0];
     AVal = AAmts[0];
     KVal = KAmts[0];
     QVal = QAmts[0];
   }
 
   // (mul N, P)

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtV()) {
     for (auto VT : MVT::integer_scalable_vector_valuetypes()) {
       setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
 
       setOperationAction(ISD::SMIN, VT, Legal);
       setOperationAction(ISD::SMAX, VT, Legal);
       setOperationAction(ISD::UMIN, VT, Legal);
       setOperationAction(ISD::UMAX, VT, Legal);
 
+      setOperationAction(ISD::ROTL, VT, Expand);
+      setOperationAction(ISD::ROTR, VT, Expand);
+
       if (isTypeLegal(VT)) {
         // Custom-lower extensions and truncations from/to mask types.
         setOperationAction(ISD::ANY_EXTEND, VT, Custom);
         setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
         setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
 
         // We custom-lower all legally-typed vector truncates:
         // 1. Mask VTs are custom-expanded into a series of standard nodes
case RISCVISD::SELECT_CC: {
     }
     break;
   }
   case ISD::SETCC: {
     // (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.
     // Comparing with 0 may allow us to fold into bnez/beqz.
     SDValue LHS = N->getOperand(0);
     SDValue RHS = N->getOperand(1);
+    if (LHS.getValueType().isScalableVector())
+      break;
     auto CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
     APInt Mask = APInt::getBitsSetFrom(LHS.getValueSizeInBits(), 1);
     if (isOneConstant(RHS) && ISD::isIntEqualitySetCC(CC) &&
         DAG.MaskedValueIsZero(LHS, Mask)) {
       SDLoc DL(N);
       SDValue Zero = DAG.getConstant(0, DL, LHS.getValueType());
       CC = ISD::getSetCCInverse(CC, LHS.getValueType());
       return DAG.getSetCC(DL, N->getValueType(0), LHS, Zero, CC);

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
   %res = mul <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %res
 }
 
 ; ASR
 
 define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a){
 ; CHECK-LABEL: @asr_i8
-; CHECK-DAG: asr z0.b, z0.b, #8
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %lshr = ashr <vscale x 16 x i8> %a, %splat
   ret <vscale x 16 x i8> %lshr
 }
 
 define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a){
 ; CHECK-LABEL: @asr_i16
-; CHECK-DAG: asr z0.h, z0.h, #16
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %ashr = ashr <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i16> %ashr
 }
 
 define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a){
 ; CHECK-LABEL: @asr_i32
-; CHECK-DAG: asr z0.s, z0.s, #32
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %ashr = ashr <vscale x 4 x i32> %a, %splat
   ret <vscale x 4 x i32> %ashr
 }
 
 define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a){
 ; CHECK-LABEL: @asr_i64
-; CHECK-DAG: asr z0.d, z0.d, #64
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %ashr = ashr <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %ashr
 }
 
 ; LSL
; CHECK-NEXT: ret
   %shl = shl <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %shl
 }
 
 ; LSR
 
 define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a){
 ; CHECK-LABEL: @lsr_i8
-; CHECK-DAG: lsr z0.b, z0.b, #8
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0
   %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %lshr = lshr <vscale x 16 x i8> %a, %splat
   ret <vscale x 16 x i8> %lshr
 }
 
 define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a){
 ; CHECK-LABEL: @lsr_i16
-; CHECK-DAG: lsr z0.h, z0.h, #16
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %lshr = lshr <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i16> %lshr
 }
 
 define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a){
 ; CHECK-LABEL: @lsr_i32
-; CHECK-DAG: lsr z0.s, z0.s, #32
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
   %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %lshr = lshr <vscale x 4 x i32> %a, %splat
   ret <vscale x 4 x i32> %lshr
 }
 
 define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a){
 ; CHECK-LABEL: @lsr_i64
-; CHECK-DAG: lsr z0.d, z0.d, #64
+; CHECK: // %bb.0:
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 64, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %lshr = lshr <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %lshr
 }

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 ; Test V/1 to see if we can optimize it away for scalable vectors.
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v8, v28, 7
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 7
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v8, v28, 15
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v16, v8, 15
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vsub.vv v26, v26, v8
+; CHECK-NEXT:    vsra.vi v28, v26, 2
+; CHECK-NEXT:    vsrl.vi v26, v26, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vsub.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v8, v28, 2
+; CHECK-NEXT:    vsrl.vi v28, v28, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v16, v8, 2
+; CHECK-NEXT:    vsrl.vi v8, v8, 31
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vmulh.vv v25, v8, v25
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vmulh.vv v26, v8, v26
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v12, a1
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vmulh.vv v28, v8, v28
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v8, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v24, a1
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vmulh.vv v8, v8, v16
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v16, v8, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdiv_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdiv_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdiv_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdiv_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdiv_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v8, v28, 7
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdiv_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 7
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vdiv_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdiv_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdiv_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdiv_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdiv_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v8, v28, 15
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdiv_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v16, v8, 15
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vdiv_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdiv_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdiv_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdiv_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v8, v28, 31
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdiv_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v8, v8, 0
+; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 31
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdiv_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v8, v26, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdiv_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v8, v28, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdiv_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v8, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdiv_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vadd.vi v8, v8, 0
+; CHECK-NEXT:    vsra.vi v16, v8, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v8, v8, a0
+; CHECK-NEXT:    vand.vi v8, v8, -1
+; CHECK-NEXT:    vadd.vv v8, v16, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 ; Test V/1 to see if we can optimize it away for scalable vectors.
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = udiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = udiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 29
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    vsrl.vi v24, v24, 29
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vmv.v.i v27, 1
+; CHECK-NEXT:    vsll.vx v27, v27, a0
+; CHECK-NEXT:    vsrl.vx v27, v27, a0
+; CHECK-NEXT:    vor.vv v26, v27, v26
+; CHECK-NEXT:    vmulhu.vv v26, v8, v26
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vmv.v.i v30, 1
+; CHECK-NEXT:    vsll.vx v30, v30, a0
+; CHECK-NEXT:    vsrl.vx v30, v30, a0
+; CHECK-NEXT:    vor.vv v28, v30, v28
+; CHECK-NEXT:    vmulhu.vv v28, v8, v28
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vmv.v.i v16, 1
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vor.vv v12, v16, v12
+; CHECK-NEXT:    vmulhu.vv v12, v8, v12
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vmv.v.i v0, 1
+; CHECK-NEXT:    vsll.vx v0, v0, a0
+; CHECK-NEXT:    vsrl.vx v0, v0, a0
+; CHECK-NEXT:    vor.vv v24, v0, v24
+; CHECK-NEXT:    vmulhu.vv v24, v8, v24
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = udiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = udiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v8, v25, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v8, v26, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v8, v28, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vdivu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+; Test that the prepareSREMEqFold optimization doesn't crash on scalable
+; vector types. RVV doesn't have ROTR or ROTL operations so the optimization
+; itself doesn't kick in.
+define <vscale x 4 x i1> @srem_eq_fold_nxv4i8(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: srem_eq_fold_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 43
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, 6
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v25, v8, v25
+; CHECK-NEXT:    vmseq.vi v0, v25, 0
+; CHECK-NEXT:    ret
+  %head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
+  %splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %rem = srem <vscale x 4 x i8> %va, %splat_six
+
+  %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
+  ret <vscale x 4 x i1> %cc
+}

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v12, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v12, v28, 7
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v24, v8, 0
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 7
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v12, v28, 15
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vsrl.vi v24, v16, 15
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vsub.vv v25, v25, v8
+; CHECK-NEXT:    vsra.vi v26, v25, 2
+; CHECK-NEXT:    vsrl.vi v25, v25, 31
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vsub.vv v26, v26, v8
+; CHECK-NEXT:    vsra.vi v28, v26, 2
+; CHECK-NEXT:    vsrl.vi v26, v26, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vsub.vv v28, v28, v8
+; CHECK-NEXT:    vsra.vi v12, v28, 2
+; CHECK-NEXT:    vsrl.vi v28, v28, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v16, v16, v8
+; CHECK-NEXT:    vsra.vi v24, v16, 2
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vmulh.vv v25, v8, v25
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vmulh.vv v26, v8, v26
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v12, a1
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vor.vv v28, v12, v28
+; CHECK-NEXT:    vmulh.vv v28, v8, v28
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v12, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 748983
+; CHECK-NEXT:    addi a0, a0, -586
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmv.v.x v16, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    lui a1, 898779
+; CHECK-NEXT:    addi a1, a1, 1755
+; CHECK-NEXT:    vmv.v.x v24, a1
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vor.vv v16, v24, v16
+; CHECK-NEXT:    vmulh.vv v16, v8, v16
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v24, v16, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 7
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 7
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v12, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v12, v28, 7
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v24, v8, 0
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 7
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = srem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v25, v25, 1
+; CHECK-NEXT:    vsrl.vi v26, v25, 15
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v26, v26, 1
+; CHECK-NEXT:    vsrl.vi v28, v26, 15
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v28, v28, 1
+; CHECK-NEXT:    vsrl.vi v12, v28, 15
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vsrl.vi v24, v16, 15
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vrsub.vi v26, v8, 0
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsra.vi v25, v25, 2
+; CHECK-NEXT:    vsrl.vi v26, v25, 31
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vrsub.vi v28, v8, 0
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsra.vi v26, v26, 2
+; CHECK-NEXT:    vsrl.vi v28, v26, 31
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vrsub.vi v12, v8, 0
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsra.vi v28, v28, 2
+; CHECK-NEXT:    vsrl.vi v12, v28, 31
+; CHECK-NEXT:    vand.vi v12, v12, -1
+; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vrsub.vi v24, v8, 0
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 31
+; CHECK-NEXT:    vand.vi v24, v24, -1
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v25, v8, a0
+; CHECK-NEXT:    vadd.vi v25, v25, 0
+; CHECK-NEXT:    vsra.vi v26, v25, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v25, v25, a0
+; CHECK-NEXT:    vand.vi v25, v25, -1
+; CHECK-NEXT:    vadd.vv v25, v26, v25
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v26, v8, a0
+; CHECK-NEXT:    vadd.vi v26, v26, 0
+; CHECK-NEXT:    vsra.vi v28, v26, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vand.vi v26, v26, -1
+; CHECK-NEXT:    vadd.vv v26, v28, v26
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v28, v8, a0
+; CHECK-NEXT:    vadd.vi v28, v28, 0
+; CHECK-NEXT:    vsra.vi v12, v28, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vand.vi v28, v28, -1
+; CHECK-NEXT:    vadd.vv v28, v12, v28
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 1029851
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    slli a0, a0, 12
+; CHECK-NEXT:    addi a0, a0, 1755
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vadd.vi v16, v16, 0
+; CHECK-NEXT:    vsra.vi v24, v16, 1
+; CHECK-NEXT:    addi a0, zero, 63
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    vadd.vv v16, v24, v16
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 29
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    vsrl.vi v24, v24, 29
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a0
+; CHECK-NEXT:    vmv.v.i v27, 1
+; CHECK-NEXT:    vsll.vx v27, v27, a0
+; CHECK-NEXT:    vsrl.vx v27, v27, a0
+; CHECK-NEXT:    vor.vv v26, v27, v26
+; CHECK-NEXT:    vmulhu.vv v26, v8, v26
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a0
+; CHECK-NEXT:    vmv.v.i v30, 1
+; CHECK-NEXT:    vsll.vx v30, v30, a0
+; CHECK-NEXT:    vsrl.vx v30, v30, a0
+; CHECK-NEXT:    vor.vv v28, v30, v28
+; CHECK-NEXT:    vmulhu.vv v28, v8, v28
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v12, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v12, v12, a0
+; CHECK-NEXT:    vmv.v.i v16, 1
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    vor.vv v12, v16, v12
+; CHECK-NEXT:    vmulhu.vv v12, v8, v12
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsll.vx v24, v24, a0
+; CHECK-NEXT:    vmv.v.i v0, 1
+; CHECK-NEXT:    vsll.vx v0, v0, a0
+; CHECK-NEXT:    vsrl.vx v0, v0, a0
+; CHECK-NEXT:    vor.vv v24, v0, v24
+; CHECK-NEXT:    vmulhu.vv v24, v8, v24
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 5
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 5
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 5
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vremu_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    addi a0, zero, 33
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 5
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = urem <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc
 }
 
 define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 13
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 13
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 13
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
 ; CHECK-LABEL: vremu_vi_nxv32i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
   ret <vscale x 32 x i16> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v25, v8, a0
+; CHECK-NEXT:    vsrl.vi v25, v25, 29
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmseq.vi v0, v26, -7
+; CHECK-NEXT:    vmerge.vvm v25, v25, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    vsrl.vi v26, v26, 29
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmseq.vi v0, v28, -7
+; CHECK-NEXT:    vmerge.vvm v26, v26, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    vsrl.vi v28, v28, 29
+; CHECK-NEXT:    vmv.v.i v12, 1
+; CHECK-NEXT:    vmseq.vi v0, v12, -7
+; CHECK-NEXT:    vmerge.vvm v28, v28, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vremu_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
+; CHECK-NEXT:    vmv.v.i v24, 1
+; CHECK-NEXT:    vmseq.vi v0, v24, -7
+; CHECK-NEXT:    vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv1i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v26, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v26, v26, a0
+; CHECK-NEXT:    vmseq.vi v0, v25, 1
+; CHECK-NEXT:    vmerge.vvm v25, v26, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v25, v25, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv2i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v28, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v28, v28, a0
+; CHECK-NEXT:    vmseq.vi v0, v26, 1
+; CHECK-NEXT:    vmerge.vvm v26, v28, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v26, v26, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv4i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v12, v12, a0
+; CHECK-NEXT:    vmseq.vi v0, v28, 1
+; CHECK-NEXT:    vmerge.vvm v28, v12, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v28, v28, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
 ; CHECK-LABEL: vremu_vi_nxv8i64_0:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v16, -7
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    slli a0, a0, 61
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vmulhu.vx v24, v8, a0
+; CHECK-NEXT:    addi a0, zero, 61
+; CHECK-NEXT:    vsrl.vx v24, v24, a0
+; CHECK-NEXT:    vmseq.vi v0, v16, 1
+; CHECK-NEXT:    vmerge.vvm v16, v24, v8, v0
 ; CHECK-NEXT:    addi a0, zero, -7
-; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
-; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    vmul.vx v16, v16, a0
+; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }