In D76720#1947128, @efriedma wrote:

I'd like to see better test coverage here. At least, a case that can't be promoted, and a case where a scalable alloca lands on the worklist despite the check in SROA::runImpl.

• Add test for unpromotable scalable alloca.
• Rename %pg -> %vec in <vscale x 16 x i8> test.

Fix bug in branch where allocas with scalable types that aren’t promotable could still be added to worklist and subsequently passed to runOnAlloca where asserts would be triggered as this is now fixed-width. Thanks for spotting @efriedma.

Thanks for the comments @ctetreau! I've updated the patch.

• Removed isScalableVectorTy and replaced uses in SROA with isa<VectorType> and cast<VectorType>(VecTy)->isScalable().

• Run mem2reg for scalable types from SROA.
• Fix warning warning: inline function 'llvm::Type::getVectorIsScalable' is not defined reported by Harbor by moving implementation to Type.cpp.

I updated the tests to remove the dependency on sve.tuple.get intrinsic whilst we investigate an issue there, the individual tuple vectors are now passed as arguments to the functions. Thanks for review @efriedma!

In D76720#1939896, @efriedma wrote:

We want SROA to at least run mem2reg on scalable vectors, since we don't run mem2reg separately. This is important for C code using SVE intrinsics.

In D76720#1939896, @efriedma wrote:

We want SROA to at least run mem2reg on scalable vectors, since we don't run mem2reg separately. This is important for C code using SVE intrinsics.

Thanks for reviewing Eli!

Thanks for the comments @fpetrogalli! I'll update this patch to address your comments.

In D75672#1907847, @efriedma wrote:

Please post patches with full context (-U10000)

Remove check for isScalableVector in getVectorNumElements.

Added full context.

Added context.

Fix warnings reported by Harbor.

Fix warnings reported by Harbor.

Thanks for the patch @dancgr but these intrinsics have already been implemented in D74912. @sdesmalen shared a spreadsheet [1] with the mailing list to coordinate the intrinsics upstreaming, it's probably not as useful now given they're almost all implemented but you might find it useful if you haven't seen it already.

Remove change to lower SPLAT_VECTOR of i1s to pfalse and update test.

• Fix zeroing.
• Update tests.

• Explicitly zero lanes when converting to svbool_t.

LGTM

Included a test we have downstream of a ptest feeding a compare/branch to address Eli's comment.

@dancgr Thanks for the patch! LGTM other than a minor nit (and Eli's comment).

Use ImmArg in intrinsic definition.

Add assert in custom lowering of INTRINSIC_WO_CHAIN for types that aren’t MVT::i8 or MVT::i16.

• Refactored SelectRDVLImm and SelectShiftImm into same function by adding a extra template argument for Shift.
• Added default to switch in IsSVECntIntrinsic

In D71298#1778345, @efriedma wrote:

On a sort of related note, AArch64ISelLowering.cpp says that MVT::nxv1f32 and MVT::nxv1f64 are also legal? Do we plan to implement isel patterns for them?

Refactor switch.