• Refactored SelectRDVLImm and SelectShiftImm into same function by adding a extra template argument for Shift.
• Added default to switch in IsSVECntIntrinsic

In D71298#1778345, @efriedma wrote:

On a sort of related note, AArch64ISelLowering.cpp says that MVT::nxv1f32 and MVT::nxv1f64 are also legal? Do we plan to implement isel patterns for them?

Refactor switch.

Added check to do nothing in combine if before legalisation.

Remove IR patterns for non-immediate forms.

In D70889#1769773, @efriedma wrote:

No testcases for the "IR" (setcc) patterns?

SVE while intrinsics have been added in D69059, updated this patch to only add SVE2 while intrinsics.

Use LLVMMatchType in CNTP intrinsic definition.

@mgudim I've created a patch (D70909) also implementing these intrinsics but I was unaware of this patch, sorry about that. Can this be merged now? I can update D70909 to only add the SVE2 intrinsics .

LGTM

Looks like a pretty straightforward change. Might be worth waiting a day or so before committing incase anyone else has any comments.

• Rebased since parent patch landed.
• Moved SVE comment after @greened suggestion.

• Used existing masked.load intrinsic in .ll test that checks the verifier catches bad type when passing a fixed-width vector where a scalable is expected.
• Removed definition of abs and neg intrinsics that were previously used in the above test, these are implemented in the follow-up patch.
• Updated call to CreateIntrinsic in IRBuilderTest to make types argument empty for call to fp-convert intrinsic, only required for overloaded types.

In D65931#1635304, @RKSimon wrote:

Is it worth adding in ISD::ABS support here ?

@greened sorry for the delayed response, thanks for taking a look at this.

• Moved the intrinsic implementation for abs/neg (without codegen) from D65931 so this patch can be tested.
• Added tests for IRBuilder to test scalable vectors work as expected when using intrinsics through the IRBuilder interface. This required implementing an intrinsic that is explicitly defined with scalable vectors, e.g. LLVMType<nxv4i32>, an SVE floating-point convert intrinsic was used for this. Also tested the behaviour of the overloaded type LLVMScalarOrSameVectorWidth with scalable vectors using the existing masked load intrinsic.
• Replace uses of getNumElements with getElementCount when handling intrinsic type LLVMScalarOrSameVectorWidth so it can correctly support scalable vectors.
• Added an .ll test to test the Verifier catches a bad intrinsic argument when passing a fixed-width predicate (mask) to the abs intrinsic where a scalable is expected.

In D65930#1620641, @sdesmalen wrote:

Specifically to assert that passing a fixed-width vector where a scalable vector is expected (and vice-versa), fails.

I've posted a follow-up patch (D65931) to Phabricator that tests this functionality by implementing intrinsics for a couple of SVE arithmetic instructions.

@ostannard Thanks for review!

• Improved tests
• Fixed up comments

In D65385#1604643, @rengolin wrote:

Right, ArchExtKind was supposed to be shared between Arm and AArch64, but that ship has sailed a long time ago. LGTM, thanks!