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- User Since
- Jun 9 2016, 6:44 PM (391 w, 1 d)
Sep 7 2023
I can help land this patch and the baseline test.
Just give it more hours in case other people catch anything different.
Aug 24 2023
This is causing compilation failure in https://github.com/llvm/llvm-project/issues/64971
Feb 16 2023
Addressed review comments, also clean out "ISD::MemIndexedMode &AM" from getIndexedAddressParts().
Feb 15 2023
Thanks Eli for the feedbacks!
Feb 14 2023
Dumped -debug-only=isel,dagcombine for a few targets (armv7a, aarch64, x86_64, riscv64) to see what's going on. Here is what I found:
Feb 10 2023
Test case was reduced from internal benchmark. Assuming we would run into similar issues for post-dec addressing mode.
If needed I can try to synthesize a test for post-dec.
Jan 13 2023
Nov 17 2022
The test attached no longer trigger assertion "Attempting to place block with unscheduled predecessors in worklist.".
I am not currently active on this issue.
I also don't have much experience in MachineBlockPlacement.
Feb 10 2022
Thanks @fhahn , stack accesses are not needed. I just clean them in https://reviews.llvm.org/rG19302cd7a449
Feb 9 2022
Thanks Eli for the feedbacks!
Exclude undef from overlap diagnosis.
Feb 8 2022
Take test mir attached test/CodeGen/AArch64/stp-opt-with-renaming-crash.mir
run with llc -run-pass=aarch64-ldst-opt -mtriple=aarch64 -verify-machineinstrs
Jan 31 2022
Thank you guys for looking into this!
Nov 22 2021
Thanks Sanjay for the review!
I did another local run for fadd, with "--disable-undef-input" it finish within a minute.
When removing "--disable-undef-input", it's taking about an hour now, still not finished.
Nov 17 2021
Rebased, and a gentle ping ?
Nov 11 2021
Update on overnight run for fdiv
Nov 10 2021
Addressed review comments.
Pre-commit baseline test test/Transforms/InstCombine/select-binop-foldable-floating-point.ll
Nov 9 2021
Thanks Sanjay for the comments, I will update unit test as suggested.
Nov 8 2021
Take test.ll attached.
Sep 10 2021
Sep 9 2021
Jul 13 2021
I think this fix looks right, but wait a bit for @reames , in case he caught anything unusual ?
Jun 29 2021
Another note on LSRInstance::GenerateReassociationsImpl() where 1*reg is created, eventually trigger this assertion.
Jun 22 2021
Ideally we should reject early when stride is zero, but in this case we won't be able to detect this early since stride zero is in a form of add expression.
Jun 14 2021
Jun 11 2021
Thanks @sdesmalen for the review! Happy to help out! ;)
Jun 10 2021
To be more conservative, added checking IgnoreSignificantBits || isMulSExtable(MulRHS, SE) to MulRHS as well.
Jun 9 2021
Thanks @efriedma @dmgreen for the feedbacks!
Addressed review comments, please let me know if there are anything I missed ?
Jun 8 2021
Mar 31 2021
Mar 30 2021
Update diff to use SetVector.
Thank you for the feedback!
Addressed review comments.
Mar 29 2021
Thank you for the review! @wenlei , could you also help take a look at D99544 and D99549. They are in a similar vein. Thanks a lot!
Feb 17 2021
Thanks @frasercrmck for helping! Appreciate it!
Feb 16 2021
This is crashing SVE target lowering with "LLVM ERROR: Cannot select: t23: nxv4i32 = mulhu t9, t34"
Let me know if there is a way of fixing it?
Feb 5 2021
Feb 4 2021
Thanks David and Paul for the reviews!
Feb 3 2021
Take test function @sext_inreg
run: llc -mtriple=aarch64-linux-gnu -mattr=+sve < test/CodeGen/AArch64/DAGCombine_vscale.ll
Dec 8 2020
Dec 7 2020
Thanks for the feedback!
Test cases for vector splitting added. Also fix the warning message caused by extracting subvector.
Dec 3 2020
Oct 23 2020
Thanks @sdesmalen for the review!
Fixed in the commit patch.
Oct 21 2020
Oct 20 2020
Current upstream mis-compile, take t.ll , run "llc -mtriple=aarch64-linux-gnu -mattr=+sve < t.ll"
Sep 18 2020
Current upstream crash with test attached.
Sep 15 2020
Sep 14 2020
Thanks guys for the feedback!
Addressed review comments.