User Details
- User Since
- Jun 9 2016, 6:44 PM (322 w, 5 d)
Feb 10 2022
Thanks @fhahn , stack accesses are not needed. I just clean them in https://reviews.llvm.org/rG19302cd7a449
Feb 9 2022
Thanks Eli for the feedbacks!
Exclude undef from overlap diagnosis.
Feb 8 2022
Take test mir attached test/CodeGen/AArch64/stp-opt-with-renaming-crash.mir
run with llc -run-pass=aarch64-ldst-opt -mtriple=aarch64 -verify-machineinstrs
Jan 31 2022
Thank you guys for looking into this!
Nov 22 2021
Thanks Sanjay for the review!
I did another local run for fadd, with "--disable-undef-input" it finish within a minute.
When removing "--disable-undef-input", it's taking about an hour now, still not finished.
Nov 17 2021
Rebased, and a gentle ping ?
Nov 11 2021
Update on overnight run for fdiv
Nov 10 2021
Addressed review comments.
Pre-commit baseline test test/Transforms/InstCombine/select-binop-foldable-floating-point.ll
Nov 9 2021
Thanks Sanjay for the comments, I will update unit test as suggested.
Nov 8 2021
Take test.ll attached.
Sep 10 2021
Sep 9 2021
Jul 13 2021
I think this fix looks right, but wait a bit for @reames , in case he caught anything unusual ?
Jun 29 2021
Another note on LSRInstance::GenerateReassociationsImpl() where 1*reg is created, eventually trigger this assertion.
Jun 22 2021
Ideally we should reject early when stride is zero, but in this case we won't be able to detect this early since stride zero is in a form of add expression.
Jun 14 2021
Jun 11 2021
Thanks @sdesmalen for the review! Happy to help out! ;)
Jun 10 2021
To be more conservative, added checking IgnoreSignificantBits || isMulSExtable(MulRHS, SE) to MulRHS as well.
Jun 9 2021
Thanks @efriedma @dmgreen for the feedbacks!
Addressed review comments, please let me know if there are anything I missed ?
Jun 8 2021
Mar 31 2021
Mar 30 2021
Update diff to use SetVector.
Thank you for the feedback!
Addressed review comments.
Mar 29 2021
Thank you for the review! @wenlei , could you also help take a look at D99544 and D99549. They are in a similar vein. Thanks a lot!
Feb 17 2021
Thanks @frasercrmck for helping! Appreciate it!
Feb 16 2021
This is crashing SVE target lowering with "LLVM ERROR: Cannot select: t23: nxv4i32 = mulhu t9, t34"
Let me know if there is a way of fixing it?
Feb 5 2021
Feb 4 2021
Thanks David and Paul for the reviews!
Feb 3 2021
Take test function @sext_inreg
run: llc -mtriple=aarch64-linux-gnu -mattr=+sve < test/CodeGen/AArch64/DAGCombine_vscale.ll
Dec 8 2020
Dec 7 2020
Thanks for the feedback!
Test cases for vector splitting added. Also fix the warning message caused by extracting subvector.
Dec 3 2020
Oct 23 2020
Thanks @sdesmalen for the review!
Fixed in the commit patch.
Oct 21 2020
Oct 20 2020
Current upstream mis-compile, take t.ll , run "llc -mtriple=aarch64-linux-gnu -mattr=+sve < t.ll"
Sep 18 2020
Current upstream crash with test attached.
Sep 15 2020
Sep 14 2020
Thanks guys for the feedback!
Addressed review comments.
Sep 11 2020
Sep 2 2020
Thanks Sanjay for the review!
Addressed review comments.
Sep 1 2020
Aug 10 2020
I don't think that's the intention of this specific test given the name insert_extract_element_same_vec_idx_2. And also the unused parameter %a.
This is failing due after a local change to instsimplify and I think the test maybe isn't testing what it wants to test?
why do we need this change?
insert element into undef is common to construct a vector, being fixed or scalable.
Jul 31 2020
Thanks @paulwalker-arm for the review!
I have moved the new tests into sve-masked-ldst-nonext.ll in the commit.
Jun 25 2020
Hey @fpetrogalli @sdesmalen , any updates on this patch? This should be the last one to commit for structure load? Or are we using different approach?
Jun 17 2020
Jun 12 2020
Jun 4 2020
Jun 3 2020
Thanks Eli for pointing this out!