Thank you @bryanpkc, this LGTM

Hi @bryanpkc, thank you for updating this patch & applying the previous review comments here too.
I just have a couple of minor suggestions:

LGTM!

Thank you for checking and removing EltTypeBool128. I think you have addressed all of the other comments on this patch too, so it looks good to me!

Fixed the immediates used in the *za64.lane.vg4x1 tests so that they are within the correct range for VectorIndexH32b.

• Changed sme2_mla_ll_array_index_64b to use VectorIndexH32b_timm

• Added a sme2_mla_ll_array_vg24_single multiclass to reduce duplication in sme2_mla_ll_array_vg2_single & sme2_mla_ll_array_vg4_single
• Removed -mattr=+sve from sme2-intrinsics-mlall.ll

LGTM!

LGTM

LGTM!

• Renamed the sme2_bfp_mopx_tile multiclass to sme2_int_bmopx_tile
• Removed the -mattr=+sve and -mattr=+bf16 flags from the RUN line in sme2-intrinsics-mop.ll

• Added an %unused argument to the tests to ensure the multi-vector lists start with a multiple of 2 or 4.

• Replace ZPR2/ZPR4 with ZPR2Mul2/ZPR4Mul4 in SME2_Sat_Shift_VG2_Pat & SME2_Sat_Shift_VG4_Pat.
• Removed unnecessary flags from the RUN lines of the tests.

• Added a new first argument (%unused) to the tests in sme2-intrinsics-sqdmulh.ll, to ensure the multi-vector input starts on a multiple of 2 or 4.

Thank you for the changes, @CarolineConcatto!

• Added multi-vector to ZA intrinsic tests with non-zero slices

Rebased patch.

LGTM!

• Renamed the intrinsic class names in IntrinsicsAArch64.td to SME2_Matrix_TileVector*/SME2_ZA_ArrayVector*
• Changed SelectSMETile to remove extra braces & fix indentation
• Replaced the llvm_unreachable in SelectMultiVectorMove with return false
• Removed adds of zero from tests

LGTM!

Hi Carol,
I just spotted one issue with the SVE2p1_Cvt_VG2_Pat class, but otherwise I think this patch looks good!

• Updated the multiclasses changed in SMEInstrFormats.td to use VectorIndexS32b_timm/VectorIndexD32b_timm consistently.
• Removed the _regclass tests for the multiple and single vector intrinsics. Added similar tests for the multiple & indexed vector intrinisics instead.

LGTM!

Gentle ping :)

• Changed LowerCall to allocate a lazy-save buffer and TPIDR2 block if RequiresLazySave is true but the TPIDR2 object has not yet been set in AArch64FunctionInfo. This is possible where requiresLazySave finds no calls in the function, but the function contains an instruction which will be lowered to a lib call (e.g. a 128 bit floating-point add).
• Renamed requiresLazySave to requiresBufferForLazySave.
• Added a function for allocating the buffer & TPIDR2 object (allocateLazySaveBuffer).
• Added a test case to sme-shared-za-interface.ll for the scenario described above.

Commandeering this patch to try and address review comments while @sdesmalen is away.

Hi Carol
I think you have addressed all of the comments that were previously left here, so other than a couple of minor comments from me I think this patch looks good!

Hi @david-arm, this change looks reasonable to me. Can you please wait a day or so before landing, just to make sure the other reviewers have a chance to look at it again?

This change looks good to me!

Thank you @david-arm, this LGTM

LGTM!

LGTM!

LGTM

LGTM

LGTM