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kmclaughlin (Kerry McLaughlin)
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User Since
Jul 10 2019, 8:51 AM (149 w, 5 d)

Recent Activity

Mon, May 9

kmclaughlin accepted D125001: [NFC][LoopVectorize] Add SVE test for tail-folding combined with interleaving.

LGTM

Mon, May 9, 3:19 AM · Restricted Project, Restricted Project

Thu, Apr 28

kmclaughlin accepted D123326: [DAGCombiner] Stop invalid sign conversion in refineIndexType..

LGTM

Thu, Apr 28, 5:49 AM · Restricted Project, Restricted Project
kmclaughlin accepted D123222: [DAGCombiner][SVE] Ensure MGATHER/MSCATTER addressing mode combines preserve index scaling.

LGTM!

Thu, Apr 28, 4:06 AM · Restricted Project, Restricted Project
kmclaughlin accepted D123318: [SVE][ISel] Ensure explicit gather/scatter offset extension isn't lost..

LGTM!

Thu, Apr 28, 1:51 AM · Restricted Project, Restricted Project

Mar 16 2022

kmclaughlin planned changes to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
Mar 16 2022, 6:34 AM · Restricted Project, Restricted Project

Mar 10 2022

kmclaughlin updated the diff for D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
  • Renamed VecVT to MemVT in the preferGatherScatter function.
  • Fixed formatting issues.
Mar 10 2022, 9:34 AM · Restricted Project, Restricted Project
kmclaughlin added a comment to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.

Hi @rscottmanley, thank you for taking a look at this patch.

Mar 10 2022, 6:05 AM · Restricted Project, Restricted Project
kmclaughlin added inline comments to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
Mar 10 2022, 5:59 AM · Restricted Project, Restricted Project
kmclaughlin updated the diff for D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
  • Added the preferGatherScatter function to AArch64Subtarget, which checks if a gather/scatter with a given type & stride is preferable to contiguous loads/stores on the current target.
  • Create new machine memory operands for the contiguous loads/stores instead of reusing the mem operand from the gather/scatter.
  • Added tests for floating-point gathers & scatters, and extending & truncating gathers/scatters.
Mar 10 2022, 5:59 AM · Restricted Project, Restricted Project

Mar 7 2022

kmclaughlin added a comment to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.

Did you try using ld2/st2? I guess the problem is that it accesses too many bytes?

Mar 7 2022, 7:37 AM · Restricted Project, Restricted Project
kmclaughlin updated the diff for D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
  • Moved the changes to performMaskedGatherScatterCombine into a new function, tryCombineToMaskedLoadStore.
  • Removed the switch statement and use of getSimpleVT(), using if-else statements which check MemVT for supported types instead.
  • Removed the restriction that the mask opcode of the gather/scatter is not an extract_subvector.
Mar 7 2022, 7:36 AM · Restricted Project, Restricted Project

Mar 3 2022

kmclaughlin requested review of D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
Mar 3 2022, 8:11 AM · Restricted Project, Restricted Project

Feb 22 2022

kmclaughlin committed rG12fb133eba81: [LoopVectorize] Support conditional in-loop vector reductions (authored by kmclaughlin).
[LoopVectorize] Support conditional in-loop vector reductions
Feb 22 2022, 4:05 AM
kmclaughlin closed D117580: [LoopVectorize] Support conditional in-loop vector reductions.
Feb 22 2022, 4:04 AM · Restricted Project

Feb 21 2022

kmclaughlin added inline comments to D117580: [LoopVectorize] Support conditional in-loop vector reductions.
Feb 21 2022, 8:13 AM · Restricted Project
kmclaughlin updated the diff for D117580: [LoopVectorize] Support conditional in-loop vector reductions.
  • Changes to tryToBlend() so that all incoming values of the Phi are checked for in-loop reductions.
  • Added an assert to tryToBlend() that the number of incoming values to the Phi is 2 if an in-loop reduction is found. Also added an assert that only one of the incoming values is an in-loop reduction.
  • Reworded the comment describing the number of uses of Phi in getReductionOpChain().
Feb 21 2022, 8:12 AM · Restricted Project

Feb 17 2022

kmclaughlin committed rGfc1b21228e39: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo (authored by kmclaughlin).
[AArch64][SVE] Add structured load/store opcodes to getMemOpInfo
Feb 17 2022, 9:10 AM
kmclaughlin closed D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
Feb 17 2022, 9:09 AM · Restricted Project
kmclaughlin updated the diff for D117580: [LoopVectorize] Support conditional in-loop vector reductions.
  • Moved the and reduction in the @unconditional_and test into the if.then block.
Feb 17 2022, 8:47 AM · Restricted Project
kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • Reverted the previous changes which set Scale to TypeSize::Scalable(16) for all opcodes.
  • Corrected the Min & Max values added to getMemOpInfo, as these should be the indices -8 to 7 for all structured loads & stores.
Feb 17 2022, 6:24 AM · Restricted Project

Feb 15 2022

kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • Changed Scale to TypeSize::Scalable(16) for all opcodes added to getMemOpInfo, fixing incorrect scaling when the immediate is out of range
Feb 15 2022, 9:40 AM · Restricted Project

Feb 14 2022

kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • Moved all structured load tests into sve-ldN.mir & all store tests to sve-stN.mir
Feb 14 2022, 9:09 AM · Restricted Project
kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • After some discussion about the tests in this patch offline, I have removed ldN-reg-imm-alloca.ll & stN-reg-imm-alloca.ll in favour of adding mir tests.
  • Removed newlines introduced in AArch64InstrInfo.cpp.
Feb 14 2022, 7:44 AM · Restricted Project

Feb 11 2022

kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • Changed fixed-width allocas used in the tests to scalable.
  • Added tests for offsets which are at the min/max range & tests outside the min/max range.
  • Added the nounwind attribute to all tests.
  • Changed the tests for non-zero offsets to remove the second alloca.
Feb 11 2022, 12:17 PM · Restricted Project

Feb 10 2022

kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • Removed unnecessary stores from tests in stN-reg-imm-alloca.ll which use only one alloca.
  • Increased the number of elements for allocas in a number of tests in which a gep was attempting to access data beyond the allocated space.
Feb 10 2022, 8:14 AM · Restricted Project
kmclaughlin updated the diff for D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
  • Ensure the correct amount of space is allocated in each test by increasing the size of the allocas.
  • Added a store to each of the tests to ensure the allocas aren't optimised away.
  • Moved vscale_range into the definitions of the tests.
Feb 10 2022, 6:46 AM · Restricted Project

Feb 9 2022

kmclaughlin requested review of D119338: [AArch64][SVE] Add structured load/store opcodes to getMemOpInfo.
Feb 9 2022, 7:01 AM · Restricted Project

Feb 4 2022

kmclaughlin added a comment to D117307: [LoopVectorize] Only check for ordered reductions if the op chain was found.

Hi @fhahn, there was a test added in D114002 which covers the changes here. This is just a follow up from some discussion on that patch.

Feb 4 2022, 9:52 AM · Restricted Project
kmclaughlin added inline comments to D117580: [LoopVectorize] Support conditional in-loop vector reductions.
Feb 4 2022, 9:46 AM · Restricted Project
kmclaughlin updated the diff for D117580: [LoopVectorize] Support conditional in-loop vector reductions.
  • Renamed the @multiple_cond_ands test to @unconditional_and.
  • Removed the -instcombine & -dce flags from scalable-reduction-inloop-cond.ll.
  • Simplified the CHECK lines for the negative tests in reduction-inloop-cond.ll.
Feb 4 2022, 9:45 AM · Restricted Project

Feb 3 2022

kmclaughlin added a comment to D117580: [LoopVectorize] Support conditional in-loop vector reductions.

Thank you for reviewing these changes, @david-arm!

Feb 3 2022, 10:05 AM · Restricted Project
kmclaughlin updated the diff for D117580: [LoopVectorize] Support conditional in-loop vector reductions.
  • Changed getNextInstruction to iterate over Cur->users() and handle Phi nodes found by moving to the next user, similar to ICmp/FCmp.
  • Removed the dyn_cast<PHINode>(Cur) == LoopExitInstr block as Phis are now handled by getNextInstruction.
  • Added tests for various scenarios involving chained reductions where we should not vectorise with in-loop reductions.
Feb 3 2022, 10:02 AM · Restricted Project

Jan 31 2022

kmclaughlin committed rG002b944dfa3d: [SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca() (authored by kmclaughlin).
[SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca()
Jan 31 2022, 6:38 AM
kmclaughlin closed D118372: [SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca().
Jan 31 2022, 6:38 AM · Restricted Project

Jan 28 2022

kmclaughlin updated the diff for D118372: [SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca().
  • Generated the check lines in sve-alloca.ll with update_llc_test_checks.py
  • Use TySize.getFixedValue() when TySize is not scalable
Jan 28 2022, 6:06 AM · Restricted Project
kmclaughlin updated the diff for D118372: [SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca().
  • Fixed AllocSize to ensure we multiply by vscale for scalable vectors
  • Added CHECK lines to the test in sve-alloca.ll
Jan 28 2022, 3:46 AM · Restricted Project

Jan 27 2022

kmclaughlin requested review of D118372: [SVE] Fix TypeSize->uint64_t implicit conversion in visitAlloca().
Jan 27 2022, 7:59 AM · Restricted Project

Jan 26 2022

kmclaughlin accepted D118073: [IVDescriptor] Get the exact FP instruction that does not allow reordering.
Jan 26 2022, 9:54 AM · Restricted Project

Jan 25 2022

kmclaughlin accepted D118073: [IVDescriptor] Get the exact FP instruction that does not allow reordering.

Thank you for this fix @congzhe, LGTM! I have just added one minor comment on the new test.

Jan 25 2022, 9:32 AM · Restricted Project

Jan 24 2022

kmclaughlin committed rG8082ab2fc391: [LoopVectorize] Support epilogue vectorisation of loops with reductions (authored by kmclaughlin).
[LoopVectorize] Support epilogue vectorisation of loops with reductions
Jan 24 2022, 4:04 AM
kmclaughlin closed D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
Jan 24 2022, 4:03 AM · Restricted Project

Jan 21 2022

kmclaughlin updated the diff for D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
  • Added StartVal as an external def to BestEpiPlan
  • Updated pr35432.ll without auto-generating the check lines
Jan 21 2022, 3:41 AM · Restricted Project

Jan 19 2022

kmclaughlin updated the diff for D117307: [LoopVectorize] Only check for ordered reductions if the op chain was found.
  • Renamed getReductionOpChain -> findReductionOpChain
  • Added !LoopExitInstr->hasNUses(2) back into findReductionOpChain
Jan 19 2022, 9:33 AM · Restricted Project
kmclaughlin added inline comments to D117578: [LoopVectorize] Test in-loop reductions with tail folding for scalable vectors.
Jan 19 2022, 6:41 AM · Restricted Project
kmclaughlin committed rGc740a07863b4: [LoopVectorize] Test in-loop reductions with tail folding for scalable vectors (authored by kmclaughlin).
[LoopVectorize] Test in-loop reductions with tail folding for scalable vectors
Jan 19 2022, 6:38 AM
kmclaughlin closed D117578: [LoopVectorize] Test in-loop reductions with tail folding for scalable vectors.
Jan 19 2022, 6:38 AM · Restricted Project

Jan 18 2022

kmclaughlin requested review of D117580: [LoopVectorize] Support conditional in-loop vector reductions.
Jan 18 2022, 10:03 AM · Restricted Project
kmclaughlin requested review of D117578: [LoopVectorize] Test in-loop reductions with tail folding for scalable vectors.
Jan 18 2022, 9:52 AM · Restricted Project

Jan 17 2022

kmclaughlin updated the diff for D117307: [LoopVectorize] Only check for ordered reductions if the op chain was found.
  • Moved getReductionOpChain back to the original location in IVDescriptors.cpp
Jan 17 2022, 8:17 AM · Restricted Project
kmclaughlin added inline comments to D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
Jan 17 2022, 6:16 AM · Restricted Project
kmclaughlin updated the diff for D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
  • Renamed ResumeValues -> ReductionResumeValues
  • Removed several tests which were not covering anything new from this patch compared to other tests
Jan 17 2022, 6:16 AM · Restricted Project

Jan 14 2022

kmclaughlin requested review of D117307: [LoopVectorize] Only check for ordered reductions if the op chain was found.
Jan 14 2022, 6:48 AM · Restricted Project
kmclaughlin accepted D117109: [LoopVectorize][AArch64] Use get.active.lane.mask intrinsic when SVE is enabled.

This seems like a sensible change to me, LGTM!

Jan 14 2022, 6:05 AM · Restricted Project

Jan 13 2022

kmclaughlin added inline comments to D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
Jan 13 2022, 7:05 AM · Restricted Project
kmclaughlin updated the diff for D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
  • Added a test to epilog-vectorization-reductions.ll where the start value of the reduction is also Phi node
Jan 13 2022, 7:03 AM · Restricted Project
kmclaughlin updated the diff for D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
  • Changed getResumeValue to return a PHINode instead of a Value
  • Pass in the RecurrenceDescriptor as a const reference to getResumeValue
  • Assert that the resume value must be found in getResumeValue
Jan 13 2022, 3:23 AM · Restricted Project

Jan 12 2022

kmclaughlin accepted D116644: [NFC][AArch64][CodeGen] Add fixed-width vector tests for get.active.lane.mask.

LGTM

Jan 12 2022, 8:35 AM · Restricted Project
kmclaughlin added a comment to D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.

Thank you for the comments on this patch, @sdesmalen & @bmahjour!

Jan 12 2022, 6:33 AM · Restricted Project
kmclaughlin updated the diff for D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
  • Added a map to associate resume values with RecurrenceDescriptors in the loop
  • Changed the tests to use more meaningful start values
  • Added a test case where there is more than one reduction in the loop
  • Use the start value of the VPReductionPHIRecipe in fixReduction to check if the resume value is a Phi
  • Restructured the changes to fixReduction & createEpilogueVectorizedLoopSkeleton
Jan 12 2022, 6:31 AM · Restricted Project

Jan 10 2022

kmclaughlin requested review of D116928: [LoopVectorize] Support epilogue vectorisation of loops with reductions.
Jan 10 2022, 3:54 AM · Restricted Project

Dec 10 2021

kmclaughlin accepted D115512: [NFC][SVE] Add missing tests for i32 INC/DEC patterns..

Thank you for adding these tests @paulwalker-arm, LGTM

Dec 10 2021, 9:50 AM · Restricted Project

Nov 23 2021

kmclaughlin accepted D111555: [LoopVectorize] Add vector reduction support for fmuladd intrinsic.
Nov 23 2021, 8:48 AM · Restricted Project

Nov 18 2021

kmclaughlin committed rGff64b2933a7d: [LoopVectorize] Check the number of uses of an FAdd before classifying as… (authored by kmclaughlin).
[LoopVectorize] Check the number of uses of an FAdd before classifying as…
Nov 18 2021, 8:44 AM
kmclaughlin closed D114002: [LoopVectorize] Check the number of uses of an FAdd before classifying as ordered.
Nov 18 2021, 8:43 AM · Restricted Project
kmclaughlin added a comment to D114002: [LoopVectorize] Check the number of uses of an FAdd before classifying as ordered.

The underlying issue seems to be that AddReductionVar returns a reduction, whereas getReductionOpChain cannot find the chain. Are there more situations that could happen? Would it be better to somehow detect that getReductionOpChain will fail to find the chain?

Nov 18 2021, 7:01 AM · Restricted Project

Nov 16 2021

kmclaughlin requested review of D114002: [LoopVectorize] Check the number of uses of an FAdd before classifying as ordered.
Nov 16 2021, 7:20 AM · Restricted Project

Nov 15 2021

kmclaughlin accepted D113777: [Analysis] Ensure getTypeLegalizationCost returns a simple VT for TypeScalarizeScalableVector.
Nov 15 2021, 3:54 AM · Restricted Project

Nov 12 2021

kmclaughlin committed rG764782215651: [AArch64][SVE] Remove i1 type from isElementTypeLegalForScalableVector (authored by kmclaughlin).
[AArch64][SVE] Remove i1 type from isElementTypeLegalForScalableVector
Nov 12 2021, 6:25 AM
kmclaughlin closed D113680: [AArch64][SVE] Remove i1 type from isElementTypeLegalForScalableVector.
Nov 12 2021, 6:25 AM · Restricted Project

Nov 11 2021

kmclaughlin requested review of D113680: [AArch64][SVE] Remove i1 type from isElementTypeLegalForScalableVector.
Nov 11 2021, 8:32 AM · Restricted Project

Nov 10 2021

kmclaughlin accepted D113180: [LoopVectorize] Make VPWidenCanonicalIVRecipe::execute work for scalable vectors.

LGTM!

Nov 10 2021, 5:28 AM · Restricted Project
kmclaughlin added a reverting change for rG0d748b4d32cb: [LoopVectorize] Extract the last lane from a uniform store: rG6f16ee5e14a0: Revert "[LoopVectorize] Extract the last lane from a uniform store".
Nov 10 2021, 3:23 AM
kmclaughlin committed rG6f16ee5e14a0: Revert "[LoopVectorize] Extract the last lane from a uniform store" (authored by kmclaughlin).
Revert "[LoopVectorize] Extract the last lane from a uniform store"
Nov 10 2021, 3:23 AM
kmclaughlin added a reverting change for D112725: [LoopVectorize] Extract the last lane from a uniform store: rG6f16ee5e14a0: Revert "[LoopVectorize] Extract the last lane from a uniform store".
Nov 10 2021, 3:23 AM · Restricted Project

Nov 9 2021

kmclaughlin committed rG0d748b4d32cb: [LoopVectorize] Extract the last lane from a uniform store (authored by kmclaughlin).
[LoopVectorize] Extract the last lane from a uniform store
Nov 9 2021, 6:44 AM
kmclaughlin closed D112725: [LoopVectorize] Extract the last lane from a uniform store.
Nov 9 2021, 6:44 AM · Restricted Project

Nov 5 2021

kmclaughlin accepted D113209: [LV] Use VScaleForTuning to fine-tune the cost per lane..

Thanks @sdesmalen, this LGTM!

Nov 5 2021, 3:50 AM · Restricted Project

Nov 4 2021

kmclaughlin added inline comments to D112725: [LoopVectorize] Extract the last lane from a uniform store.
Nov 4 2021, 10:23 AM · Restricted Project
kmclaughlin updated the diff for D112725: [LoopVectorize] Extract the last lane from a uniform store.
  • Add store instructions to the Uniforms list in collectLoopUniforms, instead of the worklist. Added more comments to clarify that instructions in Uniforms may demand the first or last lane.
  • Moved the new tests in sve-uniform-store.ll into sve-inv-store.ll.
  • Removed the CHECK lines from middle.block from @inv_store_i16
Nov 4 2021, 10:22 AM · Restricted Project

Nov 3 2021

kmclaughlin abandoned D113034: [LoopVectorize] Mark store instructions as uniform in collectLoopUniforms.

Merged this with the parent patch, D112725

Nov 3 2021, 10:00 AM · Restricted Project
kmclaughlin added inline comments to D112725: [LoopVectorize] Extract the last lane from a uniform store.
Nov 3 2021, 9:59 AM · Restricted Project
kmclaughlin updated the diff for D112725: [LoopVectorize] Extract the last lane from a uniform store.
  • Merged with D113034, which makes changes to collectLoopUniforms to collect uniform store instructions.
Nov 3 2021, 9:54 AM · Restricted Project

Nov 2 2021

kmclaughlin added inline comments to D112725: [LoopVectorize] Extract the last lane from a uniform store.
Nov 2 2021, 11:25 AM · Restricted Project
kmclaughlin updated the diff for D112725: [LoopVectorize] Extract the last lane from a uniform store.
  • Removed the uniform-store.ll test added in the previous revision.
Nov 2 2021, 10:44 AM · Restricted Project
kmclaughlin requested review of D113034: [LoopVectorize] Mark store instructions as uniform in collectLoopUniforms.
Nov 2 2021, 10:40 AM · Restricted Project

Oct 29 2021

kmclaughlin added inline comments to D112725: [LoopVectorize] Extract the last lane from a uniform store.
Oct 29 2021, 9:19 AM · Restricted Project
kmclaughlin updated the diff for D112725: [LoopVectorize] Extract the last lane from a uniform store.
  • Removed redundant Legal->isUniformMemOp(I) check from setCostBasedWideningDecision
  • Added a comment to VPReplicateRecipe::execute
  • Removed the State.VF.isScalable() check from VPReplicateRecipe::execute & updated the tests affected by this change. Also added a test of uniform stores for fixed-width.
Oct 29 2021, 9:19 AM · Restricted Project

Oct 28 2021

kmclaughlin accepted D112548: [LoopVectorize] Propagate fast-math flags for inloop reductions.

Thank you @RosieSumpter, this patch looks good to me and I think all of the comments have been addressed.

Oct 28 2021, 9:01 AM · Restricted Project
kmclaughlin requested review of D112725: [LoopVectorize] Extract the last lane from a uniform store.
Oct 28 2021, 8:27 AM · Restricted Project

Oct 27 2021

kmclaughlin committed rGf01fafdcd469: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads (authored by kmclaughlin).
[SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads
Oct 27 2021, 6:18 AM
kmclaughlin closed D112320: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads.
Oct 27 2021, 6:18 AM · Restricted Project
kmclaughlin accepted D112610: [LoopVectorize] Change getRuntimeVFAsFloat to use unsigned int->FP conversion.
Oct 27 2021, 3:50 AM · Restricted Project
kmclaughlin accepted D111882: [NFC][LoopVectorize] Change getStepVector to take a Value* for the StartIdx.
Oct 27 2021, 3:49 AM · Restricted Project
kmclaughlin added inline comments to D111882: [NFC][LoopVectorize] Change getStepVector to take a Value* for the StartIdx.
Oct 27 2021, 2:58 AM · Restricted Project

Oct 25 2021

kmclaughlin added a comment to D112320: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads.

Do we know what was the logic to set ExtType to ISD::EXTLOAD?
I don't see that on other parts of the legalisation for Masked load.

Oct 25 2021, 6:33 AM · Restricted Project
kmclaughlin updated the diff for D112320: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads.
  • Pass isExpandingLoad() to getMaskedLoad
Oct 25 2021, 6:29 AM · Restricted Project
kmclaughlin committed rG1f49b71fe5fa: [SVE][CodeGen] Enable reciprocal estimates for scalable fdiv/fsqrt (authored by kmclaughlin).
[SVE][CodeGen] Enable reciprocal estimates for scalable fdiv/fsqrt
Oct 25 2021, 3:31 AM
kmclaughlin closed D111657: [SVE][CodeGen] Enable reciprocal estimates for scalable fdiv/fsqrt.
Oct 25 2021, 3:31 AM · Restricted Project

Oct 22 2021

kmclaughlin requested review of D112320: [SVE][CodeGen] Fix incorrect legalisation of zero-extended masked loads.
Oct 22 2021, 8:26 AM · Restricted Project
kmclaughlin added inline comments to D111657: [SVE][CodeGen] Enable reciprocal estimates for scalable fdiv/fsqrt.
Oct 22 2021, 6:37 AM · Restricted Project