- User Since
- Jul 10 2019, 8:51 AM (193 w, 4 d)
Wed, Mar 15
Thank you @bryanpkc, this LGTM
Tue, Feb 28
Hi @bryanpkc, thank you for updating this patch & applying the previous review comments here too.
I just have a couple of minor suggestions:
Mon, Feb 27
Feb 23 2023
Thank you for checking and removing EltTypeBool128. I think you have addressed all of the other comments on this patch too, so it looks good to me!
Fixed the immediates used in the *za64.lane.vg4x1 tests so that they are within the correct range for VectorIndexH32b.
Feb 21 2023
Feb 20 2023
Feb 16 2023
Feb 15 2023
- Changed sme2_mla_ll_array_index_64b to use VectorIndexH32b_timm
- Added a sme2_mla_ll_array_vg24_single multiclass to reduce duplication in sme2_mla_ll_array_vg2_single & sme2_mla_ll_array_vg4_single
- Removed -mattr=+sve from sme2-intrinsics-mlall.ll
Feb 7 2023
Feb 3 2023
Feb 2 2023
Feb 1 2023
Jan 31 2023
Jan 30 2023
- Renamed the sme2_bfp_mopx_tile multiclass to sme2_int_bmopx_tile
- Removed the -mattr=+sve and -mattr=+bf16 flags from the RUN line in sme2-intrinsics-mop.ll
- Added an %unused argument to the tests to ensure the multi-vector lists start with a multiple of 2 or 4.
Jan 27 2023
Jan 26 2023
Jan 25 2023
- Replace ZPR2/ZPR4 with ZPR2Mul2/ZPR4Mul4 in SME2_Sat_Shift_VG2_Pat & SME2_Sat_Shift_VG4_Pat.
- Removed unnecessary flags from the RUN lines of the tests.
- Added a new first argument (%unused) to the tests in sme2-intrinsics-sqdmulh.ll, to ensure the multi-vector input starts on a multiple of 2 or 4.
Jan 24 2023
Thank you for the changes, @CarolineConcatto!
- Added multi-vector to ZA intrinsic tests with non-zero slices
Jan 23 2023
Jan 20 2023
- Renamed the intrinsic class names in IntrinsicsAArch64.td to SME2_Matrix_TileVector*/SME2_ZA_ArrayVector*
- Changed SelectSMETile to remove extra braces & fix indentation
- Replaced the llvm_unreachable in SelectMultiVectorMove with return false
- Removed adds of zero from tests
I just spotted one issue with the SVE2p1_Cvt_VG2_Pat class, but otherwise I think this patch looks good!
Jan 19 2023
- Updated the multiclasses changed in SMEInstrFormats.td to use VectorIndexS32b_timm/VectorIndexD32b_timm consistently.
- Removed the _regclass tests for the multiple and single vector intrinsics. Added similar tests for the multiple & indexed vector intrinisics instead.
Jan 18 2023
Jan 17 2023
Jan 16 2023
Dec 16 2022
Oct 27 2022
Oct 24 2022
Oct 5 2022
Oct 4 2022
Sep 30 2022
Gentle ping :)
Sep 27 2022
- Changed LowerCall to allocate a lazy-save buffer and TPIDR2 block if RequiresLazySave is true but the TPIDR2 object has not yet been set in AArch64FunctionInfo. This is possible where requiresLazySave finds no calls in the function, but the function contains an instruction which will be lowered to a lib call (e.g. a 128 bit floating-point add).
- Renamed requiresLazySave to requiresBufferForLazySave.
- Added a function for allocating the buffer & TPIDR2 object (allocateLazySaveBuffer).
- Added a test case to sme-shared-za-interface.ll for the scenario described above.
Commandeering this patch to try and address review comments while @sdesmalen is away.
Sep 22 2022
I think you have addressed all of the comments that were previously left here, so other than a couple of minor comments from me I think this patch looks good!
Aug 16 2022
Jul 29 2022
Hi @david-arm, this change looks reasonable to me. Can you please wait a day or so before landing, just to make sure the other reviewers have a chance to look at it again?
Jul 19 2022
This change looks good to me!
Jul 18 2022
Jul 12 2022
Thank you @david-arm, this LGTM
Jul 5 2022
Jul 4 2022
Jun 24 2022
Jun 20 2022
May 9 2022
Apr 28 2022