[SelectionDAG] Support scalable-vector splats in yet more cases

[frasercrmck]

Summary

This patch extends support for (scalable-vector) splats in the
DAGCombiner via the ISD::matchBinaryPredicate function, which enable a
variety of simple combines of constants.

Users of this function may now have to distinguish between
BUILD_VECTOR and SPLAT_VECTOR vector operands. The way of dealing
with this in-tree follows the approach added for
ISD::matchUnaryPredicate implemented in D94501.

[RKSimon]

The ISD::matchBinaryPredicate mechanical change looks fine - but I've no idea about the change to test_urem_vec ?

[craig.topper]

I think the test_urem_vec looks correct. Whether it is better depends on the cost of a multiply accumulate versus shift and or which is going to be microarchitecture dependent. So I think it is fine.

[frasercrmck]

• update on top of extra urem tests

[frasercrmck]

In D106575#2897784, @craig.topper wrote:

I think the test_urem_vec looks correct. Whether it is better depends on the cost of a multiply accumulate versus shift and or which is going to be microarchitecture dependent. So I think it is fine.

Indeed. I've since added some tests to better show the combine's range. We can see it's a more obvious win on odd divisors. On even divisors it generates a ROTR which we expand into separate shifts.

[craig.topper]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

auto SumOfShifts = [&](ConstantSDNode *LHS, ConstantSDNode *RHS) {
       APInt Sum = c1 + c2;
       unsigned ShiftSum =
           Sum.uge(OpSizeInBits) ? (OpSizeInBits - 1) : Sum.getZExtValue();
       ShiftValues.push_back(DAG.getConstant(ShiftSum, DL, ShiftSVT));
       return true;
     };
     if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), SumOfShifts)) {
       SDValue ShiftValue;
-      if (VT.isVector())
+      if (N1.getOpcode() == ISD::BUILD_VECTOR)
         ShiftValue = DAG.getBuildVector(ShiftVT, DL, ShiftValues);
-      else
+      else if (N1.getOpcode() == ISD::SPLAT_VECTOR) {
+        assert(ShiftValues.size() == 1 &&
+               "Expected matchBinaryPredicate to return one element for "
+               "SPLAT_VECTORs");
+        ShiftValue = DAG.getSplatVector(ShiftVT, DL, ShiftValues[0]);
+      } else
         ShiftValue = ShiftValues[0];
       return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue);
     }
   }
 
   // fold (sra (shl X, m), (sub result_size, n))
   // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
   // result_size - n != m.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (!AllowTypeMismatch && LHS.getValueType() != RHS.getValueType())
     return false;
 
   // TODO: Add support for scalar UNDEF cases?
   if (auto *LHSCst = dyn_cast<ConstantSDNode>(LHS))
     if (auto *RHSCst = dyn_cast<ConstantSDNode>(RHS))
       return Match(LHSCst, RHSCst);
 
   // TODO: Add support for vector UNDEF cases?
-  if (ISD::BUILD_VECTOR != LHS.getOpcode() ||
-      ISD::BUILD_VECTOR != RHS.getOpcode())
+  if (LHS.getOpcode() != RHS.getOpcode() ||
+      (LHS.getOpcode() != ISD::BUILD_VECTOR &&
+       LHS.getOpcode() != ISD::SPLAT_VECTOR))
     return false;
 
   EVT SVT = LHS.getValueType().getScalarType();
   for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
     SDValue LHSOp = LHS.getOperand(i);
     SDValue RHSOp = RHS.getOperand(i);
     bool LHSUndef = AllowUndefs && LHSOp.isUndef();
     bool RHSUndef = AllowUndefs && RHSOp.isUndef();

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (AllLanesAreTautological)
     return SDValue();
 
   // If this is a urem by a powers-of-two, avoid the fold since it can be
   // best implemented as a bit test.
   if (AllDivisorsArePowerOfTwo)
     return SDValue();
 
   SDValue PVal, KVal, QVal;
-  if (VT.isVector()) {
+  if (D.getOpcode() == ISD::BUILD_VECTOR) {
     if (HadTautologicalLanes) {
       // Try to turn PAmts into a splat, since we don't care about the values
       // that are currently '0'. If we can't, just keep '0'`s.
       turnVectorIntoSplatVector(PAmts, isNullConstant);
       // Try to turn KAmts into a splat, since we don't care about the values
       // that are currently '-1'. If we can't, change them to '0'`s.
       turnVectorIntoSplatVector(KAmts, isAllOnesConstant,
                                 DAG.getConstant(0, DL, ShSVT));
     }
 
     PVal = DAG.getBuildVector(VT, DL, PAmts);
     KVal = DAG.getBuildVector(ShVT, DL, KAmts);
     QVal = DAG.getBuildVector(VT, DL, QAmts);
+  } else if (D.getOpcode() == ISD::SPLAT_VECTOR) {
+    assert(PAmts.size() == 1 && KAmts.size() == 1 && QAmts.size() == 1 &&
+           "Expected matchBinaryPredicate to return one element for "
+           "SPLAT_VECTORs");
+    PVal = DAG.getSplatVector(VT, DL, PAmts[0]);
+    KVal = DAG.getSplatVector(ShVT, DL, KAmts[0]);
+    QVal = DAG.getSplatVector(VT, DL, QAmts[0]);
   } else {
     PVal = PAmts[0];
     KVal = KAmts[0];
     QVal = QAmts[0];
   }
 
   if (!ComparingWithAllZeros && !AllComparisonsWithNonZerosAreTautological) {
     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT))

llvm/test/CodeGen/RISCV/rvv/combine-splats.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s
 
 ; fold (and (or x, C), D) -> D if (C & D) == D
 
 define <vscale x 4 x i32> @and_or_nxv4i32(<vscale x 4 x i32> %A) {
 ; CHECK-LABEL: and_or_nxv4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    addi a0, zero, 255
-; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; CHECK-NEXT:    vor.vx v26, v8, a0
-; CHECK-NEXT:    vand.vi v8, v26, 8
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmv.v.i v8, 8
 ; CHECK-NEXT:    ret
   %ins1 = insertelement <vscale x 4 x i32> poison, i32 255, i32 0
   %splat1 = shufflevector <vscale x 4 x i32> %ins1, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %ins2 = insertelement <vscale x 4 x i32> poison, i32 8, i32 0
   %splat2 = shufflevector <vscale x 4 x i32> %ins2, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
   %v1 = or <vscale x 4 x i32> %A, %splat1
   %v2 = and <vscale x 4 x i32> %v1, %splat2
   ret <vscale x 4 x i32> %v2
 }
 
 ; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) iff (c1 & c2) != 0
 
 define <vscale x 2 x i64> @or_and_nxv2i64(<vscale x 2 x i64> %a0) {
 ; CHECK-LABEL: or_and_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT:    vand.vi v26, v8, 7
-; CHECK-NEXT:    vor.vi v8, v26, 3
+; CHECK-NEXT:    vor.vi v26, v8, 3
+; CHECK-NEXT:    vand.vi v8, v26, 7
 ; CHECK-NEXT:    ret
   %ins1 = insertelement <vscale x 2 x i64> poison, i64 7, i32 0
   %splat1 = shufflevector <vscale x 2 x i64> %ins1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
   %ins2 = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %ins2, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
   %v1 = and <vscale x 2 x i64> %a0, %splat1
   %v2 = or <vscale x 2 x i64> %v1, %splat2
   ret <vscale x 2 x i64> %v2
 }
 
 ; If all masked bits are going to be set, that's a constant fold.
 
 define <vscale x 2 x i64> @or_and_nxv2i64_fold(<vscale x 2 x i64> %a0) {
 ; CHECK-LABEL: or_and_nxv2i64_fold:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT:    vand.vi v26, v8, 1
-; CHECK-NEXT:    vor.vi v8, v26, 3
+; CHECK-NEXT:    vmv.v.i v8, 3
 ; CHECK-NEXT:    ret
   %ins1 = insertelement <vscale x 2 x i64> poison, i64 1, i32 0
   %splat1 = shufflevector <vscale x 2 x i64> %ins1, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
   %ins2 = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
   %splat2 = shufflevector <vscale x 2 x i64> %ins2, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
   %v1 = and <vscale x 2 x i64> %a0, %splat1
   %v2 = or <vscale x 2 x i64> %v1, %splat2
   ret <vscale x 2 x i64> %v2

 }
 
 ; fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
 
 define <vscale x 2 x i32> @combine_vec_ashr_ashr(<vscale x 2 x i32> %x) {
 ; CHECK-LABEL: combine_vec_ashr_ashr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vsra.vi v25, v8, 2
-; CHECK-NEXT:    vsra.vi v8, v25, 4
+; CHECK-NEXT:    vsra.vi v8, v8, 6
 ; CHECK-NEXT:    ret
   %ins1 = insertelement <vscale x 2 x i32> poison, i32 2, i32 0
   %splat1 = shufflevector <vscale x 2 x i32> %ins1, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %ins2 = insertelement <vscale x 2 x i32> poison, i32 4, i32 0
   %splat2 = shufflevector <vscale x 2 x i32> %ins2, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
   %v1 = ashr <vscale x 2 x i32> %x, %splat1
   %v2 = ashr <vscale x 2 x i32> %v1, %splat2
   ret <vscale x 2 x i32> %v2
 }
 
 ; fold (srl (srl x, c1), c2) -> (srl x, (add c1, c2))
 
 define <vscale x 8 x i16> @combine_vec_lshr_lshr(<vscale x 8 x i16> %x) {
 ; CHECK-LABEL: combine_vec_lshr_lshr:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
-; CHECK-NEXT:    vsrl.vi v26, v8, 4
-; CHECK-NEXT:    vsrl.vi v8, v26, 4
+; CHECK-NEXT:    vsrl.vi v8, v8, 8
 ; CHECK-NEXT:    ret
   %ins1 = insertelement <vscale x 8 x i16> poison, i16 2, i32 0
   %splat1 = shufflevector <vscale x 8 x i16> %ins1, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %ins2 = insertelement <vscale x 8 x i16> poison, i16 4, i32 0
   %splat2 = shufflevector <vscale x 8 x i16> %ins2, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %v1 = lshr <vscale x 8 x i16> %x, %splat2
   %v2 = lshr <vscale x 8 x i16> %v1, %splat2
   ret <vscale x 8 x i16> %v2
 }

llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v < %s | FileCheck %s --check-prefix=RV64
 
 define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq0(<vscale x 1 x i16> %x) nounwind {
 ; RV32-LABEL: test_urem_vec_even_divisor_eq0:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a0, 1048571
 ; RV32-NEXT:    addi a0, a0, -1365
 ; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v25, v8, a0
-; RV32-NEXT:    vsrl.vi v25, v25, 2
-; RV32-NEXT:    addi a0, zero, 6
-; RV32-NEXT:    vnmsub.vx v25, a0, v8
-; RV32-NEXT:    vmv.v.i v26, 0
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    vmerge.vim v8, v26, -1, v0
+; RV32-NEXT:    vmul.vx v25, v8, a0
+; RV32-NEXT:    vsll.vi v26, v25, 15
+; RV32-NEXT:    vsrl.vi v25, v25, 1
+; RV32-NEXT:    vor.vv v25, v25, v26
+; RV32-NEXT:    lui a0, 3
+; RV32-NEXT:    addi a0, a0, -1366
+; RV32-NEXT:    vmsgtu.vx v0, v25, a0
+; RV32-NEXT:    vmv.v.i v25, 0
+; RV32-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_vec_even_divisor_eq0:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a0, 1048571
 ; RV64-NEXT:    addiw a0, a0, -1365
 ; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v25, v8, a0
-; RV64-NEXT:    vsrl.vi v25, v25, 2
-; RV64-NEXT:    addi a0, zero, 6
-; RV64-NEXT:    vnmsub.vx v25, a0, v8
-; RV64-NEXT:    vmv.v.i v26, 0
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    vmerge.vim v8, v26, -1, v0
+; RV64-NEXT:    vmul.vx v25, v8, a0
+; RV64-NEXT:    vsll.vi v26, v25, 15
+; RV64-NEXT:    vsrl.vi v25, v25, 1
+; RV64-NEXT:    vor.vv v25, v25, v26
+; RV64-NEXT:    lui a0, 3
+; RV64-NEXT:    addiw a0, a0, -1366
+; RV64-NEXT:    vmsgtu.vx v0, v25, a0
+; RV64-NEXT:    vmv.v.i v25, 0
+; RV64-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV64-NEXT:    ret
   %ins1 = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
   %splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %urem = urem <vscale x 1 x i16> %x, %splat1
   %ins2 = insertelement <vscale x 1 x i16> poison, i16 0, i32 0
   %splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
   %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %ext
 }
 
 define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq0(<vscale x 1 x i16> %x) nounwind {
 ; RV32-LABEL: test_urem_vec_odd_divisor_eq0:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a0, 1048573
 ; RV32-NEXT:    addi a0, a0, -819
 ; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v25, v8, a0
-; RV32-NEXT:    vsrl.vi v25, v25, 2
-; RV32-NEXT:    addi a0, zero, 5
-; RV32-NEXT:    vnmsub.vx v25, a0, v8
-; RV32-NEXT:    vmv.v.i v26, 0
-; RV32-NEXT:    vmsne.vi v0, v25, 0
-; RV32-NEXT:    vmerge.vim v8, v26, -1, v0
+; RV32-NEXT:    vmul.vx v25, v8, a0
+; RV32-NEXT:    lui a0, 3
+; RV32-NEXT:    addi a0, a0, 819
+; RV32-NEXT:    vmsgtu.vx v0, v25, a0
+; RV32-NEXT:    vmv.v.i v25, 0
+; RV32-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_vec_odd_divisor_eq0:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a0, 1048573
 ; RV64-NEXT:    addiw a0, a0, -819
 ; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v25, v8, a0
-; RV64-NEXT:    vsrl.vi v25, v25, 2
-; RV64-NEXT:    addi a0, zero, 5
-; RV64-NEXT:    vnmsub.vx v25, a0, v8
-; RV64-NEXT:    vmv.v.i v26, 0
-; RV64-NEXT:    vmsne.vi v0, v25, 0
-; RV64-NEXT:    vmerge.vim v8, v26, -1, v0
+; RV64-NEXT:    vmul.vx v25, v8, a0
+; RV64-NEXT:    lui a0, 3
+; RV64-NEXT:    addiw a0, a0, 819
+; RV64-NEXT:    vmsgtu.vx v0, v25, a0
+; RV64-NEXT:    vmv.v.i v25, 0
+; RV64-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV64-NEXT:    ret
   %ins1 = insertelement <vscale x 1 x i16> poison, i16 5, i32 0
   %splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %urem = urem <vscale x 1 x i16> %x, %splat1
   %ins2 = insertelement <vscale x 1 x i16> poison, i16 0, i32 0
   %splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
   %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %ext
 }
 
 define <vscale x 1 x i16> @test_urem_vec_even_divisor_eq1(<vscale x 1 x i16> %x) nounwind {
 ; RV32-LABEL: test_urem_vec_even_divisor_eq1:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, 1
+; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; RV32-NEXT:    vsub.vx v25, v8, a0
 ; RV32-NEXT:    lui a0, 1048571
 ; RV32-NEXT:    addi a0, a0, -1365
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v25, v8, a0
-; RV32-NEXT:    vsrl.vi v25, v25, 2
-; RV32-NEXT:    addi a0, zero, 6
-; RV32-NEXT:    vnmsub.vx v25, a0, v8
-; RV32-NEXT:    vmsne.vi v0, v25, 1
+; RV32-NEXT:    vmul.vx v25, v25, a0
+; RV32-NEXT:    vsll.vi v26, v25, 15
+; RV32-NEXT:    vsrl.vi v25, v25, 1
+; RV32-NEXT:    vor.vv v25, v25, v26
+; RV32-NEXT:    lui a0, 3
+; RV32-NEXT:    addi a0, a0, -1366
+; RV32-NEXT:    vmsgtu.vx v0, v25, a0
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_vec_even_divisor_eq1:
 ; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 1
+; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; RV64-NEXT:    vsub.vx v25, v8, a0
 ; RV64-NEXT:    lui a0, 1048571
 ; RV64-NEXT:    addiw a0, a0, -1365
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v25, v8, a0
-; RV64-NEXT:    vsrl.vi v25, v25, 2
-; RV64-NEXT:    addi a0, zero, 6
-; RV64-NEXT:    vnmsub.vx v25, a0, v8
-; RV64-NEXT:    vmsne.vi v0, v25, 1
+; RV64-NEXT:    vmul.vx v25, v25, a0
+; RV64-NEXT:    vsll.vi v26, v25, 15
+; RV64-NEXT:    vsrl.vi v25, v25, 1
+; RV64-NEXT:    vor.vv v25, v25, v26
+; RV64-NEXT:    lui a0, 3
+; RV64-NEXT:    addiw a0, a0, -1366
+; RV64-NEXT:    vmsgtu.vx v0, v25, a0
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV64-NEXT:    ret
   %ins1 = insertelement <vscale x 1 x i16> poison, i16 6, i32 0
   %splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %urem = urem <vscale x 1 x i16> %x, %splat1
   %ins2 = insertelement <vscale x 1 x i16> poison, i16 1, i32 0
   %splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
   %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %ext
 }
 
 define <vscale x 1 x i16> @test_urem_vec_odd_divisor_eq1(<vscale x 1 x i16> %x) nounwind {
 ; RV32-LABEL: test_urem_vec_odd_divisor_eq1:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    addi a0, zero, 1
+; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; RV32-NEXT:    vsub.vx v25, v8, a0
 ; RV32-NEXT:    lui a0, 1048573
 ; RV32-NEXT:    addi a0, a0, -819
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v25, v8, a0
-; RV32-NEXT:    vsrl.vi v25, v25, 2
-; RV32-NEXT:    addi a0, zero, 5
-; RV32-NEXT:    vnmsub.vx v25, a0, v8
-; RV32-NEXT:    vmsne.vi v0, v25, 1
+; RV32-NEXT:    vmul.vx v25, v25, a0
+; RV32-NEXT:    lui a0, 3
+; RV32-NEXT:    addi a0, a0, 818
+; RV32-NEXT:    vmsgtu.vx v0, v25, a0
 ; RV32-NEXT:    vmv.v.i v25, 0
 ; RV32-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: test_urem_vec_odd_divisor_eq1:
 ; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, zero, 1
+; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; RV64-NEXT:    vsub.vx v25, v8, a0
 ; RV64-NEXT:    lui a0, 1048573
 ; RV64-NEXT:    addiw a0, a0, -819
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v25, v8, a0
-; RV64-NEXT:    vsrl.vi v25, v25, 2
-; RV64-NEXT:    addi a0, zero, 5
-; RV64-NEXT:    vnmsub.vx v25, a0, v8
-; RV64-NEXT:    vmsne.vi v0, v25, 1
+; RV64-NEXT:    vmul.vx v25, v25, a0
+; RV64-NEXT:    lui a0, 3
+; RV64-NEXT:    addiw a0, a0, 818
+; RV64-NEXT:    vmsgtu.vx v0, v25, a0
 ; RV64-NEXT:    vmv.v.i v25, 0
 ; RV64-NEXT:    vmerge.vim v8, v25, -1, v0
 ; RV64-NEXT:    ret
   %ins1 = insertelement <vscale x 1 x i16> poison, i16 5, i32 0
   %splat1 = shufflevector <vscale x 1 x i16> %ins1, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %urem = urem <vscale x 1 x i16> %x, %splat1
   %ins2 = insertelement <vscale x 1 x i16> poison, i16 1, i32 0
   %splat2 = shufflevector <vscale x 1 x i16> %ins2, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %cmp = icmp ne <vscale x 1 x i16> %urem, %splat2
   %ext = sext <vscale x 1 x i1> %cmp to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %ext
 }