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david-arm (David Sherwood)
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Nov 20 2019, 6:41 AM (131 w, 2 d)

Recent Activity

Wed, May 25

david-arm added a comment to D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.

Hi @dmgreen, thanks for the explanation! The reason for doing this in LoopVectorize.cpp is because it feels much more natural to express it this way than writing a complicated pass just before lowering to transform it afterwards. There is no guarantee that such a transform would even succeed if subsequent passes change aspects of the loop. I believe this is actually the way it's done in GCC as well. From a performance perspective I've not observed any degradations in code quality or performance so far with this approach.

Wed, May 25, 8:22 AM · Restricted Project, Restricted Project
david-arm updated the diff for D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.
  • Changed TTI interface emitGetActiveLaneMask to return a new ActiveLaneMask enum class.
  • Added/moved comments in a few places.
  • Tidied up the ::execute function.
Wed, May 25, 8:20 AM · Restricted Project, Restricted Project
david-arm committed rG87936c7b131e: [LoopVectorize] Fix assertion failure in fixReduction when tail-folding (authored by david-arm).
[LoopVectorize] Fix assertion failure in fixReduction when tail-folding
Wed, May 25, 3:47 AM · Restricted Project, Restricted Project
david-arm closed D126295: [LoopVectorize] Fix assertion failure in fixReduction when tail-folding.
Wed, May 25, 3:47 AM · Restricted Project, Restricted Project
david-arm added a comment to D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.

Would it be better for this be done later, by the backend? I worry that the BETC would not be calculable any more for the loop, and the new structure would be more difficult to analyze in general. Handling it separately from the vectorizer would also allow other loops to be transformed. What happens at the moment for loops with ACLE intrinsics, for example?

Wed, May 25, 3:10 AM · Restricted Project, Restricted Project

Tue, May 24

david-arm added inline comments to D126295: [LoopVectorize] Fix assertion failure in fixReduction when tail-folding.
Tue, May 24, 8:53 AM · Restricted Project, Restricted Project
david-arm updated the diff for D126295: [LoopVectorize] Fix assertion failure in fixReduction when tail-folding.
  • Address review comments on test.
Tue, May 24, 8:52 AM · Restricted Project, Restricted Project
david-arm requested review of D126295: [LoopVectorize] Fix assertion failure in fixReduction when tail-folding.
Tue, May 24, 6:17 AM · Restricted Project, Restricted Project

Mon, May 23

david-arm added inline comments to D126201: [WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors..
Mon, May 23, 7:28 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121899: [LoopVectorize] Optimise away the icmp when tail-folding for some low trip counts.
  • I've removed the need for a separate TripCount VPValue in the VPlan class because we're always going to need the original scalar trip count, and the value is the same for each Part anyway. Now we just store a copy in the VPTransformState so that the execute() functions can access it.
Mon, May 23, 1:35 AM · Restricted Project, Restricted Project
david-arm accepted D126168: [SelectionDAG] Add support to widen ISD::STEP_VECTOR operations..

LGTM!

Mon, May 23, 12:42 AM · Restricted Project, Restricted Project

Fri, May 20

david-arm added inline comments to D121899: [LoopVectorize] Optimise away the icmp when tail-folding for some low trip counts.
Fri, May 20, 7:10 AM · Restricted Project, Restricted Project
david-arm accepted D125977: [AArch64] Remove references to Streaming SVE from target features..

LGTM!

Fri, May 20, 6:52 AM · Restricted Project, Restricted Project

Mon, May 16

david-arm resigned from D107541: [AArch64] Cost-model vector concatenation.

Nothing has happened with this patch since last August, so I'm resigning as a reviewer for now!

Mon, May 16, 6:22 AM · Restricted Project, Restricted Project
david-arm resigned from D104521: [InstrRef][AArch64][2/4] Recognise post-fe spills and restores.
Mon, May 16, 6:21 AM · Restricted Project, Restricted Project
david-arm accepted D123381: [SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes..

LGTM!

Mon, May 16, 6:20 AM · Restricted Project, Restricted Project
david-arm added inline comments to D125601: [DAGCombiner][AArch64] Reorder the bitcast of scalable vector.
Mon, May 16, 6:01 AM · Restricted Project, Restricted Project
david-arm accepted D125640: [AArch64][ARM][RISCV][X86] Add test cases for PR55484. NFC.

LGTM!

Mon, May 16, 5:07 AM · Restricted Project, Restricted Project
david-arm accepted D125537: [AArch64][SME]Tied up ZA operand for accumulate instructions.

LGTM!

Mon, May 16, 5:06 AM · Restricted Project, Restricted Project
david-arm added a comment to D125533: Revert "[LoopVectorize] Simplify scalar cost calculation in getInstructionCost.".

Hi @fhahn, I think I remember when doing this patch these asserts were put in to deal with reviewer requests, but in my original patch I didn't have any asserts at all. I worry that reverting the patch doesn't solve the underlying problem, which is that the cost calculations are sometimes incorrect and difficult to follow. As a compromise could we just remove the assert, but keep the simpler (and easier to understand) logic? This patch has been in the codebase for over a year now without problems - personally it feels more appropriate to fix the assert rather than revert. What do you think?

Mon, May 16, 4:59 AM · Restricted Project, Restricted Project
david-arm committed rGbefc95204506: [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors (authored by david-arm).
[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors
Mon, May 16, 1:14 AM · Restricted Project, Restricted Project
david-arm closed D121595: [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors.
Mon, May 16, 1:14 AM · Restricted Project, Restricted Project

Fri, May 13

david-arm committed rG92c645b5c196: [LoopVectorize] Add overflow checks when tail-folding with scalable vectors (authored by david-arm).
[LoopVectorize] Add overflow checks when tail-folding with scalable vectors
Fri, May 13, 6:10 AM · Restricted Project, Restricted Project
david-arm closed D125235: [LoopVectorize] Add overflow checks when tail-folding with scalable vectors.
Fri, May 13, 6:10 AM · Restricted Project, Restricted Project
david-arm added inline comments to D125235: [LoopVectorize] Add overflow checks when tail-folding with scalable vectors.
Fri, May 13, 1:36 AM · Restricted Project, Restricted Project
david-arm updated the diff for D125235: [LoopVectorize] Add overflow checks when tail-folding with scalable vectors.
  • Addressed review comments!
Fri, May 13, 1:35 AM · Restricted Project, Restricted Project

Wed, May 11

david-arm added a reviewer for D119442: [NFC][SVE] Add more tests to CodeGen/AArch64/sve-fixed-length-reshuffle.ll: kmclaughlin.
Wed, May 11, 2:32 AM · Restricted Project, Restricted Project

Tue, May 10

david-arm added a comment to D125233: [AArch64][SVE] Convert SRSHL to LSL when the fed from an ABS intrinsic.

Hi @bsmith, this looks like a sensible optimisation! I suppose we can also do something similar when the input is an and too? i.e.

Tue, May 10, 8:37 AM · Restricted Project, Restricted Project
david-arm added a comment to D121595: [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors.

Gentle ping.

Tue, May 10, 5:32 AM · Restricted Project, Restricted Project
david-arm added inline comments to D121899: [LoopVectorize] Optimise away the icmp when tail-folding for some low trip counts.
Tue, May 10, 5:30 AM · Restricted Project, Restricted Project
david-arm accepted D125193: [SVE] Enable use of 32bit gather/scatter indices for fixed length vectors.

LGTM! Some nice codegen improvements. :)

Tue, May 10, 3:50 AM · Restricted Project, Restricted Project
david-arm edited reviewers for D125301: [LoopVectorize] Add option to use active lane mask for loop control flow, added: dmgreen; removed: greened.
Tue, May 10, 3:41 AM · Restricted Project, Restricted Project
david-arm requested review of D125301: [LoopVectorize] Add option to use active lane mask for loop control flow.
Tue, May 10, 3:40 AM · Restricted Project, Restricted Project

Mon, May 9

david-arm added inline comments to D125193: [SVE] Enable use of 32bit gather/scatter indices for fixed length vectors.
Mon, May 9, 8:41 AM · Restricted Project, Restricted Project
david-arm requested review of D125235: [LoopVectorize] Add overflow checks when tail-folding with scalable vectors.
Mon, May 9, 8:04 AM · Restricted Project, Restricted Project
david-arm added a comment to D125016: [LV] Widen freeze instead of scalarizing it.

Hi @lizhijin, thanks a lot for the fix. This looks a lot better than the previous one! I just had a few minor comments ...

Mon, May 9, 5:43 AM · Restricted Project, Restricted Project
david-arm committed rG45f2e92d971b: [NFC][LoopVectorize] Add SVE test for tail-folding combined with interleaving (authored by david-arm).
[NFC][LoopVectorize] Add SVE test for tail-folding combined with interleaving
Mon, May 9, 5:08 AM · Restricted Project, Restricted Project
david-arm closed D125001: [NFC][LoopVectorize] Add SVE test for tail-folding combined with interleaving.
Mon, May 9, 5:08 AM · Restricted Project, Restricted Project
david-arm added inline comments to D123381: [SelectionDAG] Remove duplicate "is scaled" information from gather/scatter SDNodes..
Mon, May 9, 4:06 AM · Restricted Project, Restricted Project
david-arm accepted D125215: [AArch64][SVE] Improve codegen when extracting first lane of active lane mask.

LGTM! Thanks for the codegen improvement @RosieSumpter. :)

Mon, May 9, 3:56 AM · Restricted Project, Restricted Project

Thu, May 5

david-arm requested review of D125001: [NFC][LoopVectorize] Add SVE test for tail-folding combined with interleaving.
Thu, May 5, 3:57 AM · Restricted Project, Restricted Project

Tue, May 3

david-arm accepted D123347: [ISD::IndexType] Helper functions for common queries..

LGTM!

Tue, May 3, 3:47 AM · Restricted Project, Restricted Project
david-arm added inline comments to D123347: [ISD::IndexType] Helper functions for common queries..
Tue, May 3, 1:33 AM · Restricted Project, Restricted Project

Thu, Apr 28

david-arm added inline comments to D124506: [NFC][AArch64][CodeGen] Use ArrayRef in TargetLowering functions.
Thu, Apr 28, 5:36 AM · Restricted Project, Restricted Project

Apr 27 2022

david-arm added inline comments to D121899: [LoopVectorize] Optimise away the icmp when tail-folding for some low trip counts.
Apr 27 2022, 8:49 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121595: [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors.
  • Completely removed all restrictions on using tail-folding for scalable vectors.
  • Added test to show we apply tail-folding when compiling with -Os
Apr 27 2022, 8:20 AM · Restricted Project, Restricted Project

Apr 25 2022

david-arm added a comment to D124269: [CostModel] Add basic fptoi_sat costs.

Hi @dmgreen, just out of curiosity why do we only care about NaNs for the signed case? Looking at the documentation for llvm.fptosi.sat and llvm.fptoui.sat they both state that "if any argument is NaN, zero is returned". So don't you have to do a fcmp+select in both cases?

Apr 25 2022, 7:20 AM · Restricted Project, Restricted Project
david-arm accepted D110235: [LoopVectorize] Support reductions that store intermediary result.

LGTM! Thanks for addressing all the comments and fixing bugs, adding new tests, etc. I have a couple of nits you can address before merging. I think given that you've run the LLVM test suite without seeing failures and we know more loops are vectorising then that gives us a good level of confidence. :)

Apr 25 2022, 7:01 AM · Restricted Project, Restricted Project
david-arm added a reviewer for D124326: [AArch64][SVE] Fix assertions when vectorizing Freeze Instructions: fhahn.

Hi @lizhijin, I'm not sure if this is really the right strategy here. From what I can tell the freeze instruction can be widened normally, so it feels wrong to have a special case for it in the VPReplicateRecipe. Can we not just ensure we choose the right vplan in the first place, i.e. VPWidenRecipe?

Apr 25 2022, 3:37 AM · Restricted Project, Restricted Project

Apr 22 2022

david-arm added inline comments to D124224: [AArch64][SVE] Add some logical operation DestructiveBinaryComm patterns.
Apr 22 2022, 1:18 AM · Restricted Project, Restricted Project
david-arm added a comment to D124224: [AArch64][SVE] Add some logical operation DestructiveBinaryComm patterns.

This patch seems sensible to me! I just had a couple of minor comments.

Apr 22 2022, 12:43 AM · Restricted Project, Restricted Project

Apr 14 2022

david-arm accepted D123670: [SVE] Add support for non-element-type sized scaling when lowering MGATHER/MSCATTER..

LGTM! Thanks for the changes Paul. :)

Apr 14 2022, 2:51 AM · Restricted Project, Restricted Project
david-arm accepted D123683: [SVE] Refactor MGATHER lowering for unsupported passthru values..

LGTM!

Apr 14 2022, 1:49 AM · Restricted Project, Restricted Project
david-arm added a comment to D123670: [SVE] Add support for non-element-type sized scaling when lowering MGATHER/MSCATTER..

This looks like a nice couple of fixes @paulwalker-arm, thanks! I had a couple of minor comments ...

Apr 14 2022, 1:18 AM · Restricted Project, Restricted Project

Apr 13 2022

david-arm committed rG44271e7c5582: [AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE (authored by david-arm).
[AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE
Apr 13 2022, 2:24 AM · Restricted Project, Restricted Project
david-arm closed D121905: [AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE.
Apr 13 2022, 2:24 AM · Restricted Project, Restricted Project

Apr 12 2022

david-arm updated the diff for D121905: [AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE.
  • Removed expansion of SETUNE and fixed up the fcmne patterns to use SETUNE instead of SETONE as they were incorrect before.
Apr 12 2022, 6:03 AM · Restricted Project, Restricted Project

Apr 1 2022

david-arm added a comment to D122829: [AArch64] Optimize SDIV with pow2 constant divisor.

Is it also possible that in some contexts we may want to avoid setting flags where possible? i.e. for loops with control flow? The architecture only has one flags register, but has many GPRs.

Apr 1 2022, 1:08 AM · Restricted Project, Restricted Project

Mar 31 2022

david-arm added inline comments to D122796: [SVE][AArch64] Enable first active true vector combine for INTRINSIC_WO_CHAIN.
Mar 31 2022, 9:11 AM · Restricted Project, Restricted Project
david-arm added inline comments to D122796: [SVE][AArch64] Enable first active true vector combine for INTRINSIC_WO_CHAIN.
Mar 31 2022, 5:43 AM · Restricted Project, Restricted Project

Mar 18 2022

david-arm accepted D121968: [AArch64] Fix incorrect getSetCCInverse usage within trySwapVSelectOperands..

LGTM! Thanks for making the changes @paulwalker-arm. :)

Mar 18 2022, 3:42 AM · Restricted Project, Restricted Project
david-arm added inline comments to D121968: [AArch64] Fix incorrect getSetCCInverse usage within trySwapVSelectOperands..
Mar 18 2022, 1:45 AM · Restricted Project, Restricted Project

Mar 17 2022

david-arm requested review of D121905: [AArch64][SVE] Fix lowering of "fcmp ueq/one" when using SVE.
Mar 17 2022, 5:00 AM · Restricted Project, Restricted Project
david-arm added a reviewer for D121899: [LoopVectorize] Optimise away the icmp when tail-folding for some low trip counts: fhahn.
Mar 17 2022, 3:38 AM · Restricted Project, Restricted Project
david-arm requested review of D121899: [LoopVectorize] Optimise away the icmp when tail-folding for some low trip counts.
Mar 17 2022, 3:38 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121595: [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors.
  • Added more CHECK lines to the new tests because they will be useful for a future patch.
Mar 17 2022, 3:36 AM · Restricted Project, Restricted Project

Mar 14 2022

david-arm requested review of D121595: [LoopVectorize] Permit tail-folding for low trip counts using scalable vectors.
Mar 14 2022, 4:44 AM · Restricted Project, Restricted Project
david-arm committed rGe7b89c2fc359: Add BasicTTIImpl cost model for llvm.get.active.lane.mask intrinsic (authored by david-arm).
Add BasicTTIImpl cost model for llvm.get.active.lane.mask intrinsic
Mar 14 2022, 2:35 AM · Restricted Project
david-arm closed D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic.
Mar 14 2022, 2:35 AM · Restricted Project, Restricted Project
david-arm accepted D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.
Mar 14 2022, 2:20 AM · Restricted Project, Restricted Project

Mar 11 2022

david-arm added a comment to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.

LGTM (with formatting issues fixed)! This looks great now thanks @kmclaughlin. :)

Mar 11 2022, 6:04 AM · Restricted Project, Restricted Project
david-arm committed rGaeeb1199b4b4: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal… (authored by david-arm).
[AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal…
Mar 11 2022, 1:58 AM · Restricted Project
david-arm closed D121297: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types.
Mar 11 2022, 1:58 AM · Restricted Project, Restricted Project

Mar 10 2022

david-arm added a comment to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.

Thanks for making all the changes @kmclaughlin! I think it looks pretty good now. I just had a few more minor comments ...

Mar 10 2022, 7:17 AM · Restricted Project, Restricted Project
david-arm added a reviewer for D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic: frasercrmck.
Mar 10 2022, 2:53 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic.
  • Added cost model tests for ARM and RISCV too. Some of the costs for RISCV with scalable vector types are showing as Invalid, but I think this is probably due to something attempting to scalarise the saturating add, etc.
Mar 10 2022, 2:53 AM · Restricted Project, Restricted Project
david-arm accepted D118584: [AArch64] Combine ISD::AND into AArch64ISD::ANDS.

LGTM as well! Sorry I'd forgotten about this and should have responded much earlier!

Mar 10 2022, 2:44 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121297: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types.
  • I have tried an alternative approach with this latest patch. Instead of changing the default min SVE vector bits to 128, I have amended the asserts in LowerToPredicatedOp to check that the fixed-width type is legal.
Mar 10 2022, 1:26 AM · Restricted Project, Restricted Project

Mar 9 2022

david-arm requested review of D121297: [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types.
Mar 9 2022, 8:04 AM · Restricted Project, Restricted Project
david-arm added inline comments to D119238: [InstCombine] Support load-store forwarding with scalable vector types.
Mar 9 2022, 3:08 AM · Restricted Project, Restricted Project
david-arm added a comment to D120953: [AArch64][SelectionDAG] Supports unpklo/hi instructions to reduce the number of loads.

Hi @Allen, the codegen for the tests looks good to me and the optimisation seems sensible. However, I think perhaps what @paulwalker-arm meant was that we should set all expand types for all integer combinations to be Expand, then selectively mark some as Legal. Can you confirm this is what you meant @paulwalker-arm?

Mar 9 2022, 1:55 AM · Restricted Project, Restricted Project

Mar 8 2022

david-arm added a comment to D120894: [AArch64][SVE]Make better use of gather/scatter when inside a loop body.

Hi @CarolineConcatto, I just have a few more minor comments!

Mar 8 2022, 6:18 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic.
  • Moved all of the cost calculation into BasicTTIImpl.h and tried to estimate the cost more formally for the case where we expand the intrinsic. The expansion costs look way over the top to be honest, but I guess we can refine those later if necessary.
Mar 8 2022, 6:09 AM · Restricted Project, Restricted Project
david-arm added inline comments to D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic.
Mar 8 2022, 1:09 AM · Restricted Project, Restricted Project

Mar 7 2022

david-arm added a comment to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.

Hi @kmclaughlin, this patch looks a lot better now thanks! Most of my remaining comments are minor, but I do think we should add some explicit checks for truncating scatters and extending gathers.

Mar 7 2022, 8:34 AM · Restricted Project, Restricted Project
david-arm added inline comments to D120894: [AArch64][SVE]Make better use of gather/scatter when inside a loop body.
Mar 7 2022, 6:48 AM · Restricted Project, Restricted Project
david-arm updated the diff for D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic.
  • Moved the cost for the intrinsic expansion case into BasicTTIImpl.h
Mar 7 2022, 6:21 AM · Restricted Project, Restricted Project
Herald added a project to D119238: [InstCombine] Support load-store forwarding with scalable vector types: Restricted Project.
Mar 7 2022, 5:42 AM · Restricted Project, Restricted Project
david-arm requested review of D121109: [AArch64] Add cost model for llvm.get.active.lane.mask intrinsic.
Mar 7 2022, 5:06 AM · Restricted Project, Restricted Project
david-arm accepted D120891: [AArch64] Perform first active true vector combine.

LGTM! Thanks for making the changes @Allen.

Mar 7 2022, 1:09 AM · Restricted Project, Restricted Project

Mar 4 2022

david-arm added inline comments to D120891: [AArch64] Perform first active true vector combine.
Mar 4 2022, 3:13 AM · Restricted Project, Restricted Project
david-arm added inline comments to D120953: [AArch64][SelectionDAG] Supports unpklo/hi instructions to reduce the number of loads.
Mar 4 2022, 3:04 AM · Restricted Project, Restricted Project
david-arm accepted D119469: [AArch64] Turn truncating buildvectors into truncates.

LGTM! Thanks for adding the tests @dmgreen . This patch seems like a nice improvement. :)

Mar 4 2022, 2:51 AM · Restricted Project, Restricted Project
david-arm committed rGf9331c9a2c87: [AArch64] Fix the TuneExynosM4 entry in lib/Target/AArch64/AArch64.td (authored by david-arm).
[AArch64] Fix the TuneExynosM4 entry in lib/Target/AArch64/AArch64.td
Mar 4 2022, 2:27 AM · Restricted Project
david-arm closed D120665: [AArch64] Fix the TuneExynosM4 entry in lib/Target/AArch64/AArch64.td.
Mar 4 2022, 2:27 AM · Restricted Project, Restricted Project

Mar 3 2022

david-arm added a comment to D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores.

Hi @kmclaughlin, this looks like a nice improvement! I've not reviewed all of it so far, but I'll leave a few comments in the bits I have reviewed.

Mar 3 2022, 8:57 AM · Restricted Project, Restricted Project
david-arm updated the diff for D120665: [AArch64] Fix the TuneExynosM4 entry in lib/Target/AArch64/AArch64.td.
Mar 3 2022, 7:40 AM · Restricted Project, Restricted Project
Herald added a project to D119469: [AArch64] Turn truncating buildvectors into truncates: Restricted Project.
Mar 3 2022, 6:38 AM · Restricted Project, Restricted Project
david-arm accepted D120738: [AArch64] Improve access to fixed-width object when stack has SVE..

LGTM! Nice fix thx @sdesmalen. :)

Mar 3 2022, 5:50 AM · Restricted Project, Restricted Project

Feb 28 2022

david-arm requested review of D120665: [AArch64] Fix the TuneExynosM4 entry in lib/Target/AArch64/AArch64.td.
Feb 28 2022, 9:12 AM · Restricted Project, Restricted Project