Delete NaCl support

[MaskRay]

Summary

See https://developer.chrome.com/native-client/migration

[jfb]

I think someone from the current NaCl team should OK this change.

[dschuff]

@jfb thanks for the heads-up.
I replied on the mailing list thread.

[MaskRay]

@dschuff Is NaCL dead in 2022 ? :)

[dschuff]

Sorry, no :)

[MaskRay]

In D78441#4067440, @dschuff wrote:

Sorry, no :)

Is there a timeline for the removal?

[MaskRay]

In D78441#4074689, @MaskRay wrote:

In D78441#4067440, @dschuff wrote:

Sorry, no :)

Is there a timeline for the removal?

@dschuff :)

[dschuff]

Deprecation is progressing (https://groups.google.com/a/chromium.org/g/chromium-extensions/c/v8H1UHnPotY/m/NmzrIv_VBAAJ) but we are still supporting it on some platforms, (and using clang's upstream support), so we aren't there yet.

[brad]

In D78441#4593287, @dschuff wrote:

Deprecation is progressing (https://groups.google.com/a/chromium.org/g/chromium-extensions/c/v8H1UHnPotY/m/NmzrIv_VBAAJ) but we are still supporting it on some platforms, (and using clang's upstream support), so we aren't there yet.

Ok, it's a bit confusing with different dates in different spots. So according to that the mainstream OS (Win/macOS/Linux) releases of Chromium will drop support by Dec 2023 just leaving ChromeOS support.

[dschuff]

In D78441#4602312, @brad wrote:

In D78441#4593287, @dschuff wrote:

Deprecation is progressing (https://groups.google.com/a/chromium.org/g/chromium-extensions/c/v8H1UHnPotY/m/NmzrIv_VBAAJ) but we are still supporting it on some platforms, (and using clang's upstream support), so we aren't there yet.

Ok, it's a bit confusing with different dates in different spots. So according to that the mainstream OS (Win/macOS/Linux) releases of Chromium will drop support by Dec 2023 just leaving ChromeOS support.

Correct.

clang/include/clang/Basic/BuiltinsLe64.def

-//==- BuiltinsLe64.def - Le64 Builtin function database ----------*- C++ -*-==//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the Le64-specific builtin function database.  Users of this
-// file must define the BUILTIN macro to make use of this information.
-//
-//===----------------------------------------------------------------------===//
-
-// The format of this database matches clang/Basic/Builtins.def.
-
-BUILTIN(__clear_cache, "vv*v*", "i")
-
-#undef BUILTIN

clang/include/clang/Basic/TargetBuiltins.h

namespace XCore {
     enum {
         LastTIBuiltin = clang::Builtin::FirstTSBuiltin-1,
 #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
 #include "clang/Basic/BuiltinsXCore.def"
         LastTSBuiltin
     };
   }
 
-  /// Le64 builtins
-  namespace Le64 {
-  enum {
-    LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
-  #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
-  #include "clang/Basic/BuiltinsLe64.def"
-    LastTSBuiltin
-  };
-  }
-
   /// SystemZ builtins
   namespace SystemZ {
     enum {
         LastTIBuiltin = clang::Builtin::FirstTSBuiltin-1,
 #define BUILTIN(ID, TYPE, ATTRS) BI##ID,
 #include "clang/Basic/BuiltinsSystemZ.def"
         LastTSBuiltin
     };

clang/include/clang/Basic/TargetInfo.h

enum BuiltinVaListKind {
 
     /// typedef void* __builtin_va_list;
     VoidPtrBuiltinVaList,
 
     /// __builtin_va_list as defined by the AArch64 ABI
     /// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055a/IHI0055A_aapcs64.pdf
     AArch64ABIBuiltinVaList,
 
-    /// __builtin_va_list as defined by the PNaCl ABI:
-    /// http://www.chromium.org/nativeclient/pnacl/bitcode-abi#TOC-Machine-Types
-    PNaClABIBuiltinVaList,
-
     /// __builtin_va_list as defined by the Power ABI:
     /// https://www.power.org
     ///        /resources/downloads/Power-Arch-32-bit-ABI-supp-1.0-Embedded.pdf
     PowerABIBuiltinVaList,
 
     /// __builtin_va_list as defined by the x86-64 ABI:
     /// http://refspecs.linuxbase.org/elf/x86_64-abi-0.21.pdf
     X86_64ABIBuiltinVaList,

clang/include/clang/module.modulemap

module Clang_Basic {
   textual header "Basic/BuiltinsAArch64.def"
   textual header "Basic/BuiltinsAMDGPU.def"
   textual header "Basic/BuiltinsARM.def"
   textual header "Basic/BuiltinsBPF.def"
   textual header "Basic/Builtins.def"
   textual header "Basic/BuiltinsHexagon.def"
   textual header "Basic/BuiltinsHexagonDep.def"
   textual header "Basic/BuiltinsHexagonMapCustomDep.def"
-  textual header "Basic/BuiltinsLe64.def"
   textual header "Basic/BuiltinsMips.def"
   textual header "Basic/BuiltinsNEON.def"
   textual header "Basic/BuiltinsNVPTX.def"
   textual header "Basic/BuiltinsPPC.def"
   textual header "Basic/BuiltinsSVE.def"
   textual header "Basic/BuiltinsSystemZ.def"
   textual header "Basic/BuiltinsWebAssembly.def"
   textual header "Basic/BuiltinsX86.def"

clang/lib/AST/ASTContext.cpp

static TypedefDecl *CreateVaListDecl(const ASTContext *Context,
   case TargetInfo::VoidPtrBuiltinVaList:
     return CreateVoidPtrBuiltinVaListDecl(Context);
   case TargetInfo::AArch64ABIBuiltinVaList:
     return CreateAArch64ABIBuiltinVaListDecl(Context);
   case TargetInfo::PowerABIBuiltinVaList:
     return CreatePowerABIBuiltinVaListDecl(Context);
   case TargetInfo::X86_64ABIBuiltinVaList:
     return CreateX86_64ABIBuiltinVaListDecl(Context);
-  case TargetInfo::PNaClABIBuiltinVaList:
-    return CreatePNaClABIBuiltinVaListDecl(Context);
   case TargetInfo::AAPCSABIBuiltinVaList:
     return CreateAAPCSABIBuiltinVaListDecl(Context);
   case TargetInfo::SystemZBuiltinVaList:
     return CreateSystemZBuiltinVaListDecl(Context);
   case TargetInfo::HexagonBuiltinVaList:
     return CreateHexagonBuiltinVaListDecl(Context);
   }
 

clang/lib/Basic/CMakeLists.txt

add_clang_library(clangBasic
   Targets/AArch64.cpp
   Targets/AMDGPU.cpp
   Targets/ARC.cpp
   Targets/ARM.cpp
   Targets/AVR.cpp
   Targets/BPF.cpp
   Targets/Hexagon.cpp
   Targets/Lanai.cpp
-  Targets/Le64.cpp
   Targets/MSP430.cpp
   Targets/Mips.cpp
   Targets/NVPTX.cpp
   Targets/OSTargets.cpp
-  Targets/PNaCl.cpp
   Targets/PPC.cpp
   Targets/RISCV.cpp
   Targets/SPIR.cpp
   Targets/Sparc.cpp
   Targets/SystemZ.cpp
   Targets/TCE.cpp
   Targets/WebAssembly.cpp
   Targets/X86.cpp

clang/lib/Basic/Targets.cpp

 #include "Targets/AArch64.h"
 #include "Targets/AMDGPU.h"
 #include "Targets/ARC.h"
 #include "Targets/ARM.h"
 #include "Targets/AVR.h"
 #include "Targets/BPF.h"
 #include "Targets/Hexagon.h"
 #include "Targets/Lanai.h"
-#include "Targets/Le64.h"
 #include "Targets/MSP430.h"
 #include "Targets/Mips.h"
 #include "Targets/NVPTX.h"
 #include "Targets/OSTargets.h"
-#include "Targets/PNaCl.h"
 #include "Targets/PPC.h"
 #include "Targets/RISCV.h"
 #include "Targets/SPIR.h"
 #include "Targets/Sparc.h"
 #include "Targets/SystemZ.h"
 #include "Targets/TCE.h"
 #include "Targets/WebAssembly.h"
 #include "Targets/X86.h"
case llvm::Triple::thumb:
     case llvm::Triple::FreeBSD:
       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
     case llvm::Triple::NetBSD:
       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
     case llvm::Triple::OpenBSD:
       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts);
     case llvm::Triple::RTEMS:
       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts);
-    case llvm::Triple::NaCl:
-      return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts);
     case llvm::Triple::Win32:
       switch (Triple.getEnvironment()) {
       case llvm::Triple::Cygnus:
         return new CygwinARMTargetInfo(Triple, Opts);
       case llvm::Triple::GNU:
         return new MinGWARMTargetInfo(Triple, Opts);
       case llvm::Triple::Itanium:
         return new ItaniumWindowsARMleTargetInfo(Triple, Opts);
case llvm::Triple::thumbeb:
     case llvm::Triple::FreeBSD:
       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
     case llvm::Triple::NetBSD:
       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
     case llvm::Triple::OpenBSD:
       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts);
     case llvm::Triple::RTEMS:
       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts);
-    case llvm::Triple::NaCl:
-      return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts);
     default:
       return new ARMbeTargetInfo(Triple, Opts);
     }
 
   case llvm::Triple::avr:
     return new AVRTargetInfo(Triple, Opts);
   case llvm::Triple::bpfeb:
   case llvm::Triple::bpfel:
case llvm::Triple::mipsel:
     case llvm::Triple::Linux:
       return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
     case llvm::Triple::RTEMS:
       return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts);
     case llvm::Triple::FreeBSD:
       return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
     case llvm::Triple::NetBSD:
       return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
-    case llvm::Triple::NaCl:
-      return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts);
     default:
       return new MipsTargetInfo(Triple, Opts);
     }
 
   case llvm::Triple::mips64:
     switch (os) {
     case llvm::Triple::Linux:
       return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts);
case llvm::Triple::mips64el:
     case llvm::Triple::NetBSD:
       return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
     case llvm::Triple::OpenBSD:
       return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts);
     default:
       return new MipsTargetInfo(Triple, Opts);
     }
 
-  case llvm::Triple::le32:
-    switch (os) {
-    case llvm::Triple::NaCl:
-      return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts);
-    default:
-      return nullptr;
-    }
-
-  case llvm::Triple::le64:
-    return new Le64TargetInfo(Triple, Opts);
-
   case llvm::Triple::ppc:
     if (Triple.isOSDarwin())
       return new DarwinPPC32TargetInfo(Triple, Opts);
     switch (os) {
     case llvm::Triple::Linux:
       return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts);
     case llvm::Triple::FreeBSD:
       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts);
case llvm::Triple::Win32: {
       default: // Assume MSVC for unknown environments
         return new MicrosoftX86_32TargetInfo(Triple, Opts);
       }
     }
     case llvm::Triple::Haiku:
       return new HaikuX86_32TargetInfo(Triple, Opts);
     case llvm::Triple::RTEMS:
       return new RTEMSX86_32TargetInfo(Triple, Opts);
-    case llvm::Triple::NaCl:
-      return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts);
     case llvm::Triple::ELFIAMCU:
       return new MCUX86_32TargetInfo(Triple, Opts);
     case llvm::Triple::Hurd:
       return new HurdTargetInfo<X86_32TargetInfo>(Triple, Opts);
     default:
       return new X86_32TargetInfo(Triple, Opts);
     }
 
case llvm::Triple::Win32: {
         return new MinGWX86_64TargetInfo(Triple, Opts);
       case llvm::Triple::MSVC:
       default: // Assume MSVC for unknown environments
         return new MicrosoftX86_64TargetInfo(Triple, Opts);
       }
     }
     case llvm::Triple::Haiku:
       return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts);
-    case llvm::Triple::NaCl:
-      return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts);
     case llvm::Triple::PS4:
       return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts);
     default:
       return new X86_64TargetInfo(Triple, Opts);
     }
 
   case llvm::Triple::spir: {
     if (Triple.getOS() != llvm::Triple::UnknownOS ||

clang/lib/Basic/Targets/ARM.cpp

resetDataLayout("e"
                     "-m:w"
                     "-p:32:32"
                     "-Fi8"
                     "-i64:64"
                     "-v128:64:128"
                     "-a:0:32"
                     "-n32"
                     "-S64");
-  } else if (T.isOSNaCl()) {
-    assert(!BigEndian && "NaCl on ARM does not support big endian");
-    resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
   } else {
     resetDataLayout(BigEndian
                         ? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
                         : "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64");
   }
 
   // FIXME: Enumerated types are variable width in straight AAPCS.
 }

clang/lib/Basic/Targets/Le64.h

-//===--- Le64.h - Declare Le64 target feature support -----------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares Le64 TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_LE64_H
-#define LLVM_CLANG_LIB_BASIC_TARGETS_LE64_H
-
-#include "clang/Basic/TargetInfo.h"
-#include "clang/Basic/TargetOptions.h"
-#include "llvm/ADT/Triple.h"
-#include "llvm/Support/Compiler.h"
-
-namespace clang {
-namespace targets {
-
-class LLVM_LIBRARY_VISIBILITY Le64TargetInfo : public TargetInfo {
-  static const Builtin::Info BuiltinInfo[];
-
-public:
-  Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
-      : TargetInfo(Triple) {
-    NoAsmVariants = true;
-    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
-    resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
-  }
-
-  void getTargetDefines(const LangOptions &Opts,
-                        MacroBuilder &Builder) const override;
-
-  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
-
-  BuiltinVaListKind getBuiltinVaListKind() const override {
-    return TargetInfo::PNaClABIBuiltinVaList;
-  }
-
-  const char *getClobbers() const override { return ""; }
-
-  ArrayRef<const char *> getGCCRegNames() const override { return None; }
-
-  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
-    return None;
-  }
-
-  bool validateAsmConstraint(const char *&Name,
-                             TargetInfo::ConstraintInfo &Info) const override {
-    return false;
-  }
-
-  bool hasProtectedVisibility() const override { return false; }
-};
-
-} // namespace targets
-} // namespace clang
-#endif // LLVM_CLANG_LIB_BASIC_TARGETS_LE64_H

clang/lib/Basic/Targets/Le64.cpp

-//===--- Le64.cpp - Implement Le64 target feature support -----------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements Le64 TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Le64.h"
-#include "Targets.h"
-#include "clang/Basic/Builtins.h"
-#include "clang/Basic/MacroBuilder.h"
-#include "clang/Basic/TargetBuiltins.h"
-
-using namespace clang;
-using namespace clang::targets;
-
-const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
-#define BUILTIN(ID, TYPE, ATTRS)                                               \
-  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
-#include "clang/Basic/BuiltinsLe64.def"
-};
-
-ArrayRef<Builtin::Info> Le64TargetInfo::getTargetBuiltins() const {
-  return llvm::makeArrayRef(BuiltinInfo, clang::Le64::LastTSBuiltin -
-                                             Builtin::FirstTSBuiltin);
-}
-
-void Le64TargetInfo::getTargetDefines(const LangOptions &Opts,
-                                      MacroBuilder &Builder) const {
-  DefineStd(Builder, "unix", Opts);
-  defineCPUMacros(Builder, "le64", /*Tuning=*/false);
-  Builder.defineMacro("__ELF__");
-}

clang/lib/Basic/Targets/OSTargets.h

 public:
   WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : OSTargetInfo<Target>(Triple, Opts) {
     this->WCharType = TargetInfo::UnsignedShort;
     this->WIntType = TargetInfo::UnsignedShort;
   }
 };
 
-template <typename Target>
-class LLVM_LIBRARY_VISIBILITY NaClTargetInfo : public OSTargetInfo<Target> {
-protected:
-  void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
-                    MacroBuilder &Builder) const override {
-    if (Opts.POSIXThreads)
-      Builder.defineMacro("_REENTRANT");
-    if (Opts.CPlusPlus)
-      Builder.defineMacro("_GNU_SOURCE");
-
-    DefineStd(Builder, "unix", Opts);
-    Builder.defineMacro("__ELF__");
-    Builder.defineMacro("__native_client__");
-  }
-
-public:
-  NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
-      : OSTargetInfo<Target>(Triple, Opts) {
-    this->LongAlign = 32;
-    this->LongWidth = 32;
-    this->PointerAlign = 32;
-    this->PointerWidth = 32;
-    this->IntMaxType = TargetInfo::SignedLongLong;
-    this->Int64Type = TargetInfo::SignedLongLong;
-    this->DoubleAlign = 64;
-    this->LongDoubleWidth = 64;
-    this->LongDoubleAlign = 64;
-    this->LongLongWidth = 64;
-    this->LongLongAlign = 64;
-    this->SizeType = TargetInfo::UnsignedInt;
-    this->PtrDiffType = TargetInfo::SignedInt;
-    this->IntPtrType = TargetInfo::SignedInt;
-    // RegParmMax is inherited from the underlying architecture.
-    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
-    if (Triple.getArch() == llvm::Triple::arm) {
-      // Handled in ARM's setABI().
-    } else if (Triple.getArch() == llvm::Triple::x86) {
-      this->resetDataLayout("e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-"
-                            "i64:64-n8:16:32-S128");
-    } else if (Triple.getArch() == llvm::Triple::x86_64) {
-      this->resetDataLayout("e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-"
-                            "i64:64-n8:16:32:64-S128");
-    } else if (Triple.getArch() == llvm::Triple::mipsel) {
-      // Handled on mips' setDataLayout.
-    } else {
-      assert(Triple.getArch() == llvm::Triple::le32);
-      this->resetDataLayout("e-p:32:32-i64:64");
-    }
-  }
-};
-
 // Fuchsia Target
 template <typename Target>
 class LLVM_LIBRARY_VISIBILITY FuchsiaTargetInfo : public OSTargetInfo<Target> {
 protected:
   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
                     MacroBuilder &Builder) const override {
     Builder.defineMacro("__Fuchsia__");
     Builder.defineMacro("__ELF__");

clang/lib/Basic/Targets/PNaCl.h

-//===--- PNaCl.h - Declare PNaCl target feature support ---------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares PNaCl TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H
-#define LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H
-
-#include "Mips.h"
-#include "clang/Basic/TargetInfo.h"
-#include "clang/Basic/TargetOptions.h"
-#include "llvm/ADT/Triple.h"
-#include "llvm/Support/Compiler.h"
-
-namespace clang {
-namespace targets {
-
-class LLVM_LIBRARY_VISIBILITY PNaClTargetInfo : public TargetInfo {
-public:
-  PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
-      : TargetInfo(Triple) {
-    this->LongAlign = 32;
-    this->LongWidth = 32;
-    this->PointerAlign = 32;
-    this->PointerWidth = 32;
-    this->IntMaxType = TargetInfo::SignedLongLong;
-    this->Int64Type = TargetInfo::SignedLongLong;
-    this->DoubleAlign = 64;
-    this->LongDoubleWidth = 64;
-    this->LongDoubleAlign = 64;
-    this->SizeType = TargetInfo::UnsignedInt;
-    this->PtrDiffType = TargetInfo::SignedInt;
-    this->IntPtrType = TargetInfo::SignedInt;
-    this->RegParmMax = 0; // Disallow regparm
-  }
-
-  void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const;
-
-  void getTargetDefines(const LangOptions &Opts,
-                        MacroBuilder &Builder) const override {
-    getArchDefines(Opts, Builder);
-  }
-
-  bool hasFeature(StringRef Feature) const override {
-    return Feature == "pnacl";
-  }
-
-  ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
-
-  BuiltinVaListKind getBuiltinVaListKind() const override {
-    return TargetInfo::PNaClABIBuiltinVaList;
-  }
-
-  ArrayRef<const char *> getGCCRegNames() const override;
-
-  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
-
-  bool validateAsmConstraint(const char *&Name,
-                             TargetInfo::ConstraintInfo &Info) const override {
-    return false;
-  }
-
-  const char *getClobbers() const override { return ""; }
-};
-
-// We attempt to use PNaCl (le32) frontend and Mips32EL backend.
-class LLVM_LIBRARY_VISIBILITY NaClMips32TargetInfo : public MipsTargetInfo {
-public:
-  NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
-      : MipsTargetInfo(Triple, Opts) {}
-
-  BuiltinVaListKind getBuiltinVaListKind() const override {
-    return TargetInfo::PNaClABIBuiltinVaList;
-  }
-};
-} // namespace targets
-} // namespace clang
-
-#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H

clang/lib/Basic/Targets/PNaCl.cpp

-//===--- PNaCl.cpp - Implement PNaCl target feature support ---------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements PNaCl TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#include "PNaCl.h"
-#include "clang/Basic/MacroBuilder.h"
-
-using namespace clang;
-using namespace clang::targets;
-
-ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { return None; }
-
-ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
-  return None;
-}
-
-void PNaClTargetInfo::getArchDefines(const LangOptions &Opts,
-                                     MacroBuilder &Builder) const {
-  Builder.defineMacro("__le32__");
-  Builder.defineMacro("__pnacl__");
-}

clang/lib/CodeGen/TargetInfo.cpp

bool IsIndirect = isAggregateTypeForABI(Ty) &&
                     !isEmptyRecord(getContext(), Ty, true) &&
                     !isSingleElementStruct(Ty, getContext());
   return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
                           getContext().getTypeInfoInChars(Ty),
                           CharUnits::fromQuantity(4),
                           /*AllowHigherAlign=*/true);
 }
 
-//===----------------------------------------------------------------------===//
-// le32/PNaCl bitcode ABI Implementation
-//
-// This is a simplified version of the x86_32 ABI.  Arguments and return values
-// are always passed on the stack.
-//===----------------------------------------------------------------------===//
-
-class PNaClABIInfo : public ABIInfo {
- public:
-  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
-
-  ABIArgInfo classifyReturnType(QualType RetTy) const;
-  ABIArgInfo classifyArgumentType(QualType RetTy) const;
-
-  void computeInfo(CGFunctionInfo &FI) const override;
-  Address EmitVAArg(CodeGenFunction &CGF,
-                    Address VAListAddr, QualType Ty) const override;
-};
-
-class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
- public:
-  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
-    : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
-};
-
-void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
-  if (!getCXXABI().classifyReturnType(FI))
-    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
-
-  for (auto &I : FI.arguments())
-    I.info = classifyArgumentType(I.type);
-}
-
-Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
-                                QualType Ty) const {
-  // The PNaCL ABI is a bit odd, in that varargs don't use normal
-  // function classification. Structs get passed directly for varargs
-  // functions, through a rewriting transform in
-  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
-  // this target to actually support a va_arg instructions with an
-  // aggregate type, unlike other targets.
-  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
-}
-
-/// Classify argument of given type \p Ty.
-ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
-  if (isAggregateTypeForABI(Ty)) {
-    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
-      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
-    return getNaturalAlignIndirect(Ty);
-  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
-    // Treat an enum type as its underlying type.
-    Ty = EnumTy->getDecl()->getIntegerType();
-  } else if (Ty->isFloatingType()) {
-    // Floating-point types don't go inreg.
-    return ABIArgInfo::getDirect();
-  }
-
-  return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty)
-                                        : ABIArgInfo::getDirect());
-}
-
-ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
-  if (RetTy->isVoidType())
-    return ABIArgInfo::getIgnore();
-
-  // In the PNaCl ABI we always return records/structures on the stack.
-  if (isAggregateTypeForABI(RetTy))
-    return getNaturalAlignIndirect(RetTy);
-
-  // Treat an enum type as its underlying type.
-  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
-    RetTy = EnumTy->getDecl()->getIntegerType();
-
-  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
-                                           : ABIArgInfo::getDirect());
-}
-
 /// IsX86_MMXType - Return true if this is an MMX type.
 bool IsX86_MMXType(llvm::Type *IRType) {
   // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
   return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
     cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
     IRType->getScalarSizeInBits() != 64;
 }
 
GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
 
   // To handle this, we have to increase the size of the low part so that the
   // second element will start at an 8 byte offset.  We can't increase the size
   // of the second element because it might make us access off the end of the
   // struct.
   if (HiStart != 8) {
     // There are usually two sorts of types the ABI generation code can produce
     // for the low part of a pair that aren't 8 bytes in size: float or
-    // i8/i16/i32.  This can also include pointers when they are 32-bit (X32 and
-    // NaCl).
+    // i8/i16/i32.  This can also include pointers when they are 32-bit (X32).
     // Promote these to a larger type.
     if (Lo->isFloatTy())
       Lo = llvm::Type::getDoubleTy(Lo->getContext());
     else {
       assert((Lo->isIntegerTy() || Lo->isPointerTy())
              && "Invalid/unknown lo type");
       Lo = llvm::Type::getInt64Ty(Lo->getContext());
     }
auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
     return *P;
   };
 
   const llvm::Triple &Triple = getTarget().getTriple();
   switch (Triple.getArch()) {
   default:
     return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
 
-  case llvm::Triple::le32:
-    return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
   case llvm::Triple::mips:
   case llvm::Triple::mipsel:
-    if (Triple.getOS() == llvm::Triple::NaCl)
-      return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
     return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
 
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
     return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
 
   case llvm::Triple::avr:
     return SetCGInfo(new AVRTargetCodeGenInfo(Types));

clang/lib/Driver/CMakeLists.txt

add_clang_library(clangDriver
   ToolChains/Hurd.cpp
   ToolChains/Linux.cpp
   ToolChains/MipsLinux.cpp
   ToolChains/MinGW.cpp
   ToolChains/Minix.cpp
   ToolChains/MSP430.cpp
   ToolChains/MSVC.cpp
   ToolChains/Myriad.cpp
-  ToolChains/NaCl.cpp
   ToolChains/NetBSD.cpp
   ToolChains/OpenBSD.cpp
   ToolChains/PS4CPU.cpp
   ToolChains/RISCVToolchain.cpp
   ToolChains/Solaris.cpp
   ToolChains/TCE.cpp
   ToolChains/WebAssembly.cpp
   ToolChains/XCore.cpp

clang/lib/Driver/Driver.cpp

 #include "ToolChains/Lanai.h"
 #include "ToolChains/Linux.h"
 #include "ToolChains/MSP430.h"
 #include "ToolChains/MSVC.h"
 #include "ToolChains/MinGW.h"
 #include "ToolChains/Minix.h"
 #include "ToolChains/MipsLinux.h"
 #include "ToolChains/Myriad.h"
-#include "ToolChains/NaCl.h"
 #include "ToolChains/NetBSD.h"
 #include "ToolChains/OpenBSD.h"
 #include "ToolChains/PPCLinux.h"
 #include "ToolChains/PS4CPU.h"
 #include "ToolChains/RISCVToolchain.h"
 #include "ToolChains/Solaris.h"
 #include "ToolChains/TCE.h"
 #include "ToolChains/WebAssembly.h"
case llvm::Triple::ELFIAMCU:
       else if (Target.getArch() == llvm::Triple::ppc ||
                Target.getArch() == llvm::Triple::ppc64 ||
                Target.getArch() == llvm::Triple::ppc64le)
         TC = std::make_unique<toolchains::PPCLinuxToolChain>(*this, Target,
                                                               Args);
       else
         TC = std::make_unique<toolchains::Linux>(*this, Target, Args);
       break;
-    case llvm::Triple::NaCl:
-      TC = std::make_unique<toolchains::NaClToolChain>(*this, Target, Args);
-      break;
     case llvm::Triple::Fuchsia:
       TC = std::make_unique<toolchains::Fuchsia>(*this, Target, Args);
       break;
     case llvm::Triple::Solaris:
       TC = std::make_unique<toolchains::Solaris>(*this, Target, Args);
       break;
     case llvm::Triple::AMDHSA:
       TC = std::make_unique<toolchains::ROCMToolChain>(*this, Target, Args);

clang/lib/Driver/ToolChains/Arch/ARM.cpp

else if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
     // Linux targets support unaligned accesses. The same goes for NaCl.
     //
     // The above behavior is consistent with GCC.
     int VersionNum = getARMSubArchVersionNumber(Triple);
     if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
       if (VersionNum < 6 ||
           Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
         Features.push_back("+strict-align");
-    } else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
+    } else if (Triple.isOSLinux()) {
       if (VersionNum < 7)
         Features.push_back("+strict-align");
     } else
       Features.push_back("+strict-align");
   }
 
   // llvm does not support reserving registers in general. There is support
   // for reserving r9 on ARM though (defined as a platform-specific register

clang/lib/Driver/ToolChains/NaCl.h

-//===--- NaCl.h - Native Client ToolChain Implementations -------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_NACL_H
-#define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_NACL_H
-
-#include "Gnu.h"
-#include "clang/Driver/Tool.h"
-#include "clang/Driver/ToolChain.h"
-
-namespace clang {
-namespace driver {
-namespace tools {
-namespace nacltools {
-class LLVM_LIBRARY_VISIBILITY AssemblerARM : public gnutools::Assembler {
-public:
-  AssemblerARM(const ToolChain &TC) : gnutools::Assembler(TC) {}
-
-  void ConstructJob(Compilation &C, const JobAction &JA,
-                    const InputInfo &Output, const InputInfoList &Inputs,
-                    const llvm::opt::ArgList &TCArgs,
-                    const char *LinkingOutput) const override;
-};
-
-class LLVM_LIBRARY_VISIBILITY Linker : public GnuTool {
-public:
-  Linker(const ToolChain &TC) : GnuTool("NaCl::Linker", "linker", TC) {}
-
-  bool hasIntegratedCPP() const override { return false; }
-  bool isLinkJob() const override { return true; }
-
-  void ConstructJob(Compilation &C, const JobAction &JA,
-                    const InputInfo &Output, const InputInfoList &Inputs,
-                    const llvm::opt::ArgList &TCArgs,
-                    const char *LinkingOutput) const override;
-};
-} // end namespace nacltools
-} // end namespace tools
-
-namespace toolchains {
-
-class LLVM_LIBRARY_VISIBILITY NaClToolChain : public Generic_ELF {
-public:
-  NaClToolChain(const Driver &D, const llvm::Triple &Triple,
-                const llvm::opt::ArgList &Args);
-
-  void
-  AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
-                            llvm::opt::ArgStringList &CC1Args) const override;
-  void addLibCxxIncludePaths(
-      const llvm::opt::ArgList &DriverArgs,
-      llvm::opt::ArgStringList &CC1Args) const override;
-
-  CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override;
-
-  void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args,
-                           llvm::opt::ArgStringList &CmdArgs) const override;
-
-  bool IsIntegratedAssemblerDefault() const override {
-    return getTriple().getArch() == llvm::Triple::mipsel;
-  }
-
-  // Get the path to the file containing NaCl's ARM macros.
-  // It lives in NaClToolChain because the ARMAssembler tool needs a
-  // const char * that it can pass around,
-  const char *GetNaClArmMacrosPath() const { return NaClArmMacrosPath.c_str(); }
-
-  std::string ComputeEffectiveClangTriple(const llvm::opt::ArgList &Args,
-                                          types::ID InputType) const override;
-
-protected:
-  Tool *buildLinker() const override;
-  Tool *buildAssembler() const override;
-
-private:
-  std::string NaClArmMacrosPath;
-};
-
-} // end namespace toolchains
-} // end namespace driver
-} // end namespace clang
-
-#endif // LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_NACL_H

clang/lib/Driver/ToolChains/NaCl.cpp

-//===--- NaCl.cpp - Native Client ToolChain Implementations -----*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "NaCl.h"
-#include "InputInfo.h"
-#include "CommonArgs.h"
-#include "clang/Driver/Compilation.h"
-#include "clang/Driver/Driver.h"
-#include "clang/Driver/DriverDiagnostic.h"
-#include "clang/Driver/Options.h"
-#include "llvm/Option/ArgList.h"
-#include "llvm/Support/Path.h"
-
-using namespace clang::driver;
-using namespace clang::driver::tools;
-using namespace clang::driver::toolchains;
-using namespace clang;
-using namespace llvm::opt;
-
-// NaCl ARM assembly (inline or standalone) can be written with a set of macros
-// for the various SFI requirements like register masking. The assembly tool
-// inserts the file containing the macros as an input into all the assembly
-// jobs.
-void nacltools::AssemblerARM::ConstructJob(Compilation &C, const JobAction &JA,
-                                           const InputInfo &Output,
-                                           const InputInfoList &Inputs,
-                                           const ArgList &Args,
-                                           const char *LinkingOutput) const {
-  const toolchains::NaClToolChain &ToolChain =
-      static_cast<const toolchains::NaClToolChain &>(getToolChain());
-  InputInfo NaClMacros(types::TY_PP_Asm, ToolChain.GetNaClArmMacrosPath(),
-                       "nacl-arm-macros.s");
-  InputInfoList NewInputs;
-  NewInputs.push_back(NaClMacros);
-  NewInputs.append(Inputs.begin(), Inputs.end());
-  gnutools::Assembler::ConstructJob(C, JA, Output, NewInputs, Args,
-                                    LinkingOutput);
-}
-
-// This is quite similar to gnutools::Linker::ConstructJob with changes that
-// we use static by default, do not yet support sanitizers or LTO, and a few
-// others. Eventually we can support more of that and hopefully migrate back
-// to gnutools::Linker.
-void nacltools::Linker::ConstructJob(Compilation &C, const JobAction &JA,
-                                     const InputInfo &Output,
-                                     const InputInfoList &Inputs,
-                                     const ArgList &Args,
-                                     const char *LinkingOutput) const {
-
-  const toolchains::NaClToolChain &ToolChain =
-      static_cast<const toolchains::NaClToolChain &>(getToolChain());
-  const Driver &D = ToolChain.getDriver();
-  const llvm::Triple::ArchType Arch = ToolChain.getArch();
-  const bool IsStatic =
-      !Args.hasArg(options::OPT_dynamic) && !Args.hasArg(options::OPT_shared);
-
-  ArgStringList CmdArgs;
-
-  // Silence warning for "clang -g foo.o -o foo"
-  Args.ClaimAllArgs(options::OPT_g_Group);
-  // and "clang -emit-llvm foo.o -o foo"
-  Args.ClaimAllArgs(options::OPT_emit_llvm);
-  // and for "clang -w foo.o -o foo". Other warning options are already
-  // handled somewhere else.
-  Args.ClaimAllArgs(options::OPT_w);
-
-  if (!D.SysRoot.empty())
-    CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
-
-  if (Args.hasArg(options::OPT_rdynamic))
-    CmdArgs.push_back("-export-dynamic");
-
-  if (Args.hasArg(options::OPT_s))
-    CmdArgs.push_back("-s");
-
-  // NaClToolChain doesn't have ExtraOpts like Linux; the only relevant flag
-  // from there is --build-id, which we do want.
-  CmdArgs.push_back("--build-id");
-
-  if (!IsStatic)
-    CmdArgs.push_back("--eh-frame-hdr");
-
-  CmdArgs.push_back("-m");
-  if (Arch == llvm::Triple::x86)
-    CmdArgs.push_back("elf_i386_nacl");
-  else if (Arch == llvm::Triple::arm)
-    CmdArgs.push_back("armelf_nacl");
-  else if (Arch == llvm::Triple::x86_64)
-    CmdArgs.push_back("elf_x86_64_nacl");
-  else if (Arch == llvm::Triple::mipsel)
-    CmdArgs.push_back("mipselelf_nacl");
-  else
-    D.Diag(diag::err_target_unsupported_arch) << ToolChain.getArchName()
-                                              << "Native Client";
-
-  if (IsStatic)
-    CmdArgs.push_back("-static");
-  else if (Args.hasArg(options::OPT_shared))
-    CmdArgs.push_back("-shared");
-
-  CmdArgs.push_back("-o");
-  CmdArgs.push_back(Output.getFilename());
-  if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) {
-    if (!Args.hasArg(options::OPT_shared))
-      CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt1.o")));
-    CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crti.o")));
-
-    const char *crtbegin;
-    if (IsStatic)
-      crtbegin = "crtbeginT.o";
-    else if (Args.hasArg(options::OPT_shared))
-      crtbegin = "crtbeginS.o";
-    else
-      crtbegin = "crtbegin.o";
-    CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin)));
-  }
-
-  Args.AddAllArgs(CmdArgs, options::OPT_L);
-  Args.AddAllArgs(CmdArgs, options::OPT_u);
-
-  ToolChain.AddFilePathLibArgs(Args, CmdArgs);
-
-  if (Args.hasArg(options::OPT_Z_Xlinker__no_demangle))
-    CmdArgs.push_back("--no-demangle");
-
-  AddLinkerInputs(ToolChain, Inputs, Args, CmdArgs, JA);
-
-  if (D.CCCIsCXX() &&
-      !Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs)) {
-    if (ToolChain.ShouldLinkCXXStdlib(Args)) {
-      bool OnlyLibstdcxxStatic =
-          Args.hasArg(options::OPT_static_libstdcxx) && !IsStatic;
-      if (OnlyLibstdcxxStatic)
-        CmdArgs.push_back("-Bstatic");
-      ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs);
-      if (OnlyLibstdcxxStatic)
-        CmdArgs.push_back("-Bdynamic");
-    }
-    CmdArgs.push_back("-lm");
-  }
-
-  if (!Args.hasArg(options::OPT_nostdlib)) {
-    if (!Args.hasArg(options::OPT_nodefaultlibs)) {
-      // Always use groups, since it has no effect on dynamic libraries.
-      CmdArgs.push_back("--start-group");
-      CmdArgs.push_back("-lc");
-      // NaCl's libc++ currently requires libpthread, so just always include it
-      // in the group for C++.
-      if (Args.hasArg(options::OPT_pthread) ||
-          Args.hasArg(options::OPT_pthreads) || D.CCCIsCXX()) {
-        // Gold, used by Mips, handles nested groups differently than ld, and
-        // without '-lnacl' it prefers symbols from libpthread.a over libnacl.a,
-        // which is not a desired behaviour here.
-        // See https://sourceware.org/ml/binutils/2015-03/msg00034.html
-        if (getToolChain().getArch() == llvm::Triple::mipsel)
-          CmdArgs.push_back("-lnacl");
-
-        CmdArgs.push_back("-lpthread");
-      }
-
-      CmdArgs.push_back("-lgcc");
-      CmdArgs.push_back("--as-needed");
-      if (IsStatic)
-        CmdArgs.push_back("-lgcc_eh");
-      else
-        CmdArgs.push_back("-lgcc_s");
-      CmdArgs.push_back("--no-as-needed");
-
-      // Mips needs to create and use pnacl_legacy library that contains
-      // definitions from bitcode/pnaclmm.c and definitions for
-      // __nacl_tp_tls_offset() and __nacl_tp_tdb_offset().
-      if (getToolChain().getArch() == llvm::Triple::mipsel)
-        CmdArgs.push_back("-lpnacl_legacy");
-
-      CmdArgs.push_back("--end-group");
-    }
-
-    if (!Args.hasArg(options::OPT_nostartfiles)) {
-      const char *crtend;
-      if (Args.hasArg(options::OPT_shared))
-        crtend = "crtendS.o";
-      else
-        crtend = "crtend.o";
-
-      CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtend)));
-      CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crtn.o")));
-    }
-  }
-
-  const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath());
-  C.addCommand(std::make_unique<Command>(JA, *this, Exec, CmdArgs, Inputs));
-}
-
-/// NaCl Toolchain
-NaClToolChain::NaClToolChain(const Driver &D, const llvm::Triple &Triple,
-                             const ArgList &Args)
-    : Generic_ELF(D, Triple, Args) {
-
-  // Remove paths added by Generic_GCC. NaCl Toolchain cannot use the
-  // default paths, and must instead only use the paths provided
-  // with this toolchain based on architecture.
-  path_list &file_paths = getFilePaths();
-  path_list &prog_paths = getProgramPaths();
-
-  file_paths.clear();
-  prog_paths.clear();
-
-  // Path for library files (libc.a, ...)
-  std::string FilePath(getDriver().Dir + "/../");
-
-  // Path for tools (clang, ld, etc..)
-  std::string ProgPath(getDriver().Dir + "/../");
-
-  // Path for toolchain libraries (libgcc.a, ...)
-  std::string ToolPath(getDriver().ResourceDir + "/lib/");
-
-  switch (Triple.getArch()) {
-  case llvm::Triple::x86:
-    file_paths.push_back(FilePath + "x86_64-nacl/lib32");
-    file_paths.push_back(FilePath + "i686-nacl/usr/lib");
-    prog_paths.push_back(ProgPath + "x86_64-nacl/bin");
-    file_paths.push_back(ToolPath + "i686-nacl");
-    break;
-  case llvm::Triple::x86_64:
-    file_paths.push_back(FilePath + "x86_64-nacl/lib");
-    file_paths.push_back(FilePath + "x86_64-nacl/usr/lib");
-    prog_paths.push_back(ProgPath + "x86_64-nacl/bin");
-    file_paths.push_back(ToolPath + "x86_64-nacl");
-    break;
-  case llvm::Triple::arm:
-    file_paths.push_back(FilePath + "arm-nacl/lib");
-    file_paths.push_back(FilePath + "arm-nacl/usr/lib");
-    prog_paths.push_back(ProgPath + "arm-nacl/bin");
-    file_paths.push_back(ToolPath + "arm-nacl");
-    break;
-  case llvm::Triple::mipsel:
-    file_paths.push_back(FilePath + "mipsel-nacl/lib");
-    file_paths.push_back(FilePath + "mipsel-nacl/usr/lib");
-    prog_paths.push_back(ProgPath + "bin");
-    file_paths.push_back(ToolPath + "mipsel-nacl");
-    break;
-  default:
-    break;
-  }
-
-  NaClArmMacrosPath = GetFilePath("nacl-arm-macros.s");
-}
-
-void NaClToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
-                                              ArgStringList &CC1Args) const {
-  const Driver &D = getDriver();
-  if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc))
-    return;
-
-  if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
-    SmallString<128> P(D.ResourceDir);
-    llvm::sys::path::append(P, "include");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-  }
-
-  if (DriverArgs.hasArg(options::OPT_nostdlibinc))
-    return;
-
-  SmallString<128> P(D.Dir + "/../");
-  switch (getTriple().getArch()) {
-  case llvm::Triple::x86:
-    // x86 is special because multilib style uses x86_64-nacl/include for libc
-    // headers but the SDK wants i686-nacl/usr/include. The other architectures
-    // have the same substring.
-    llvm::sys::path::append(P, "i686-nacl/usr/include");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-    llvm::sys::path::remove_filename(P);
-    llvm::sys::path::remove_filename(P);
-    llvm::sys::path::remove_filename(P);
-    llvm::sys::path::append(P, "x86_64-nacl/include");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-    return;
-  case llvm::Triple::arm:
-    llvm::sys::path::append(P, "arm-nacl/usr/include");
-    break;
-  case llvm::Triple::x86_64:
-    llvm::sys::path::append(P, "x86_64-nacl/usr/include");
-    break;
-  case llvm::Triple::mipsel:
-    llvm::sys::path::append(P, "mipsel-nacl/usr/include");
-    break;
-  default:
-    return;
-  }
-
-  addSystemInclude(DriverArgs, CC1Args, P.str());
-  llvm::sys::path::remove_filename(P);
-  llvm::sys::path::remove_filename(P);
-  llvm::sys::path::append(P, "include");
-  addSystemInclude(DriverArgs, CC1Args, P.str());
-}
-
-void NaClToolChain::AddCXXStdlibLibArgs(const ArgList &Args,
-                                        ArgStringList &CmdArgs) const {
-  // Check for -stdlib= flags. We only support libc++ but this consumes the arg
-  // if the value is libc++, and emits an error for other values.
-  GetCXXStdlibType(Args);
-  CmdArgs.push_back("-lc++");
-}
-
-void NaClToolChain::addLibCxxIncludePaths(
-    const llvm::opt::ArgList &DriverArgs,
-    llvm::opt::ArgStringList &CC1Args) const {
-  const Driver &D = getDriver();
-
-  SmallString<128> P(D.Dir + "/../");
-  switch (getTriple().getArch()) {
-  default:
-    break;
-  case llvm::Triple::arm:
-    llvm::sys::path::append(P, "arm-nacl/include/c++/v1");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-    break;
-  case llvm::Triple::x86:
-    llvm::sys::path::append(P, "x86_64-nacl/include/c++/v1");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-    break;
-  case llvm::Triple::x86_64:
-    llvm::sys::path::append(P, "x86_64-nacl/include/c++/v1");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-    break;
-  case llvm::Triple::mipsel:
-    llvm::sys::path::append(P, "mipsel-nacl/include/c++/v1");
-    addSystemInclude(DriverArgs, CC1Args, P.str());
-    break;
-  }
-}
-
-ToolChain::CXXStdlibType
-NaClToolChain::GetCXXStdlibType(const ArgList &Args) const {
-  if (Arg *A = Args.getLastArg(options::OPT_stdlib_EQ)) {
-    StringRef Value = A->getValue();
-    if (Value == "libc++")
-      return ToolChain::CST_Libcxx;
-    getDriver().Diag(clang::diag::err_drv_invalid_stdlib_name)
-        << A->getAsString(Args);
-  }
-
-  return ToolChain::CST_Libcxx;
-}
-
-std::string
-NaClToolChain::ComputeEffectiveClangTriple(const ArgList &Args,
-                                           types::ID InputType) const {
-  llvm::Triple TheTriple(ComputeLLVMTriple(Args, InputType));
-  if (TheTriple.getArch() == llvm::Triple::arm &&
-      TheTriple.getEnvironment() == llvm::Triple::UnknownEnvironment)
-    TheTriple.setEnvironment(llvm::Triple::GNUEABIHF);
-  return TheTriple.getTriple();
-}
-
-Tool *NaClToolChain::buildLinker() const {
-  return new tools::nacltools::Linker(*this);
-}
-
-Tool *NaClToolChain::buildAssembler() const {
-  if (getTriple().getArch() == llvm::Triple::arm)
-    return new tools::nacltools::AssemblerARM(*this);
-  return new tools::gnutools::Assembler(*this);
-}

clang/lib/Frontend/InitHeaderSearch.cpp

void InitHeaderSearch::AddDefaultCIncludePaths(const llvm::Triple &triple,
   }
 
   if (HSOpts.UseStandardSystemIncludes) {
     switch (os) {
     case llvm::Triple::CloudABI:
     case llvm::Triple::FreeBSD:
     case llvm::Triple::NetBSD:
     case llvm::Triple::OpenBSD:
-    case llvm::Triple::NaCl:
     case llvm::Triple::PS4:
     case llvm::Triple::ELFIAMCU:
     case llvm::Triple::Fuchsia:
       break;
     case llvm::Triple::Win32:
       if (triple.getEnvironment() != llvm::Triple::Cygnus)
         break;
       LLVM_FALLTHROUGH;
case llvm::Triple::Win32:
     break;
   default:
     break;
   }
 
   switch (os) {
   case llvm::Triple::CloudABI:
   case llvm::Triple::RTEMS:
-  case llvm::Triple::NaCl:
   case llvm::Triple::ELFIAMCU:
   case llvm::Triple::Fuchsia:
     break;
   case llvm::Triple::PS4: {
     // <isysroot> gets prepended later in AddPath().
     std::string BaseSDKPath = "";
     if (!HasSysroot) {
       const char *envValue = getenv("SCE_ORBIS_SDK_DIR");

clang/test/CodeGen/arm-aapcs-vfp.c

 // REQUIRES: arm-registered-target
 // REQUIRES: aarch64-registered-target
 // RUN: %clang_cc1 -triple thumbv7-apple-darwin9 \
 // RUN:   -target-abi aapcs \
 // RUN:   -target-cpu cortex-a8 \
 // RUN:   -mfloat-abi hard \
 // RUN:   -ffreestanding \
 // RUN:   -emit-llvm -w -o - %s | FileCheck %s
 
-// RUN: %clang_cc1 -triple armv7-unknown-nacl-gnueabi \
-// RUN:  -target-cpu cortex-a8 \
-// RUN:  -mfloat-abi hard \
-// RUN:  -ffreestanding \
-// RUN:  -emit-llvm -w -o - %s | FileCheck %s
-
 // RUN: %clang_cc1 -triple arm64-apple-darwin9 -target-feature +neon \
 // RUN:   -ffreestanding \
 // RUN:   -emit-llvm -w -o - %s | FileCheck -check-prefix=CHECK64 %s
 
 #include <arm_neon.h>
 
 struct homogeneous_struct {
   float f[2];

clang/test/CodeGen/le32-arguments.c

-// RUN: %clang_cc1 -triple le32-unknown-nacl %s -emit-llvm -o - | FileCheck %s
-
-// Basic argument/attribute tests for le32/PNaCl
-
-// CHECK-LABEL: define void @f0(i32 %i, i32 %j, double %k)
-void f0(int i, long j, double k) {}
-
-typedef struct {
-  int aa;
-  int bb;
-} s1;
-// Structs should be passed byval and not split up
-// CHECK-LABEL: define void @f1(%struct.s1* byval(%struct.s1) align 4 %i)
-void f1(s1 i) {}
-
-typedef struct {
-  int cc;
-} s2;
-// Structs should be returned sret and not simplified by the frontend
-// CHECK-LABEL: define void @f2(%struct.s2* noalias sret align 4 %agg.result)
-s2 f2() {
-  s2 foo;
-  return foo;
-}
-
-// CHECK-LABEL: define void @f3(i64 %i)
-void f3(long long i) {}
-
-// i8/i16 should be signext, i32 and higher should not
-// CHECK-LABEL: define void @f4(i8 signext %a, i16 signext %b)
-void f4(char a, short b) {}
-
-// CHECK-LABEL: define void @f5(i8 zeroext %a, i16 zeroext %b)
-void f5(unsigned char a, unsigned short b) {}
-
-
-enum my_enum {
-  ENUM1,
-  ENUM2,
-  ENUM3,
-};
-// Enums should be treated as the underlying i32
-// CHECK-LABEL: define void @f6(i32 %a)
-void f6(enum my_enum a) {}
-
-union simple_union {
-  int a;
-  char b;
-};
-// Unions should be passed as byval structs
-// CHECK-LABEL: define void @f7(%union.simple_union* byval(%union.simple_union) align 4 %s)
-void f7(union simple_union s) {}
-
-typedef struct {
-  int b4 : 4;
-  int b3 : 3;
-  int b8 : 8;
-} bitfield1;
-// Bitfields should be passed as byval structs
-// CHECK-LABEL: define void @f8(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1)
-void f8(bitfield1 bf1) {}

clang/test/CodeGen/le32-libcall-pow.c

-// RUN: %clang_cc1 -fno-math-builtin -fmath-errno -emit-llvm -o - %s -triple le32-unknown-nacl | FileCheck %s
-// RUN: %clang_cc1 -fno-math-builtin -emit-llvm -o - %s -triple le32-unknown-nacl | FileCheck %s
-
-// le32 (PNaCl) never generates intrinsics for pow calls, with or without
-// errno, when the -fno-math-builtin flag is passed to -cc1. A separate test
-// makes sure this flag is indeed passed for le32.
-
-float powf(float, float);
-double pow(double, double);
-long double powl(long double, long double);
-
-// CHECK-LABEL: define void @test_pow
-void test_pow(float a0, double a1, long double a2) {
-  // CHECK: call float @powf
-  float l0 = powf(a0, a0);
-
-  // CHECK: call double @pow
-  double l1 = pow(a1, a1);
-
-  // CHECK: call double @powl
-  long double l2 = powl(a2, a2);
-}
-
-// CHECK: declare float @powf(float, float)
-// CHECK: declare double @pow(double, double)
-// CHECK: declare double @powl(double, double)
-

clang/test/CodeGen/le32-regparm.c

-// RUN: %clang_cc1 -triple le32-unknown-nacl %s -fsyntax-only -verify
-// RUN: %clang_cc1 -triple aarch64 %s -fsyntax-only -verify
-
-void __attribute__((regparm(2))) fc_f1(int i, int j, int k) {} // expected-error{{'regparm' is not valid on this platform}}
-

clang/test/CodeGen/le32-vaarg.c

-// RUN: %clang_cc1 -triple le32-unknown-nacl -emit-llvm -o - %s | FileCheck %s
-#include <stdarg.h>
-
-int get_int(va_list *args) {
-  return va_arg(*args, int);
-}
-// CHECK: define i32 @get_int
-// CHECK: [[RESULT:%[a-z_0-9]+]] = va_arg {{.*}}, i32{{$}}
-// CHECK: store i32 [[RESULT]], i32* [[LOC:%[a-z_0-9]+]]
-// CHECK: [[RESULT2:%[a-z_0-9]+]] = load i32, i32* [[LOC]]
-// CHECK: ret i32 [[RESULT2]]
-
-struct Foo {
-  int x;
-};
-
-struct Foo dest;
-
-void get_struct(va_list *args) {
-  dest = va_arg(*args, struct Foo);
-}
-// CHECK: define void @get_struct
-// CHECK: [[RESULT:%[a-z_0-9]+]] = va_arg {{.*}}, %struct.Foo{{$}}
-// CHECK: store %struct.Foo [[RESULT]], %struct.Foo* [[LOC:%[a-z_0-9]+]]
-// CHECK: [[LOC2:%[a-z_0-9]+]] = bitcast {{.*}} [[LOC]] to i8*
-// CHECK: call void @llvm.memcpy{{.*}}@dest{{.*}}, i8* align {{[0-9]+}} [[LOC2]]
-
-void skip_struct(va_list *args) {
-  va_arg(*args, struct Foo);
-}
-// CHECK: define void @skip_struct
-// CHECK: va_arg {{.*}}, %struct.Foo{{$}}

clang/test/CodeGen/long_double_fp128.cpp

 // RUN: %clang_cc1 -triple x86_64-linux-android -emit-llvm -o - %s \
 // RUN:    | FileCheck %s --check-prefix=A64
 // RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -o - %s \
 // RUN:    | FileCheck %s --check-prefix=G64
 // RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm -o - %s \
 // RUN:    | FileCheck %s --check-prefix=P64
 // RUN: %clang_cc1 -triple i686-linux-android -emit-llvm -o - %s \
 // RUN:    | FileCheck %s --check-prefix=A32
 // RUN: %clang_cc1 -triple i686-linux-gnu -emit-llvm -o - %s \
 // RUN:    | FileCheck %s --check-prefix=G32
 // RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm -o - %s \
 // RUN:    | FileCheck %s --check-prefix=P32
-// RUN: %clang_cc1 -triple x86_64-nacl -emit-llvm -o - %s \
-// RUN:    | FileCheck %s --check-prefix=N64
 
 // Check mangled name of long double.
 // Android's gcc and llvm use fp128 for long double.
-// NaCl uses double format for long double, but still has separate overloads.
 void test(long, float, double, long double, long double _Complex) { }
 // A64:  define void @_Z4testlfdgCg(i64 %0, float %1, double %2, fp128 %3, { fp128, fp128 }*
 // G64:  define void @_Z4testlfdeCe(i64 %0, float %1, double %2, x86_fp80 %3, { x86_fp80, x86_fp80 }*
 // P64:  define void @_Z4testlfdgCg(i64 %0, float %1, double %2, ppc_fp128 %3, ppc_fp128 {{.*}}, ppc_fp128
 // A32:  define void @_Z4testlfdeCe(i32 %0, float %1, double %2, double %3, { double, double }*
 // G32:  define void @_Z4testlfdeCe(i32 %0, float %1, double %2, x86_fp80 %3, { x86_fp80, x86_fp80 }*
 // P32:  define void @_Z4testlfdgCg(i32 %0, float %1, double %2, ppc_fp128 %3, { ppc_fp128, ppc_fp128 }*
 // N64: define void @_Z4testlfdeCe(i32 %0, float %1, double %2, double %3, double {{.*}}, double

clang/test/CodeGen/malign-double-x86-nacl.c

-// RUN: %clang_cc1 %s -emit-llvm -o - -triple=i686-unknown-nacl | FileCheck %s
-// Check that i686-nacl essentially has -malign-double, which aligns
-// double, long double, and long long to 64-bits.
-
-int checksize[sizeof(long double) == 8 ? 1 : -1];
-int checkalign[__alignof(long double) == 8 ? 1 : -1];
-
-// CHECK-LABEL: define void @s1(double %a)
-void s1(long double a) {}
-
-struct st_ld {
-  char c;
-  long double ld;
-};
-int checksize2[sizeof(struct st_ld) == 16 ? 1 : -1];
-int checkalign2[__alignof(struct st_ld) == 8 ? 1 : -1];
-
-int checksize3[sizeof(double) == 8 ? 1 : -1];
-int checkalign3[__alignof(double) == 8 ? 1 : -1];
-
-// CHECK-LABEL: define void @s2(double %a)
-void s2(double a) {}
-
-struct st_d {
-  char c;
-  double d;
-};
-int checksize4[sizeof(struct st_d) == 16 ? 1 : -1];
-int checkalign4[__alignof(struct st_d) == 8 ? 1 : -1];
-
-
-int checksize5[sizeof(long long) == 8 ? 1 : -1];
-int checkalign5[__alignof(long long) == 8 ? 1 : -1];
-
-// CHECK-LABEL: define void @s3(i64 %a)
-void s3(long long a) {}
-
-struct st_ll {
-  char c;
-  long long ll;
-};
-int checksize6[sizeof(struct st_ll) == 16 ? 1 : -1];
-int checkalign6[__alignof(struct st_ll) == 8 ? 1 : -1];

clang/test/CodeGen/pr18235.c

-// RUN: not %clang_cc1 -triple le32-unknown-nacl %s -S -o - 2>&1 | FileCheck %s
-
-// CHECK: error: unable to create target: 'No available targets are compatible with triple "le32-unknown-nacl"'

clang/test/CodeGen/target-data.c

 // RUN: %clang_cc1 -triple mipsisa64r6-linux-gnuabin32 -o - -emit-llvm %s \
 // RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
 // MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
 
 // RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=PS3
 // PS3: target datalayout = "E-m:e-p:32:32-i64:64-n32:64"
 
-// RUN: %clang_cc1 -triple i686-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=I686-NACL
-// I686-NACL: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-n8:16:32-S128"
-
-// RUN: %clang_cc1 -triple x86_64-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=X86_64-NACL
-// X86_64-NACL: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-n8:16:32:64-S128"
-
-// RUN: %clang_cc1 -triple arm-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=ARM-NACL
-// ARM-NACL: target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128"
-
-// RUN: %clang_cc1 -triple mipsel-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=MIPS-NACL
-// MIPS-NACL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
-
-// RUN: %clang_cc1 -triple le32-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=LE32-NACL
-// LE32-NACL: target datalayout = "e-p:32:32-i64:64"
-
 // RUN: %clang_cc1 -triple wasm32-unknown-unknown -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=WEBASSEMBLY32
 // WEBASSEMBLY32: target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 
 // RUN: %clang_cc1 -triple wasm64-unknown-unknown -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=WEBASSEMBLY64
 // WEBASSEMBLY64: target datalayout = "e-m:e-p:64:64-i64:64-n32:64-S128"
 

clang/test/CodeGen/x86_64-arguments-nacl.c

-// RUN: %clang_cc1 -triple x86_64-unknown-nacl -emit-llvm -o - %s| FileCheck %s
-#include <stdarg.h>
-// Test for x86-64 structure representation (instead of pnacl representation),
-// in particular for unions. Also crib a few tests from x86 Linux.
-
-union PP_VarValue {
-  int as_int;
-  double as_double;
-  long long as_i64;
-};
-
-struct PP_Var {
-  int type;
-  int padding;
-  union PP_VarValue value;
-};
-
-// CHECK: define { i64, i64 } @f0()
-struct PP_Var f0() {
-  struct PP_Var result = { 0, 0, 0 };
-  return result;
-}
-
-// CHECK-LABEL: define void @f1(i64 %p1.coerce0, i64 %p1.coerce1)
-void f1(struct PP_Var p1) { while(1) {} }
-
-// long doubles are 64 bits on NaCl
-// CHECK-LABEL: define double @f5()
-long double f5(void) {
-  return 0;
-}
-
-// CHECK-LABEL: define void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
-void f6(char a0, short a1, int a2, long long a3, void *a4) {
-}
-
-// CHECK-LABEL: define i64 @f8_1()
-// CHECK-LABEL: define void @f8_2(i64 %a0.coerce)
-union u8 {
-  long double a;
-  int b;
-};
-union u8 f8_1() { while (1) {} }
-void f8_2(union u8 a0) {}
-
-// CHECK-LABEL: define i64 @f9()
-struct s9 { int a; int b; int : 0; } f9(void) { while (1) {} }
-
-// CHECK-LABEL: define void @f10(i64 %a0.coerce)
-struct s10 { int a; int b; int : 0; };
-void f10(struct s10 a0) {}
-
-// CHECK-LABEL: define double @f11()
-union { long double a; float b; } f11() { while (1) {} }
-
-// CHECK-LABEL: define i32 @f12_0()
-// CHECK-LABEL: define void @f12_1(i32 %a0.coerce)
-struct s12 { int a __attribute__((aligned(16))); };
-struct s12 f12_0(void) { while (1) {} }
-void f12_1(struct s12 a0) {}
-
-// Check that sret parameter is accounted for when checking available integer
-// registers.
-// CHECK: define void @f13(%struct.s13_0* noalias sret align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)
-
-struct s13_0 { long long f0[3]; };
-struct s13_1 { long long f0[2]; };
-struct s13_0 f13(int a, int b, int c, int d,
-                 struct s13_1 e, int f) { while (1) {} }
-
-// CHECK-LABEL: define void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
-struct __attribute__((aligned(32))) s20 {
-  int x;
-  int y;
-};
-void f20(struct s20 x) {}
-
-
-// CHECK: declare void @func(i64)
-typedef struct _str {
-  union {
-    long double a;
-    long c;
-  };
-} str;
-
-void func(str s);
-str ss;
-void f9122143()
-{
-  func(ss);
-}

clang/test/CodeGen/x86_64-longdouble.c

 // RUN: %clang_cc1 -triple x86_64-linux-android -emit-llvm -O -o - %s \
 // RUN:    | FileCheck %s --check-prefix=ANDROID --check-prefix=CHECK
 // RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -O -o - %s \
 // RUN:    | FileCheck %s --check-prefix=GNU --check-prefix=CHECK
 // RUN: %clang_cc1 -triple x86_64 -emit-llvm -O -o - %s \
 // RUN:    | FileCheck %s --check-prefix=GNU --check-prefix=CHECK
-// NaCl is an example of a target for which long double is the same as double.
-// RUN: %clang_cc1 -triple x86_64-nacl -emit-llvm -O -o - %s \
-// RUN:    | FileCheck %s --check-prefix=NACL --check-prefix=CHECK
 
 // Android uses fp128 for long double but other x86_64 targets use x86_fp80.
 
 long double dataLD = 1.0L;
 // ANDROID: @dataLD = local_unnamed_addr global fp128 0xL00000000000000003FFF000000000000, align 16
 // GNU: @dataLD = local_unnamed_addr global x86_fp80 0xK3FFF8000000000000000, align 16
 
 long double _Complex dataLDC = {1.0L, 1.0L};

clang/test/CodeGenCXX/member-function-pointers.cpp

 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-unknown | FileCheck -check-prefix CODE-LP64 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=i386-unknown-unknown | FileCheck -check-prefix CODE-LP32 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-unknown | FileCheck -check-prefix GLOBAL-LP64 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=i386-unknown-unknown | FileCheck -check-prefix GLOBAL-LP32 %s
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=armv7-unknown-unknown | FileCheck -check-prefix GLOBAL-ARM %s
 
-// PNaCl uses the same representation of method pointers as ARM.
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple=le32-unknown-nacl | FileCheck -check-prefix GLOBAL-ARM %s
 // MIPS uses the same representation of method pointers as ARM.
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=mips-unknown-linux-gnu | FileCheck -check-prefix GLOBAL-ARM %s
 // WebAssembly uses the same representation of method pointers as ARM.
 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=wasm32-unknown-unknown | FileCheck -check-prefix GLOBAL-ARM %s
 
 struct A { int a; void f(); virtual void vf1(); virtual void vf2(); };
 struct B { int b; virtual void g(); };
 struct C : B, A { };

clang/test/CodeGenCXX/static-init-pnacl.cpp

-// RUN: %clang_cc1 -emit-llvm -triple=le32-unknown-nacl -o - %s | FileCheck %s
-
-int f();
-
-// Test that PNaCl uses the Itanium/x86 ABI in which the static
-// variable's guard variable is tested via "load i8 and compare with
-// zero" rather than the ARM ABI which uses "load i32 and test the
-// bottom bit".
-void g() {
-  static int a = f();
-}
-// CHECK: [[LOAD:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ1gvE1a to i8*) acquire
-// CHECK-NEXT: [[GUARD:%.*]] = icmp eq i8 [[LOAD]], 0
-// CHECK-NEXT: br i1 [[GUARD]]

clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp

-// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-nacl -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -std=c++11 -triple=x86_64-unknown-linux-gnux32 -emit-llvm -o - %s | FileCheck %s
-
-struct test_struct {};
-typedef int test_struct::* test_struct_mdp;
-typedef int (test_struct::*test_struct_mfp)();
-
-// CHECK-LABEL: define i32 @{{.*}}f_mdp{{.*}}(i32 %a)
-test_struct_mdp f_mdp(test_struct_mdp a) { return a; }
-
-// CHECK-LABEL: define {{.*}} @{{.*}}f_mfp{{.*}}(i64 %a.coerce)
-test_struct_mfp f_mfp(test_struct_mfp a) { return a; }
-
-// A struct with <= 12 bytes before a member data pointer should still
-// be allowed in registers, since the member data pointer is only 4 bytes.
-// CHECK-LABEL: define void @{{.*}}f_struct_with_mdp{{.*}}(i64 %a.coerce0, i64 %a.coerce1)
-struct struct_with_mdp { char *a; char *b; char *c; test_struct_mdp d; };
-void f_struct_with_mdp(struct_with_mdp a) { (void)a; }
-
-struct struct_with_mdp_too_much {
-  char *a; char *b; char *c; char *d; test_struct_mdp e;
-};
-// CHECK-LABEL: define void @{{.*}}f_struct_with_mdp_too_much{{.*}}({{.*}} byval({{.*}} {{.*}} %a)
-void f_struct_with_mdp_too_much(struct_with_mdp_too_much a) {
-  (void)a;
-}
-
-// A struct with <= 8 bytes before a member function pointer should still
-// be allowed in registers, since the member function pointer is only 8 bytes.
-// CHECK-LABEL: define void @{{.*}}f_struct_with_mfp_0{{.*}}(i64 %a.coerce0, i32 %a.coerce1)
-struct struct_with_mfp_0 { char *a; test_struct_mfp b; };
-void f_struct_with_mfp_0(struct_with_mfp_0 a) { (void)a; }
-
-// CHECK-LABEL: define void @{{.*}}f_struct_with_mfp_1{{.*}}(i64 %a.coerce0, i64 %a.coerce1)
-struct struct_with_mfp_1 { char *a; char *b; test_struct_mfp c; };
-void f_struct_with_mfp_1(struct_with_mfp_1 a) { (void)a; }
-
-// CHECK-LABEL: define void @{{.*}}f_struct_with_mfp_too_much{{.*}}({{.*}} byval({{.*}}) {{.*}} %a, i32 %x)
-struct struct_with_mfp_too_much {
-  char *a; char *b; char *c; test_struct_mfp d;
-};
-void f_struct_with_mfp_too_much(struct_with_mfp_too_much a, int x) {
-  (void)a;
-}
-
-/* Struct containing an empty struct */
-typedef struct { int* a; test_struct x; double *b; } struct_with_empty;
-
-// CHECK-LABEL: define void @{{.*}}f_pass_struct_with_empty{{.*}}(i64 %x{{.*}}, double* %x
-void f_pass_struct_with_empty(struct_with_empty x) {
-  (void) x;
-}
-
-// CHECK-LABEL: define { i64, double* } @{{.*}}f_return_struct_with_empty
-struct_with_empty f_return_struct_with_empty() {
-  return {0, {}, 0};
-}

clang/test/Driver/arm-alignment.c

 // RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
 
 // RUN: %clang -target armv6-netbsd-eabi -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
 
 // RUN: %clang -target armv7-unknown-linux -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
 
-// RUN: %clang -target armv7-unknown-nacl-gnueabihf -### %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
-
 // RUN: %clang -target aarch64-none-gnueabi -munaligned-access -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-UNALIGNED-AARCH64 < %t %s
 
 // RUN: %clang -target aarch64-none-gnueabi -mstrict-align -munaligned-access -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-UNALIGNED-AARCH64 < %t %s
 
 // RUN: %clang -target aarch64-none-gnueabi -mno-unaligned-access -munaligned-access -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-UNALIGNED-AARCH64 < %t %s

 // RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
 
 // RUN: %clang -target armv5t-netbsd-eabi -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
 
 // RUN: %clang -target armv6-unknown-linux -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
 
-// RUN: %clang -target armv6-unknown-nacl-gnueabihf -### %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
-
 // RUN: %clang -target armv6m-apple-darwin -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
 
 // RUN: %clang -target armv6m-netbsd-eabi -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
 
 // RUN: %clang -target aarch64-none-gnueabi -mno-unaligned-access -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ALIGNED-AARCH64 < %t %s

clang/test/Driver/le32-toolchain.c

-// RUN: %clang -### -target le32-unknown-nacl %s 2>&1 | FileCheck -check-prefix=CHECK-DEFAULT %s
-
-// CHECK-DEFAULT: "-cc1" {{.*}} "-fno-math-builtin"
-

clang/test/Driver/le32-unknown-nacl.cpp

-// RUN: %clang -target le32-unknown-nacl -### %s -emit-llvm-only -c 2>&1 | FileCheck %s -check-prefix=ECHO
-// RUN: %clang -target le32-unknown-nacl %s -emit-llvm -S -c -o - | FileCheck %s
-// RUN: %clang -target le32-unknown-nacl -fexperimental-new-pass-manager %s -emit-llvm -S -c -o - | FileCheck %s
-// RUN: %clang -target le32-unknown-nacl %s -emit-llvm -S -c -pthread -o - | FileCheck %s -check-prefix=THREADS
-
-// ECHO: {{.*}} "-cc1" {{.*}}le32-unknown-nacl.c
-
-typedef __builtin_va_list va_list;
-typedef __SIZE_TYPE__ size_t;
-typedef __PTRDIFF_TYPE__ ptrdiff_t;
-
-extern "C" {
-
-// CHECK: @align_c = dso_local global i32 1
-int align_c = __alignof(char);
-
-// CHECK: @align_s = dso_local global i32 2
-int align_s = __alignof(short);
-
-// CHECK: @align_i = dso_local global i32 4
-int align_i = __alignof(int);
-
-// CHECK: @align_l = dso_local global i32 4
-int align_l = __alignof(long);
-
-// CHECK: @align_ll = dso_local global i32 8
-int align_ll = __alignof(long long);
-
-// CHECK: @align_p = dso_local global i32 4
-int align_p = __alignof(void*);
-
-// CHECK: @align_f = dso_local global i32 4
-int align_f = __alignof(float);
-
-// CHECK: @align_d = dso_local global i32 8
-int align_d = __alignof(double);
-
-// CHECK: @align_ld = dso_local global i32 8
-int align_ld = __alignof(long double);
-
-// CHECK: @align_vl = dso_local global i32 4
-int align_vl = __alignof(va_list);
-
-// CHECK: __LITTLE_ENDIAN__defined
-#ifdef __LITTLE_ENDIAN__
-void __LITTLE_ENDIAN__defined() {}
-#endif
-
-// CHECK: __native_client__defined
-#ifdef __native_client__
-void __native_client__defined() {}
-#endif
-
-// CHECK: __le32__defined
-#ifdef __le32__
-void __le32__defined() {}
-#endif
-
-// CHECK: __pnacl__defined
-#ifdef __pnacl__
-void __pnacl__defined() {}
-#endif
-
-// CHECK: unixdefined
-#ifdef unix
-void unixdefined() {}
-#endif
-
-// CHECK: __ELF__defined
-#ifdef __ELF__
-void __ELF__defined() {}
-#endif
-
-// CHECK: _GNU_SOURCEdefined
-#ifdef _GNU_SOURCE
-void _GNU_SOURCEdefined() {}
-#endif
-
-// THREADS: _REENTRANTdefined
-// CHECK: _REENTRANTundefined
-#ifdef _REENTRANT
-void _REENTRANTdefined() {}
-#else
-void _REENTRANTundefined() {}
-#endif
-
-// Check types
-
-// CHECK: signext i8 @check_char()
-char check_char() { return 0; }
-
-// CHECK: signext i16 @check_short()
-short check_short() { return 0; }
-
-// CHECK: i32 @check_int()
-int check_int() { return 0; }
-
-// CHECK: i32 @check_long()
-long check_long() { return 0; }
-
-// CHECK: i64 @check_longlong()
-long long check_longlong() { return 0; }
-
-// CHECK: zeroext i8 @check_uchar()
-unsigned char check_uchar() { return 0; }
-
-// CHECK: zeroext i16 @check_ushort()
-unsigned short check_ushort() { return 0; }
-
-// CHECK: i32 @check_uint()
-unsigned int check_uint() { return 0; }
-
-// CHECK: i32 @check_ulong()
-unsigned long check_ulong() { return 0; }
-
-// CHECK: i64 @check_ulonglong()
-unsigned long long check_ulonglong() { return 0; }
-
-// CHECK: i32 @check_size_t()
-size_t check_size_t() { return 0; }
-
-// CHECK: float @check_float()
-float check_float() { return 0; }
-
-// CHECK: double @check_double()
-double check_double() { return 0; }
-
-// CHECK: double @check_longdouble()
-long double check_longdouble() { return 0; }
-
-}
-
-template<int> void Switch();
-template<> void Switch<4>();
-template<> void Switch<8>();
-template<> void Switch<16>();
-
-void check_pointer_size() {
-  // CHECK: SwitchILi4
-  Switch<sizeof(void*)>();
-
-  // CHECK: SwitchILi8
-  Switch<sizeof(long long)>();
-
-  // CHECK: SwitchILi16
-  Switch<sizeof(va_list)>();
-}

clang/test/Driver/le64-unknown-unknown.cpp

-// RUN: %clang -target le64-unknown-unknown -### %s -emit-llvm-only -c 2>&1 | FileCheck %s -check-prefix=ECHO
-// RUN: %clang -target le64-unknown-unknown %s -emit-llvm -S -c -o - | FileCheck %s
-
-// ECHO: {{.*}} "-cc1" {{.*}}le64-unknown-unknown.c
-
-typedef __builtin_va_list va_list;
-typedef __SIZE_TYPE__ size_t;
-typedef __PTRDIFF_TYPE__ ptrdiff_t;
-
-extern "C" {
-
-// CHECK: @align_c = dso_local global i32 1
-int align_c = __alignof(char);
-
-// CHECK: @align_s = dso_local global i32 2
-int align_s = __alignof(short);
-
-// CHECK: @align_i = dso_local global i32 4
-int align_i = __alignof(int);
-
-// CHECK: @align_l = dso_local global i32 8
-int align_l = __alignof(long);
-
-// CHECK: @align_ll = dso_local global i32 8
-int align_ll = __alignof(long long);
-
-// CHECK: @align_p = dso_local global i32 8
-int align_p = __alignof(void*);
-
-// CHECK: @align_f = dso_local global i32 4
-int align_f = __alignof(float);
-
-// CHECK: @align_d = dso_local global i32 8
-int align_d = __alignof(double);
-
-// CHECK: @align_ld = dso_local global i32 8
-int align_ld = __alignof(long double);
-
-// CHECK: @align_vl = dso_local global i32 4
-int align_vl = __alignof(va_list);
-
-// CHECK: __LITTLE_ENDIAN__defined
-#ifdef __LITTLE_ENDIAN__
-void __LITTLE_ENDIAN__defined() {}
-#endif
-
-// CHECK: __le64defined
-#ifdef __le64
-void __le64defined() {}
-#endif
-
-// CHECK: __le64__defined
-#ifdef __le64__
-void __le64__defined() {}
-#endif
-
-// CHECK: unixdefined
-#ifdef unix
-void unixdefined() {}
-#endif
-
-// CHECK: __unixdefined
-#ifdef __unix
-void __unixdefined() {}
-#endif
-
-// CHECK: __unix__defined
-#ifdef __unix__
-void __unix__defined() {}
-#endif
-
-// CHECK: __ELF__defined
-#ifdef __ELF__
-void __ELF__defined() {}
-#endif
-
-// Check types
-
-// CHECK: signext i8 @check_char()
-char check_char() { return 0; }
-
-// CHECK: signext i16 @check_short()
-short check_short() { return 0; }
-
-// CHECK: i32 @check_int()
-int check_int() { return 0; }
-
-// CHECK: i64 @check_long()
-long check_long() { return 0; }
-
-// CHECK: i64 @check_longlong()
-long long check_longlong() { return 0; }
-
-// CHECK: zeroext i8 @check_uchar()
-unsigned char check_uchar() { return 0; }
-
-// CHECK: zeroext i16 @check_ushort()
-unsigned short check_ushort() { return 0; }
-
-// CHECK: i32 @check_uint()
-unsigned int check_uint() { return 0; }
-
-// CHECK: i64 @check_ulong()
-unsigned long check_ulong() { return 0; }
-
-// CHECK: i64 @check_ulonglong()
-unsigned long long check_ulonglong() { return 0; }
-
-// CHECK: i64 @check_size_t()
-size_t check_size_t() { return 0; }
-
-// CHECK: i64 @check_ptrdiff_t()
-ptrdiff_t check_ptrdiff_t() { return 0; }
-
-// CHECK: float @check_float()
-float check_float() { return 0; }
-
-// CHECK: double @check_double()
-double check_double() { return 0; }
-
-// CHECK: double @check_longdouble()
-long double check_longdouble() { return 0; }
-
-}
-
-template<int> void Switch();
-template<> void Switch<4>();
-template<> void Switch<8>();
-template<> void Switch<16>();
-
-void check_pointer_size() {
-  // CHECK: SwitchILi8
-  Switch<sizeof(void*)>();
-
-  // CHECK: SwitchILi16
-  Switch<sizeof(va_list)>();
-}

clang/test/Driver/mipsel-nacl-defines.cpp

-// RUN: %clang -target mipsel-unknown-nacl -### %s -emit-llvm-only -c -o %t.o 2>&1 | FileCheck %s -check-prefix=ECHO
-// RUN: %clang -target mipsel-unknown-nacl %s -emit-llvm -S -c -o - | FileCheck %s
-// RUN: %clang -target mipsel-unknown-nacl %s -emit-llvm -S -c -pthread -o - | FileCheck %s -check-prefix=THREADS
-
-// ECHO: {{.*}} "-cc1" {{.*}}mipsel-nacl-defines.c
-
-// Check platform defines
-
-// CHECK: _MIPSELdefined
-#ifdef _MIPSEL
-void _MIPSELdefined() {}
-#endif
-
-// CHECK: _mipsdefined
-#ifdef _mips
-void _mipsdefined() {}
-#endif
-
-// CHECK: __native_client__defined
-#ifdef __native_client__
-void __native_client__defined() {}
-#endif
-
-// CHECK: unixdefined
-#ifdef unix
-void unixdefined() {}
-#endif
-
-// CHECK: __ELF__defined
-#ifdef __ELF__
-void __ELF__defined() {}
-#endif
-
-// CHECK: _GNU_SOURCEdefined
-#ifdef _GNU_SOURCE
-void _GNU_SOURCEdefined() {}
-#endif
-
-// THREADS: _REENTRANTdefined
-// CHECK: _REENTRANTundefined
-#ifdef _REENTRANT
-void _REENTRANTdefined() {}
-#else
-void _REENTRANTundefined() {}
-#endif

clang/test/Driver/nacl-direct.c

-// Test clang changes for NaCl Support including:
-//    include paths, library paths, emulation, default static
-//
-// RUN: %clang -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target i686-unknown-nacl -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-I686 %s
-// CHECK-I686: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-I686-NOT: "-fno-use-init-array"
-// CHECK-I686: "-target-cpu" "pentium4"
-// CHECK-I686: "-resource-dir" "foo"
-// CHECK-I686: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-I686: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-I686: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-I686: as{{(.exe)?}}" "--32"
-// CHECK-I686: ld{{(.exe)?}}"
-// CHECK-I686: "--build-id"
-// CHECK-I686: "-m" "elf_i386_nacl"
-// CHECK-I686: "-static"
-// CHECK-I686: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}lib32"
-// CHECK-I686: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-I686: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}i686-nacl"
-// CHECK-I686-NOT: -lpthread
-//
-// RUN: %clang -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target x86_64-unknown-nacl -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-x86_64 %s
-// CHECK-x86_64: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-x86_64-NOT: "-fno-use-init-array"
-// CHECK-x86_64: "-target-cpu" "x86-64"
-// CHECK-x86_64: "-resource-dir" "foo"
-// CHECK-x86_64: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-x86_64: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-x86_64: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-x86_64: as{{(.exe)?}}" "--64"
-// CHECK-x86_64: ld{{(.exe)?}}"
-// CHECK-x86_64: "--build-id"
-// CHECK-x86_64: "-m" "elf_x86_64_nacl"
-// CHECK-x86_64: "-static"
-// CHECK-x86_64: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}lib"
-// CHECK-x86_64: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-x86_64: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}x86_64-nacl"
-// CHECK-X86_64-NOT: -lpthread
-//
-// RUN: %clang -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target armv7a-unknown-nacl-gnueabihf -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-ARM %s
-// CHECK-ARM: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-ARM-NOT: "-fno-use-init-array"
-// CHECK-ARM: "-target-cpu" "generic"
-// CHECK-ARM: "-target-abi" "aapcs-linux"
-// CHECK-ARM: "-mfloat-abi" "hard"
-// CHECK-ARM: "-resource-dir" "foo"
-// CHECK-ARM: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-ARM: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-ARM: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}include"
-// CHECK-ARM: as{{(.exe)?}}"
-// CHECK-ARM: "-mfloat-abi=hard"
-// CHECK-ARM: ld{{(.exe)?}}"
-// CHECK-ARM: "--build-id"
-// CHECK-ARM: "-m" "armelf_nacl"
-// CHECK-ARM: "-static"
-// CHECK-ARM: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}lib"
-// CHECK-ARM: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-ARM: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}arm-nacl"
-// CHECK-ARM-NOT: -lpthread
-//
-// RUN: %clang -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target mipsel-unknown-nacl -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-MIPS %s
-// CHECK-MIPS: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-MIPS-NOT: "-fno-use-init-array"
-// CHECK-MIPS: "-target-cpu" "mips32r2"
-// CHECK-MIPS: "-target-abi" "o32"
-// CHECK-MIPS: "-mfloat-abi" "hard"
-// CHECK-MIPS: "-resource-dir" "foo"
-// CHECK-MIPS: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-MIPS: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-MIPS: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}include"
-// CHECK-MIPS-NOT: as{{(.exe)?}}"
-// CHECK-MIPS: ld{{(.exe)?}}"
-// CHECK-MIPS: "--build-id"
-// CHECK-MIPS: "-m" "mipselelf_nacl"
-// CHECK-MIPS: "-static"
-// CHECK-MIPS: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}lib"
-// CHECK-MIPS: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-MIPS: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}mipsel-nacl"
-// CHECK-MIPS: "-lpnacl_legacy"
-// CHECK-MIPS-NOT: "-lpthread"
-
-// Check that even when the target arch is just "arm" (as will be the case when
-// it is inferred from the binary name) that we get the right ABI flags
-// RUN: %clang -no-canonical-prefixes -### -o %t.o %s 2>&1 \
-// RUN:     -target arm-nacl \
-// RUN:   | FileCheck --check-prefix=CHECK-ARM-NOV7 %s
-// CHECK-ARM-NOV7: "-triple" "armv7-unknown-nacl-gnueabihf"
-// CHECK-ARM-NOV7: "-target-abi" "aapcs-linux"
-// CHECK-ARM-NOV7: "-mfloat-abi" "hard"
-// CHECK-ARM-NOV7: as{{(.exe)?}}"
-// CHECK-ARM-NOV7: "-mfloat-abi=hard"
-
-// Test clang c++ include dirs and link line when using clang++
-
-// RUN: %clangxx -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target armv7a-unknown-nacl-gnueabihf -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-ARM-CXX %s
-// CHECK-ARM-CXX: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-ARM-CXX: "-resource-dir" "foo"
-// CHECK-ARM-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-ARM-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-ARM-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-ARM-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}include"
-// CHECK-ARM-CXX: "-lpthread"
-
-// RUN: %clangxx -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target i686-unknown-nacl -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-I686-CXX %s
-// CHECK-I686-CXX: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-I686-CXX: "-resource-dir" "foo"
-// CHECK-I686-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-I686-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-I686-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-I686-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-I686-CXX: "-lpthread"
-
-// RUN: %clangxx -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target x86_64-unknown-nacl -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-x86_64-CXX %s
-// CHECK-x86_64-CXX: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-x86_64-CXX: "-resource-dir" "foo"
-// CHECK-x86_64-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-x86_64-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-x86_64-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-x86_64-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-x86_64-CXX: "-lpthread"
-
-// RUN: %clangxx -no-canonical-prefixes -### -o %t.o %s \
-// RUN:     -target mipsel-unknown-nacl -resource-dir foo 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-MIPS-CXX %s
-// CHECK-MIPS-CXX: {{.*}}clang{{.*}}" "-cc1"
-// CHECK-MIPS-CXX: "-resource-dir" "foo"
-// CHECK-MIPS-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-MIPS-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-MIPS-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-MIPS-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}include"
-// CHECK-MIPS-CXX: "-lnacl"
-// CHECK-MIPS-CXX: "-lpthread"

clang/test/Driver/unsupported-target-arch.c

 //
 // RUN: not %clang --target=noarch-unknown-freebsd -o %t.o %s 2> %t.err
 // RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-NOARCH-FREEBSD %s
 // CHECK-NOARCH-FREEBSD: error: unknown target triple 'noarch-unknown-freebsd', please use -triple or -arch
 //
 // RUN: not %clang --target=noarch-unknown-netbsd -o %t.o %s 2> %t.err
 // RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-NOARCH-NETBSD %s
 // CHECK-NOARCH-NETBSD: error: unknown target triple 'noarch-unknown-netbsd', please use -triple or -arch
-//
-// RUN: not %clang --target=noarch-unknown-nacl -o %t.o %s 2> %t.err
-// RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-NOARCH-NACL %s
-// CHECK-NOARCH-NACL:  error: the target architecture 'noarch' is not supported by the target 'Native Client'

clang/test/Driver/x86_64-nacl-defines.cpp

-// RUN: %clang -target x86_64-unknown-nacl -### %s -emit-llvm-only -c -o %t.o 2>&1 | FileCheck %s -check-prefix=ECHO
-// RUN: %clang -target x86_64-unknown-nacl %s -emit-llvm -S -c -o - | FileCheck %s
-// RUN: %clang -target x86_64-unknown-nacl %s -emit-llvm -S -c -pthread -o - | FileCheck %s -check-prefix=THREADS
-
-// ECHO: {{.*}} "-cc1" {{.*}}x86_64-nacl-defines.c
-
-// Check platform defines
-
-// CHECK: __LITTLE_ENDIAN__defined
-#ifdef __LITTLE_ENDIAN__
-void __LITTLE_ENDIAN__defined() {}
-#endif
-
-// CHECK: __native_client__defined
-#ifdef __native_client__
-void __native_client__defined() {}
-#endif
-
-// CHECK: __x86_64__defined
-#ifdef __x86_64__
-void __x86_64__defined() {}
-#endif
-
-// CHECK: unixdefined
-#ifdef unix
-void unixdefined() {}
-#endif
-
-// CHECK: __ELF__defined
-#ifdef __ELF__
-void __ELF__defined() {}
-#endif
-
-// CHECK: _GNU_SOURCEdefined
-#ifdef _GNU_SOURCE
-void _GNU_SOURCEdefined() {}
-#endif
-
-// THREADS: _REENTRANTdefined
-// CHECK: _REENTRANTundefined
-#ifdef _REENTRANT
-void _REENTRANTdefined() {}
-#else
-void _REENTRANTundefined() {}
-#endif

clang/test/Frontend/x86_64-nacl-types.cpp

-// RUN: %clang_cc1 -triple x86_64-unknown-nacl -std=c++11 -verify %s
-// expected-no-diagnostics
-
-#include <stddef.h>
-#include <stdarg.h>
-
-static_assert(alignof(char) == 1, "alignof char is wrong");
-
-static_assert(sizeof(short) == 2, "sizeof short is wrong");
-static_assert(alignof(short) == 2, "alignof short is wrong");
-
-static_assert(sizeof(int) == 4, "sizeof int is wrong");
-static_assert(alignof(int) == 4, "alignof int is wrong");
-
-static_assert(sizeof(long) == 4, "sizeof long is wrong");
-static_assert(alignof(long) == 4, "alignof long is wrong");
-
-static_assert(sizeof(long long) == 8, "sizeof long long is wrong wrong");
-static_assert(alignof(long long) == 8, "alignof long long is wrong wrong");
-
-static_assert(sizeof(void*) == 4, "sizeof void * is wrong");
-static_assert(alignof(void*) == 4, "alignof void * is wrong");
-
-static_assert(sizeof(float) == 4, "sizeof float is wrong");
-static_assert(alignof(float) == 4, "alignof float is wrong");
-
-static_assert(sizeof(double) == 8, "sizeof double is wrong");
-static_assert(alignof(double) == 8, "alignof double is wrong");
-
-static_assert(sizeof(long double) == 8, "sizeof long double is wrong");
-static_assert(alignof(long double) == 8, "alignof long double is wrong");
-
-static_assert(sizeof(va_list) == 16, "sizeof va_list is wrong");
-static_assert(alignof(va_list) == 4, "alignof va_list is wrong");
-
-static_assert(sizeof(size_t) == 4, "sizeof size_t is wrong");
-static_assert(alignof(size_t) == 4, "alignof size_t is wrong");

clang/test/Headers/stdarg.cpp

 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple aarch64-linux -o - | FileCheck %s --check-prefix=AARCH64-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple aarch64-linux -o - | FileCheck %s --check-prefix=AARCH64-CXX
 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple x86_64-linux -o - | FileCheck %s --check-prefix=X86_64-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple x86_64-linux -o - | FileCheck %s --check-prefix=X86_64-CXX
 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple ppc64-linux -o - | FileCheck %s --check-prefix=PPC64-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple ppc64-linux -o - | FileCheck %s --check-prefix=PPC64-CXX
 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple armv7-apple-darwin9 -target-abi aapcs -o - | FileCheck %s --check-prefix=AAPCS-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple armv7-apple-darwin9 -target-abi aapcs -o - | FileCheck %s --check-prefix=AAPCS-CXX
 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple s390x-linux -o - | FileCheck %s --check-prefix=SYSTEMZ-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple s390x-linux -o - | FileCheck %s --check-prefix=SYSTEMZ-CXX
-// RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple le32-nacl -o - | FileCheck %s --check-prefix=PNACL-C
-// RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple le32-nacl -o - | FileCheck %s --check-prefix=PNACL-CXX
 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple i686-linux -o - | FileCheck %s --check-prefix=CHARPTR-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple i686-linux -o - | FileCheck %s --check-prefix=CHARPTR-CXX
 // RUN: %clang_cc1 -emit-llvm -std=c99 -x c %s -triple xcore -o - | FileCheck %s --check-prefix=VOIDPTR-C
 // RUN: %clang_cc1 -emit-llvm -std=c++17 -x c++ %s -triple xcore -o - | FileCheck %s --check-prefix=VOIDPTR-CXX
 
 #include <stdarg.h>
 
 // AARCH64-C: define {{.*}} @f(i32 %n, %struct.__va_list* %list)

llvm/include/llvm/ADT/Triple.h

enum OSType {
     MacOSX,
     NetBSD,
     OpenBSD,
     Solaris,
     Win32,
     Haiku,
     Minix,
     RTEMS,
-    NaCl,       // Native Client
     CNK,        // BG/P Compute-Node Kernel
     AIX,
     CUDA,       // NVIDIA CUDA
     NVCL,       // NVIDIA OpenCL
     AMDHSA,     // AMD HSA Runtime
     PS4,
     ELFIAMCU,
     TvOS,       // Apple tvOS
public:
   }
 
   /// Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
   bool isOSMSVCRT() const {
     return isWindowsMSVCEnvironment() || isWindowsGNUEnvironment() ||
            isWindowsItaniumEnvironment();
   }
 
-  /// Tests whether the OS is NaCl (Native Client)
-  bool isOSNaCl() const {
-    return getOS() == Triple::NaCl;
-  }
-
   /// Tests whether the OS is Linux.
   bool isOSLinux() const {
     return getOS() == Triple::Linux;
   }
 
   /// Tests whether the OS is kFreeBSD.
   bool isOSKFreeBSD() const {
     return getOS() == Triple::KFreeBSD;

llvm/lib/Support/Triple.cpp

StringRef Triple::getOSTypeName(OSType Kind) {
   case IOS: return "ios";
   case KFreeBSD: return "kfreebsd";
   case Linux: return "linux";
   case Lv2: return "lv2";
   case MacOSX: return "macosx";
   case Mesa3D: return "mesa3d";
   case Minix: return "minix";
   case NVCL: return "nvcl";
-  case NaCl: return "nacl";
   case NetBSD: return "netbsd";
   case OpenBSD: return "openbsd";
   case PS4: return "ps4";
   case RTEMS: return "rtems";
   case Solaris: return "solaris";
   case TvOS: return "tvos";
   case WASI: return "wasi";
   case WatchOS: return "watchos";
return StringSwitch<Triple::OSType>(OSName)
     .StartsWith("netbsd", Triple::NetBSD)
     .StartsWith("openbsd", Triple::OpenBSD)
     .StartsWith("solaris", Triple::Solaris)
     .StartsWith("win32", Triple::Win32)
     .StartsWith("windows", Triple::Win32)
     .StartsWith("haiku", Triple::Haiku)
     .StartsWith("minix", Triple::Minix)
     .StartsWith("rtems", Triple::RTEMS)
-    .StartsWith("nacl", Triple::NaCl)
     .StartsWith("cnk", Triple::CNK)
     .StartsWith("aix", Triple::AIX)
     .StartsWith("cuda", Triple::CUDA)
     .StartsWith("nvcl", Triple::NVCL)
     .StartsWith("amdhsa", Triple::AMDHSA)
     .StartsWith("ps4", Triple::PS4)
     .StartsWith("elfiamcu", Triple::ELFIAMCU)
     .StartsWith("tvos", Triple::TvOS)
case llvm::Triple::NetBSD:
     case llvm::Triple::EABI:
     case llvm::Triple::EABIHF:
     case llvm::Triple::GNUEABI:
     case llvm::Triple::GNUEABIHF:
       return "arm926ej-s";
     default:
       return "strongarm";
     }
-  case llvm::Triple::NaCl:
   case llvm::Triple::OpenBSD:
     return "cortex-a8";
   default:
     switch (getEnvironment()) {
     case llvm::Triple::EABIHF:
     case llvm::Triple::GNUEABIHF:
     case llvm::Triple::MuslEABIHF:
       return "arm1176jzf-s";
     default:
       return "arm7tdmi";
     }
   }
 
   llvm_unreachable("invalid arch name");
 }

llvm/lib/Target/ARM/ARMPredicates.td

def IsMClass         : Predicate<"Subtarget->isMClass()">,
                                  AssemblerPredicate<(all_of FeatureMClass), "armv*m">;
 def IsNotMClass      : Predicate<"!Subtarget->isMClass()">,
                                  AssemblerPredicate<(all_of (not FeatureMClass)),
                                                     "!armv*m">;
 def IsARM            : Predicate<"!Subtarget->isThumb()">,
                                  AssemblerPredicate<(all_of (not ModeThumb)), "arm-mode">;
 def IsMachO          : Predicate<"Subtarget->isTargetMachO()">;
 def IsNotMachO       : Predicate<"!Subtarget->isTargetMachO()">;
-def IsNaCl           : Predicate<"Subtarget->isTargetNaCl()">;
 def IsWindows        : Predicate<"Subtarget->isTargetWindows()">;
 def IsNotWindows     : Predicate<"!Subtarget->isTargetWindows()">;
 def IsReadTPHard     : Predicate<"Subtarget->isReadTPHard()">;
 def IsReadTPSoft     : Predicate<"!Subtarget->isReadTPHard()">;
 def UseNaClTrap      : Predicate<"Subtarget->useNaClTrap()">,
                                  AssemblerPredicate<(all_of FeatureNaClTrap), "NaCl">;
 def DontUseNaClTrap  : Predicate<"!Subtarget->useNaClTrap()">;
 

llvm/lib/Target/ARM/ARMSubtarget.h

public:
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
   bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
-  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
   bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
 
   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   // ARM EABI is the bare-metal EABI described in ARM ABI documents and

llvm/lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   InstrItins = getInstrItineraryForCPU(CPUString);
 
   // FIXME: this is invalid for WindowsCE
   if (isTargetWindows())
     NoARM = true;
 
   if (isAAPCS_ABI())
     stackAlignment = Align(8);
-  if (isTargetNaCl() || isAAPCS16_ABI())
+  if (isAAPCS16_ABI())
     stackAlignment = Align(16);
 
   // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
   // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
   // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
   // support in the assembler and linker to be used. This would need to be
   // fixed to fully support tail calls in Thumb1.
   //
bool ARMSubtarget::useFastISel() const {
   // Enable fast-isel for any target, for testing only.
   if (ForceFastISel)
     return true;
 
   // Limit fast-isel to the targets that are or have been tested.
   if (!hasV6Ops())
     return false;
 
-  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
-  return TM.Options.EnableFastISel &&
-         ((isTargetMachO() && !isThumb1Only()) ||
-          (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
+  // Thumb2 support on iOS; ARM support on iOS and Linux.
+  return TM.Options.EnableFastISel && ((isTargetMachO() && !isThumb1Only()) ||
+                                       (isTargetLinux() && !isThumb()));
 }
 
 unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const {
   // The GPR register class has multiple possible allocation orders, with
   // tradeoffs preferred by different sub-architectures and optimisation goals.
   // The allocation orders are:
   // 0: (the default tablegen order, not used)
   // 1: r14, r0-r13

llvm/lib/Target/ARM/ARMTargetMachine.cpp

static std::string computeDataLayout(const Triple &TT, StringRef CPU,
   // particular hardware support on 32-bit ARM).
   Ret += "-a:0:32";
 
   // Integer registers are 32 bits.
   Ret += "-n32";
 
   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
   // aligned everywhere else.
-  if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
+  if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     Ret += "-S128";
   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
     Ret += "-S64";
   else
     Ret += "-S32";
 
   return Ret;
 }

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

if (ArchID != ARM::ArchKind::INVALID &&  (CPU.empty() || CPU == "generic"))
     ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
 
   if (TT.isThumb()) {
     if (!ARMArchFeature.empty())
       ARMArchFeature += ",";
     ARMArchFeature += "+thumb-mode,+v4t";
   }
 
-  if (TT.isOSNaCl()) {
-    if (!ARMArchFeature.empty())
-      ARMArchFeature += ",";
-    ARMArchFeature += "+nacl-trap";
-  }
-
   if (TT.isOSWindows()) {
     if (!ARMArchFeature.empty())
       ARMArchFeature += ",";
     ARMArchFeature += "+noarm";
   }
 
   return ARMArchFeature;
 }

llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMMipsDesc
   MipsABIInfo.cpp
   MipsABIFlagsSection.cpp
   MipsAsmBackend.cpp
   MipsELFObjectWriter.cpp
   MipsELFStreamer.cpp
   MipsInstPrinter.cpp
   MipsMCAsmInfo.cpp
   MipsMCCodeEmitter.cpp
   MipsMCExpr.cpp
   MipsMCTargetDesc.cpp
-  MipsNaClELFStreamer.cpp
   MipsOptionRecord.cpp
   MipsTargetStreamer.cpp
   )

llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h

-//===-- MipsMCNaCl.h - NaCl-related declarations --------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
-#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
-
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/Support/Alignment.h"
-
-namespace llvm {
-
-// NaCl MIPS sandbox's instruction bundle size.
-static const Align MIPS_NACL_BUNDLE_ALIGN = Align(16);
-
-bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
-                                  bool *IsStore = nullptr);
-bool baseRegNeedsLoadStoreMask(unsigned Reg);
-
-// This function creates an MCELFStreamer for Mips NaCl.
-MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
-                                         std::unique_ptr<MCAsmBackend> TAB,
-                                         std::unique_ptr<MCObjectWriter> OW,
-                                         std::unique_ptr<MCCodeEmitter> Emitter,
-                                         bool RelaxAll);
-}
-
-#endif

llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp

 //===----------------------------------------------------------------------===//
 
 #include "MipsMCTargetDesc.h"
 #include "MipsAsmBackend.h"
 #include "MipsBaseInfo.h"
 #include "MipsELFStreamer.h"
 #include "MipsInstPrinter.h"
 #include "MipsMCAsmInfo.h"
-#include "MipsMCNaCl.h"
 #include "MipsTargetStreamer.h"
 #include "TargetInfo/MipsTargetInfo.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
   return new MipsInstPrinter(MAI, MII, MRI);
 }
 
 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
                                     std::unique_ptr<MCAsmBackend> &&MAB,
                                     std::unique_ptr<MCObjectWriter> &&OW,
                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
                                     bool RelaxAll) {
-  MCStreamer *S;
-  if (!T.isOSNaCl())
-    S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
+  return createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
                                std::move(Emitter), RelaxAll);
-  else
-    S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW),
-                                  std::move(Emitter), RelaxAll);
-  return S;
 }
 
 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
                                                      formatted_raw_ostream &OS,
                                                      MCInstPrinter *InstPrint,
                                                      bool isVerboseAsm) {
   return new MipsTargetAsmStreamer(S, OS);
 }

llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp

-//===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements MCELFStreamer for Mips NaCl.  It emits .o object files
-// as required by NaCl's SFI sandbox.  It inserts address-masking instructions
-// before dangerous control-flow and memory access instructions.  It inserts
-// address-masking instructions after instructions that change the stack
-// pointer.  It ensures that the mask and the dangerous instruction are always
-// emitted in the same bundle.  It aligns call + branch delay to the bundle end,
-// so that return address is always aligned to the start of next bundle.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Mips.h"
-#include "MipsELFStreamer.h"
-#include "MipsMCNaCl.h"
-#include "llvm/MC/MCAsmBackend.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/Support/ErrorHandling.h"
-#include <cassert>
-
-using namespace llvm;
-
-#define DEBUG_TYPE "mips-mc-nacl"
-
-namespace {
-
-const unsigned IndirectBranchMaskReg = Mips::T6;
-const unsigned LoadStoreStackMaskReg = Mips::T7;
-
-/// Extend the generic MCELFStreamer class so that it can mask dangerous
-/// instructions.
-
-class MipsNaClELFStreamer : public MipsELFStreamer {
-public:
-  MipsNaClELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
-                      std::unique_ptr<MCObjectWriter> OW,
-                      std::unique_ptr<MCCodeEmitter> Emitter)
-      : MipsELFStreamer(Context, std::move(TAB), std::move(OW),
-                        std::move(Emitter)) {}
-
-  ~MipsNaClELFStreamer() override = default;
-
-private:
-  // Whether we started the sandboxing sequence for calls.  Calls are bundled
-  // with branch delays and aligned to the bundle end.
-  bool PendingCall = false;
-
-  bool isIndirectJump(const MCInst &MI) {
-    if (MI.getOpcode() == Mips::JALR) {
-      // MIPS32r6/MIPS64r6 doesn't have a JR instruction and uses JALR instead.
-      // JALR is an indirect branch if the link register is $0.
-      assert(MI.getOperand(0).isReg());
-      return MI.getOperand(0).getReg() == Mips::ZERO;
-    }
-    return MI.getOpcode() == Mips::JR;
-  }
-
-  bool isStackPointerFirstOperand(const MCInst &MI) {
-    return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
-            && MI.getOperand(0).getReg() == Mips::SP);
-  }
-
-  bool isCall(const MCInst &MI, bool *IsIndirectCall) {
-    unsigned Opcode = MI.getOpcode();
-
-    *IsIndirectCall = false;
-
-    switch (Opcode) {
-    default:
-      return false;
-
-    case Mips::JAL:
-    case Mips::BAL:
-    case Mips::BAL_BR:
-    case Mips::BLTZAL:
-    case Mips::BGEZAL:
-      return true;
-
-    case Mips::JALR:
-      // JALR is only a call if the link register is not $0. Otherwise it's an
-      // indirect branch.
-      assert(MI.getOperand(0).isReg());
-      if (MI.getOperand(0).getReg() == Mips::ZERO)
-        return false;
-
-      *IsIndirectCall = true;
-      return true;
-    }
-  }
-
-  void emitMask(unsigned AddrReg, unsigned MaskReg,
-                const MCSubtargetInfo &STI) {
-    MCInst MaskInst;
-    MaskInst.setOpcode(Mips::AND);
-    MaskInst.addOperand(MCOperand::createReg(AddrReg));
-    MaskInst.addOperand(MCOperand::createReg(AddrReg));
-    MaskInst.addOperand(MCOperand::createReg(MaskReg));
-    MipsELFStreamer::emitInstruction(MaskInst, STI);
-  }
-
-  // Sandbox indirect branch or return instruction by inserting mask operation
-  // before it.
-  void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
-    unsigned AddrReg = MI.getOperand(0).getReg();
-
-    emitBundleLock(false);
-    emitMask(AddrReg, IndirectBranchMaskReg, STI);
-    MipsELFStreamer::emitInstruction(MI, STI);
-    emitBundleUnlock();
-  }
-
-  // Sandbox memory access or SP change.  Insert mask operation before and/or
-  // after the instruction.
-  void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
-                                   const MCSubtargetInfo &STI, bool MaskBefore,
-                                   bool MaskAfter) {
-    emitBundleLock(false);
-    if (MaskBefore) {
-      // Sandbox memory access.
-      unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
-      emitMask(BaseReg, LoadStoreStackMaskReg, STI);
-    }
-    MipsELFStreamer::emitInstruction(MI, STI);
-    if (MaskAfter) {
-      // Sandbox SP change.
-      unsigned SPReg = MI.getOperand(0).getReg();
-      assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
-      emitMask(SPReg, LoadStoreStackMaskReg, STI);
-    }
-    emitBundleUnlock();
-  }
-
-public:
-  /// This function is the one used to emit instruction data into the ELF
-  /// streamer.  We override it to mask dangerous instructions.
-  void emitInstruction(const MCInst &Inst,
-                       const MCSubtargetInfo &STI) override {
-    // Sandbox indirect jumps.
-    if (isIndirectJump(Inst)) {
-      if (PendingCall)
-        report_fatal_error("Dangerous instruction in branch delay slot!");
-      sandboxIndirectJump(Inst, STI);
-      return;
-    }
-
-    // Sandbox loads, stores and SP changes.
-    unsigned AddrIdx = 0;
-    bool IsStore = false;
-    bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
-                                                    &IsStore);
-    bool IsSPFirstOperand = isStackPointerFirstOperand(Inst);
-    if (IsMemAccess || IsSPFirstOperand) {
-      bool MaskBefore = (IsMemAccess
-                         && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
-                                                          .getReg()));
-      bool MaskAfter = IsSPFirstOperand && !IsStore;
-      if (MaskBefore || MaskAfter) {
-        if (PendingCall)
-          report_fatal_error("Dangerous instruction in branch delay slot!");
-        sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
-        return;
-      }
-      // fallthrough
-    }
-
-    // Sandbox calls by aligning call and branch delay to the bundle end.
-    // For indirect calls, emit the mask before the call.
-    bool IsIndirectCall;
-    if (isCall(Inst, &IsIndirectCall)) {
-      if (PendingCall)
-        report_fatal_error("Dangerous instruction in branch delay slot!");
-
-      // Start the sandboxing sequence by emitting call.
-      emitBundleLock(true);
-      if (IsIndirectCall) {
-        unsigned TargetReg = Inst.getOperand(1).getReg();
-        emitMask(TargetReg, IndirectBranchMaskReg, STI);
-      }
-      MipsELFStreamer::emitInstruction(Inst, STI);
-      PendingCall = true;
-      return;
-    }
-    if (PendingCall) {
-      // Finish the sandboxing sequence by emitting branch delay.
-      MipsELFStreamer::emitInstruction(Inst, STI);
-      emitBundleUnlock();
-      PendingCall = false;
-      return;
-    }
-
-    // None of the sandboxing applies, just emit the instruction.
-    MipsELFStreamer::emitInstruction(Inst, STI);
-  }
-};
-
-} // end anonymous namespace
-
-namespace llvm {
-
-bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
-                                  bool *IsStore) {
-  if (IsStore)
-    *IsStore = false;
-
-  switch (Opcode) {
-  default:
-    return false;
-
-  // Load instructions with base address register in position 1.
-  case Mips::LB:
-  case Mips::LBu:
-  case Mips::LH:
-  case Mips::LHu:
-  case Mips::LW:
-  case Mips::LWC1:
-  case Mips::LDC1:
-  case Mips::LL:
-  case Mips::LL_R6:
-  case Mips::LWL:
-  case Mips::LWR:
-    *AddrIdx = 1;
-    return true;
-
-  // Store instructions with base address register in position 1.
-  case Mips::SB:
-  case Mips::SH:
-  case Mips::SW:
-  case Mips::SWC1:
-  case Mips::SDC1:
-  case Mips::SWL:
-  case Mips::SWR:
-    *AddrIdx = 1;
-    if (IsStore)
-      *IsStore = true;
-    return true;
-
-  // Store instructions with base address register in position 2.
-  case Mips::SC:
-  case Mips::SC_R6:
-    *AddrIdx = 2;
-    if (IsStore)
-      *IsStore = true;
-    return true;
-  }
-}
-
-bool baseRegNeedsLoadStoreMask(unsigned Reg) {
-  // The contents of SP and thread pointer register do not require masking.
-  return Reg != Mips::SP && Reg != Mips::T8;
-}
-
-MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
-                                         std::unique_ptr<MCAsmBackend> TAB,
-                                         std::unique_ptr<MCObjectWriter> OW,
-                                         std::unique_ptr<MCCodeEmitter> Emitter,
-                                         bool RelaxAll) {
-  MipsNaClELFStreamer *S = new MipsNaClELFStreamer(
-      Context, std::move(TAB), std::move(OW), std::move(Emitter));
-  if (RelaxAll)
-    S->getAssembler().setRelaxAll(true);
-
-  // Set bundle-alignment as required by the NaCl ABI for the target.
-  S->emitBundleAlignMode(Log2(MIPS_NACL_BUNDLE_ALIGN));
-
-  return S;
-}
-
-} // end namespace llvm

llvm/lib/Target/Mips/MipsAsmPrinter.h

void EmitSwapFPIntParams(const MCSubtargetInfo &STI,
                            Mips16HardFloatInfo::FPParamVariant, bool LE,
                            bool ToFP);
 
   void EmitSwapFPIntRetval(const MCSubtargetInfo &STI,
                            Mips16HardFloatInfo::FPReturnVariant, bool LE);
 
   void EmitFPCallStub(const char *, const Mips16HardFloatInfo::FuncSignature *);
 
-  void NaClAlignIndirectJumpTargets(MachineFunction &MF);
-
   bool isLongBranchPseudo(int Opcode) const;
 
 public:
   const MipsSubtarget *Subtarget;
   const MipsFunctionInfo *MipsFI;
   MipsMCInstLower MCInstLowering;
 
   explicit MipsAsmPrinter(TargetMachine &TM,

llvm/lib/Target/Mips/MipsAsmPrinter.cpp

 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MipsAsmPrinter.h"
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "MCTargetDesc/MipsInstPrinter.h"
-#include "MCTargetDesc/MipsMCNaCl.h"
 #include "MCTargetDesc/MipsMCTargetDesc.h"
 #include "Mips.h"
 #include "MipsMCInstLower.h"
 #include "MipsMachineFunction.h"
 #include "MipsSubtarget.h"
 #include "MipsTargetMachine.h"
 #include "MipsTargetStreamer.h"
 #include "TargetInfo/MipsTargetInfo.h"
for (std::map<
          it != MipsFI->StubsNeeded.end(); ++it) {
       const char *Symbol = it->first;
       const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
       if (StubsNeeded.find(Symbol) == StubsNeeded.end())
         StubsNeeded[Symbol] = Signature;
     }
   MCP = MF.getConstantPool();
 
-  // In NaCl, all indirect jump targets must be aligned to bundle size.
-  if (Subtarget->isTargetNaCl())
-    NaClAlignIndirectJumpTargets(MF);
-
   AsmPrinter::runOnMachineFunction(MF);
 
   emitXRayTable();
 
   return true;
 }
 
 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
const char *MipsAsmPrinter::getCurrentABIString() const {
   case MipsABIInfo::ABI::N64:  return "abi64";
   default: llvm_unreachable("Unknown Mips ABI");
   }
 }
 
 void MipsAsmPrinter::emitFunctionEntryLabel() {
   MipsTargetStreamer &TS = getTargetStreamer();
 
-  // NaCl sandboxing requires that indirect call instructions are masked.
-  // This means that function entry points should be bundle-aligned.
-  if (Subtarget->isTargetNaCl())
-    emitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
-
   if (Subtarget->inMicroMipsMode()) {
     TS.emitDirectiveSetMicroMips();
     TS.setUsesMicroMips();
     TS.updateABIInfo(*Subtarget);
   } else
     TS.emitDirectiveSetNoMicroMips();
 
   if (Subtarget->inMips16Mode())
if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) {
         llvm_unreachable("Unexpected size of expression value.");
       }
       return;
     }
   }
   AsmPrinter::emitDebugValue(Value, Size);
 }
 
-// Align all targets of indirect branches on bundle size.  Used only if target
-// is NaCl.
-void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
-  // Align all blocks that are jumped to through jump table.
-  if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
-    const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
-    for (unsigned I = 0; I < JT.size(); ++I) {
-      const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
-
-      for (unsigned J = 0; J < MBBs.size(); ++J)
-        MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
-    }
-  }
-
-  // If basic block address is taken, block can be target of indirect branch.
-  for (auto &MBB : MF) {
-    if (MBB.hasAddressTaken())
-      MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
-  }
-}
-
 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
   return (Opcode == Mips::LONG_BRANCH_LUi
           || Opcode == Mips::LONG_BRANCH_LUi2Op
           || Opcode == Mips::LONG_BRANCH_LUi2Op_64
           || Opcode == Mips::LONG_BRANCH_ADDiu
           || Opcode == Mips::LONG_BRANCH_ADDiu2Op
           || Opcode == Mips::LONG_BRANCH_DADDiu
           || Opcode == Mips::LONG_BRANCH_DADDiu2Op);

llvm/lib/Target/Mips/MipsBranchExpansion.cpp

 /// This pass has to run after the delay slot filler as that pass can introduce
 /// pipeline hazards such as compact branch hazard, hence the existing hazard
 /// recognizer is not suitable.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/MipsABIInfo.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
-#include "MCTargetDesc/MipsMCNaCl.h"
 #include "MCTargetDesc/MipsMCTargetDesc.h"
 #include "Mips.h"
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
 #include "MipsSubtarget.h"
 #include "MipsTargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
if (!ABI.IsN64()) {
       Pos = BalTgtMBB->begin();
 
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
           .addReg(Mips::RA)
           .addReg(Mips::AT);
       BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
           .addReg(Mips::SP)
           .addImm(0);
-      if (STI->isTargetNaCl())
-        // Bundle-align the target of indirect branch JR.
-        TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
 
-      // In NaCl, modifying the sp is not allowed in branch delay slot.
       // For MIPS32R6, we can skip using a delay slot branch.
       bool hasDelaySlot = buildProperJumpMI(BalTgtMBB, Pos, DL);
 
-      if (STI->isTargetNaCl() || !hasDelaySlot) {
+      if (!hasDelaySlot) {
         BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
             .addReg(Mips::SP)
             .addImm(8);
       }
       if (hasDelaySlot) {
-        if (STI->isTargetNaCl()) {
-          BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
-        } else {
-          BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
-              .addReg(Mips::SP)
-              .addImm(8);
-        }
         BalTgtMBB->rbegin()->bundleWithPred();
       }
     } else {
       // Pre R6:
       // $longbr:
       //  daddiu $sp, $sp, -16
       //  sd $ra, 0($sp)
       //  daddiu $at, $zero, %hi($tgt - $baltgt)
for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
       ReverseIter End = MBB->rend();
       ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
 
       if ((Br != End) && Br->isBranch() && !Br->isIndirectBranch() &&
           (Br->isConditionalBranch() ||
            (Br->isUnconditionalBranch() && IsPIC))) {
         int64_t Offset = computeOffset(&*Br);
 
-        if (STI->isTargetNaCl()) {
-          // The offset calculation does not include sandboxing instructions
-          // that will be added later in the MC layer.  Since at this point we
-          // don't know the exact amount of code that "sandboxing" will add, we
-          // conservatively estimate that code will not grow more than 100%.
-          Offset *= 2;
-        }
-
         if (ForceLongBranchFirstPass ||
             !TII->isBranchOffsetInRange(Br->getOpcode(), Offset)) {
           MBBInfos[I].Offset = Offset;
           MBBInfos[I].Br = &*Br;
         }
       }
     } // End for
 

llvm/lib/Target/Mips/MipsCallingConv.td

def CC_Mips_FastCC : CallingConv<[
   // Handles byval parameters.
   CCIfByVal<CCPassByVal<4, 4>>,
 
   // Promote i8/i16 arguments to i32.
   CCIfType<[i8, i16], CCPromoteToType<i32>>,
 
   // Integer arguments are passed in integer registers. All scratch registers,
   // except for AT, V0 and T9, are available to be used as argument registers.
-  CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
-      CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
-
-  // In NaCl, T6, T7 and T8 are reserved and not available as argument
-  // registers for fastcc.  T6 contains the mask for sandboxing control flow
-  // (indirect jumps and calls).  T7 contains the mask for sandboxing memory
-  // accesses (loads and stores).  T8 contains the thread pointer.
-  CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
-      CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
+  CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>,
 
   // f32 arguments are passed in single-precision floating pointer registers.
   CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
       CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
                      F14, F15, F16, F17, F18, F19]>>>,
 
   // Don't use odd numbered single-precision registers for -mno-odd-spreg.
   CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",

llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

 //===- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // Simple pass to fill delay slots with useful instructions.
 //
 //===----------------------------------------------------------------------===//
 
-#include "MCTargetDesc/MipsMCNaCl.h"
 #include "Mips.h"
 #include "MipsInstrInfo.h"
 #include "MipsRegisterInfo.h"
 #include "MipsSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/PointerUnion.h"
 #include "llvm/ADT/SmallPtrSet.h"
if (CurrI->isKill()) {
       CurrI->eraseFromParent();
       continue;
     }
 
     if (delayHasHazard(*CurrI, RegDU, IM))
       continue;
 
     const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
-    if (STI.isTargetNaCl()) {
-      // In NaCl, instructions that must be masked are forbidden in delay slots.
-      // We only check for loads, stores and SP changes.  Calls, returns and
-      // branches are not checked because non-NaCl targets never put them in
-      // delay slots.
-      unsigned AddrIdx;
-      if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
-           baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
-          CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
-        continue;
-    }
 
     bool InMicroMipsMode = STI.inMicroMipsMode();
     const MipsInstrInfo *TII = STI.getInstrInfo();
     unsigned Opcode = (*Slot).getOpcode();
     // This is complicated by the tail call optimization. For non-PIC code
     // there is only a 32bit sized unconditional branch which can be assumed
     // to be able to reach the target. b16 only has a range of +/- 1 KB.
     // It's entirely possible that the target function is reachable with b16

llvm/lib/Target/Mips/MipsInstrFPU.td

let AdditionalPredicates = [NotInMicroMips] in {
   }
   def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
              LW_FM<0x3d>, ISA_MIPS2, FGR_32;
 }
 
 // Indexed loads and stores.
 // Base register + offset register addressing mode (indicated by "x" in the
 // instruction mnemonic) is disallowed under NaCl.
-let AdditionalPredicates = [IsNotNaCl] in {
-  def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
-              INSN_MIPS4_32R2_NOT_32R6_64R6;
-  def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
-              INSN_MIPS4_32R2_NOT_32R6_64R6;
-}
 
-let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
+let AdditionalPredicates = [NotInMicroMips] in {
   def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
               INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
   def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
               INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
 }
 
 let DecoderNamespace="MipsFP64" in {
   def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
                 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
   def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
                 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
 }
 
 // Load/store doubleword indexed unaligned.
 // FIXME: This instruction should not be defined for FGR_32.
-let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in {
+let AdditionalPredicates = [NotInMicroMips] in {
   def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
               INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
   def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
               INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
 }
 
-let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
+let AdditionalPredicates = [NotInMicroMips],
     DecoderNamespace="MipsFP64" in {
   def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
                 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
   def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
                 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
 }
 
 /// Floating-point Arithmetic

llvm/lib/Target/Mips/MipsInstrInfo.td

def HasStdEnc :       Predicate<"Subtarget->hasStandardEncoding()">,
                       AssemblerPredicate<(all_of (not FeatureMips16))>;
 def NotDSP :          Predicate<"!Subtarget->hasDSP()">;
 def InMicroMips    :  Predicate<"Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<(all_of FeatureMicroMips)>;
 def NotInMicroMips :  Predicate<"!Subtarget->inMicroMipsMode()">,
                       AssemblerPredicate<(all_of (not FeatureMicroMips))>;
 def IsLE           :  Predicate<"Subtarget->isLittle()">;
 def IsBE           :  Predicate<"!Subtarget->isLittle()">;
-def IsNotNaCl    :    Predicate<"!Subtarget->isTargetNaCl()">;
 def UseTCCInDIV    :  AssemblerPredicate<(all_of FeatureUseTCCInDIV)>;
 def HasEVA       :    Predicate<"Subtarget->hasEVA()">,
                       AssemblerPredicate<(all_of FeatureEVA)>;
 def HasMSA : Predicate<"Subtarget->hasMSA()">,
              AssemblerPredicate<(all_of FeatureMSA)>;
 def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">,
                AssemblerPredicate<(all_of (not FeatureMadd4))>;
 def HasMT  : Predicate<"Subtarget->hasMT()">,

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

getReservedRegs(const MachineFunction &MF) const {
   };
 
   BitVector Reserved(getNumRegs());
   const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
 
   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
     Reserved.set(ReservedGPR32[I]);
 
-  // Reserve registers for the NaCl sandbox.
-  if (Subtarget.isTargetNaCl()) {
-    Reserved.set(Mips::T6);   // Reserved for control flow mask.
-    Reserved.set(Mips::T7);   // Reserved for memory access mask.
-    Reserved.set(Mips::T8);   // Reserved for thread pointer.
-  }
-
   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
     Reserved.set(ReservedGPR64[I]);
 
   // For mno-abicalls, GP is a program invariant!
   if (!Subtarget.isABICalls()) {
     Reserved.set(Mips::GP);
     Reserved.set(Mips::GP_64);
   }

llvm/lib/Target/Mips/MipsSubtarget.h

public:
   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
   bool hasMTHC1() const { return hasMips32r2(); }
 
   bool allowMixed16_32() const { return inMips16ModeDefault() |
                                         AllowMixed16_32; }
 
   bool os16() const { return Os16; }
 
-  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
-
   bool isXRaySupported() const override { return true; }
 
   // for now constant islands are on for the whole compilation unit but we only
   // really use them if in addition we are in mips16 mode
   static bool useConstantIslands();
 
   Align getStackAlignment() const { return stackAlignment; }
 

llvm/lib/Target/X86/X86ExpandPseudo.cpp

case X86::TCRETURNmi64: {
     MBB.erase(MBBI);
 
     return true;
   }
   case X86::EH_RETURN:
   case X86::EH_RETURN64: {
     MachineOperand &DestAddr = MBBI->getOperand(0);
     assert(DestAddr.isReg() && "Offset should be in register!");
-    const bool Uses64BitFramePtr =
-        STI->isTarget64BitLP64() || STI->isTargetNaCl64();
     Register StackPtr = TRI->getStackRegister();
     BuildMI(MBB, MBBI, DL,
-            TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
+            TII->get(STI->isTarget64BitLP64() ? X86::MOV64rr : X86::MOV32rr),
+            StackPtr)
         .addReg(DestAddr.getReg());
     // The EH_RETURN pseudo is really removed during the MC Lowering.
     return true;
   }
   case X86::IRET: {
     // Adjust stack to erase error code
     int64_t StackAdj = MBBI->getOperand(0).getImm();
     X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);

llvm/lib/Target/X86/X86FrameLowering.cpp

X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
     : TargetFrameLowering(StackGrowsDown, StackAlignOverride.valueOrOne(),
                           STI.is64Bit() ? -8 : -4),
       STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
   // Cache a bunch of frame-related predicates for this subtarget.
   SlotSize = TRI->getSlotSize();
   Is64Bit = STI.is64Bit();
   IsLP64 = STI.isTarget64BitLP64();
   // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
-  Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
+  Uses64BitFramePtr = STI.isTarget64BitLP64();
   StackPtr = TRI->getStackRegister();
 }
 
 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
   return !MF.getFrameInfo().hasVarSizedObjects() &&
          !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
 }
 

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

case Intrinsic::x86_clzero: {
 
       break;
     }
     }
 
     break;
   }
   case ISD::BRIND: {
-    if (Subtarget->isTargetNaCl())
-      // NaCl has its own pass where jmp %r32 are converted to jmp %r64. We
-      // leave the instruction alone.
-      break;
     if (Subtarget->isTarget64BitILP32()) {
       // Converts a 32-bit register to a 64-bit, zero-extended version of
       // it. This is needed because x86-64 can do many things, but jmp %r32
       // ain't one of them.
       SDValue Target = Node->getOperand(1);
       assert(Target.getValueType() == MVT::i32 && "Unexpected VT!");
       SDValue ZextTarget = CurDAG->getZExtOrTrunc(Target, dl, MVT::i64);
       SDValue Brind = CurDAG->getNode(ISD::BRIND, dl, MVT::Other,

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
   const TargetRegisterClass *AddrRegClass =
       getRegClassFor(getPointerTy(MF->getDataLayout()));
 
   unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
            bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
            tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
            SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
            sizeVReg = MI.getOperand(1).getReg(),
-           physSPReg =
-               IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP;
+           physSPReg = IsLP64 ? X86::RSP : X86::ESP;
 
   MachineFunction::iterator MBBIter = ++BB->getIterator();
 
   MF->insert(MBBIter, bumpMBB);
   MF->insert(MBBIter, mallocMBB);
   MF->insert(MBBIter, continueMBB);
 
   continueMBB->splice(continueMBB->begin(), BB,
X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
   // sinkMBB:
   BuildMI(*sinkMBB, sinkMBB->begin(), DL,
           TII->get(X86::PHI), DstReg)
     .addReg(mainDstReg).addMBB(mainMBB)
     .addReg(restoreDstReg).addMBB(restoreMBB);
 
   // restoreMBB:
   if (RegInfo->hasBasePointer(*MF)) {
-    const bool Uses64BitFramePtr =
-        Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
+    const bool Uses64BitFramePtr = Subtarget.isTarget64BitLP64();
     X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
     X86FI->setRestoreBasePointer(MF);
     Register FramePtr = RegInfo->getFrameRegister(*MF);
     Register BasePtr = RegInfo->getBaseRegister();
     unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
     addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
                  FramePtr, true, X86FI->getRestoreBasePointerOffset())
       .setMIFlag(MachineInstr::FrameSetup);
X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
   unsigned JTE = getJumpTableEncoding();
   MachineJumpTableInfo *JTI = MF->getOrCreateJumpTableInfo(JTE);
   unsigned MJTI = JTI->createJumpTableIndex(LPadList);
 
   const X86RegisterInfo &RI = TII->getRegisterInfo();
   // Add a register mask with no preserved registers.  This results in all
   // registers being marked as clobbered.
   if (RI.hasBasePointer(*MF)) {
-    const bool FPIs64Bit =
-        Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
+    const bool FPIs64Bit = Subtarget.isTarget64BitLP64();
     X86MachineFunctionInfo *MFI = MF->getInfo<X86MachineFunctionInfo>();
     MFI->setRestoreBasePointer(MF);
 
     Register FP = RI.getFrameRegister(*MF);
     Register BP = RI.getBaseRegister();
     unsigned Op = FPIs64Bit ? X86::MOV64rm : X86::MOV32rm;
     addRegOffset(BuildMI(DispatchBB, DL, TII->get(Op), BP), FP, true,
                  MFI->getRestoreBasePointerOffset())

llvm/lib/Target/X86/X86InstrInfo.td

 def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
 def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
 def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||"
                                   "Subtarget->getFrameLowering()->hasFP(*MF)"> {
   let RecomputePerFunction = 1;
 }
 def IsPS4        : Predicate<"Subtarget->isTargetPS4()">;
 def NotPS4       : Predicate<"!Subtarget->isTargetPS4()">;
-def IsNaCl       : Predicate<"Subtarget->isTargetNaCl()">;
-def NotNaCl      : Predicate<"!Subtarget->isTargetNaCl()">;
 def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
 def KernelCode   : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
 def NearData     : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
                              "TM.getCodeModel() == CodeModel::Kernel">;
 def IsNotPIC     : Predicate<"!TM.isPositionIndependent()">;
 
 // We could compute these on a per-module basis but doing so requires accessing
 // the Function object through the <Target>Subtarget and objections were raised

llvm/lib/Target/X86/X86Subtarget.h

public:
   }
 
   bool is16Bit() const {
     return In16BitMode;
   }
 
   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
   bool isTarget64BitILP32() const {
-    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
-                           TargetTriple.isOSNaCl());
+    return In64BitMode && TargetTriple.getEnvironment() == Triple::GNUX32;
   }
 
   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
   bool isTarget64BitLP64() const {
-    return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
-                           !TargetTriple.isOSNaCl());
+    return In64BitMode && TargetTriple.getEnvironment() != Triple::GNUX32;
   }
 
   PICStyles::Style getPICStyle() const { return PICStyle; }
   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
 
   bool hasX87() const { return HasX87; }
   bool hasCmpxchg8b() const { return HasCmpxchg8b; }
   bool hasNOPL() const { return HasNOPL; }
public:
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
   bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
-  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
-  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
-  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
   bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 
   bool isTargetWindowsMSVC() const {
     return TargetTriple.isWindowsMSVCEnvironment();
   }
 
   bool isTargetWindowsCoreCLR() const {

llvm/lib/Target/X86/X86TargetMachine.cpp

 }
 
 static std::string computeDataLayout(const Triple &TT) {
   // X86 is little endian
   std::string Ret = "e";
 
   Ret += DataLayout::getManglingComponent(TT);
   // X86 and x32 have 32 bit pointers.
-  if ((TT.isArch64Bit() &&
-       (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
+  if ((TT.isArch64Bit() && TT.getEnvironment() == Triple::GNUX32) ||
       !TT.isArch64Bit())
     Ret += "-p:32:32";
 
   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
   Ret += "-p270:32:32-p271:32:32-p272:64:64";
 
   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
-  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
+  if (TT.isArch64Bit() || TT.isOSWindows())
     Ret += "-i64:64";
   else if (TT.isOSIAMCU())
     Ret += "-i64:32-f64:32";
   else
     Ret += "-f64:32:64";
 
   // Some ABIs align long double to 128 bits, others to 32.
-  if (TT.isOSNaCl() || TT.isOSIAMCU())
+  if (TT.isOSIAMCU())
     ; // No f80
   else if (TT.isArch64Bit() || TT.isOSDarwin())
     Ret += "-f80:128";
   else
     Ret += "-f80:32";
 
   if (TT.isOSIAMCU())
     Ret += "-f128:32";

llvm/test/CodeGen/ARM/fast-isel-align.ll

 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 
 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 
-; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
-
 ; RUN: llc < %s -O0 -mattr=+strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0  -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
 ; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
 
 ; Check unaligned stores

llvm/test/CodeGen/ARM/struct_byval.ll

 ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s
-; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL
 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT
 
 ; NOMOVT-NOT: movt
 
 ; rdar://9877866
 %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] }
 %struct.LargeStruct = type { i32, [1001 x i8], [300 x i32] }
 

 ; Generate a loop for large struct byval
 define i32 @g() nounwind ssp {
 entry:
 ; CHECK-LABEL: g:
 ; CHECK: ldr
 ; CHECK: sub
 ; CHECK: str
 ; CHECK: bne
-; NACL-LABEL: g:
-; Ensure that use movw instead of constpool for the loop trip count. But don't
-; match the __stack_chk_guard movw
-; NACL: movw r{{[1-9]}}, #
-; NACL: ldr
-; NACL: sub
-; NACL: str
-; NACL: bne
   %st = alloca %struct.LargeStruct, align 4
   %call = call i32 @e2(%struct.LargeStruct* byval %st)
   ret i32 0
 }
 
 ; Generate a loop using NEON instructions
 define i32 @h() nounwind ssp {
 entry:
 ; CHECK-LABEL: h:
 ; CHECK: vld1
 ; CHECK: sub
 ; CHECK: vst1
 ; CHECK: bne
-; NACL: movw r{{[1-9]}}, #
-; NACL: vld1
-; NACL: sub
-; NACL: vst1
-; NACL: bne
   %st = alloca %struct.LargeStruct, align 16
   %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st)
   ret i32 0
 }
 
 declare i32 @e1(%struct.SmallStruct* nocapture byval %in) nounwind
 declare i32 @e2(%struct.LargeStruct* nocapture byval %in) nounwind
 declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind

llvm/test/CodeGen/ARM/trap.ll

 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
 ; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC
 ; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap -O0 | FileCheck %s -check-prefix=FUNC
-; RUN: llc < %s -mtriple=armv7 -mattr=+nacl-trap | FileCheck %s -check-prefix=NACL
 ; RUN: llc < %s -mtriple=armv7 | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -mtriple=thumbv7 | FileCheck %s -check-prefix=THUMB
 
-; RUN: llc -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -d --triple=armv7 --mattr=+nacl-trap - \
-; RUN:  | FileCheck %s -check-prefix=ENCODING-NACL
-; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
-; RUN:  | llvm-objdump -d --triple=armv7 --mattr=+nacl-trap - \
-; RUN:  | FileCheck %s -check-prefix=ENCODING-NACL
-
 ; RUN: llc -mtriple=armv7 -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -d --triple=armv7 - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-ARM
 ; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -filetype=obj %s -o - \
 ; RUN:  | llvm-objdump -d --triple=armv7 - \
 ; RUN:  | FileCheck %s -check-prefix=ENCODING-ARM
 
 ; RUN: llc -mtriple=thumbv7 -filetype=obj %s -o - \

 define void @t() nounwind {
 entry:
 ; DARWIN-LABEL: t:
 ; DARWIN: trap
 
 ; FUNC-LABEL: t:
 ; FUNC: bl __trap
 
-; NACL-LABEL: t:
-; NACL: .inst 0xe7fedef0
-
 ; ARM-LABEL: t:
 ; ARM: .inst 0xe7ffdefe
 
 ; THUMB-LABEL: t:
 ; THUMB: .inst.n 0xdefe
 
-; ENCODING-NACL: f0 de fe e7 trap
-
 ; ENCODING-ARM: fe de ff e7 trap
 
 ; ENCODING-THUMB: fe de trap
 
   call void @llvm.trap()
   unreachable
 }
 
 define void @t2() nounwind {
 entry:
 ; DARWIN-LABEL: t2:
 ; DARWIN: udf #254
 
 ; FUNC-LABEL: t2:
 ; FUNC: bl __trap
 
-; NACL-LABEL: t2:
-; NACL: bkpt #0
-
 ; ARM-LABEL: t2:
 ; ARM: bkpt #0
 
 ; THUMB-LABEL: t2:
 ; THUMB: bkpt #0
 
-; ENCODING-NACL: 70 00 20 e1 bkpt #0
-
 ; ENCODING-ARM: 70 00 20 e1 bkpt #0
 
 ; ENCODING-THUMB: 00 be bkpt #0
 
   call void @llvm.debugtrap()
   unreachable
 }
 
 declare void @llvm.trap() nounwind
 declare void @llvm.debugtrap() nounwind

llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll

-; RUN: llc < %s -mtriple=arm-nacl-gnueabi | FileCheck %s
-
-declare void @llvm.va_start(i8*)
-declare void @external_func(i8*)
-
-@va_list = external global i8*
-
-; On ARM, varargs arguments are passed in r0-r3 with the rest on the
-; stack.  A varargs function must therefore spill rN-r3 just below the
-; function's initial stack pointer.
-;
-; This test checks for a bug in which a gap was left between the spill
-; area and varargs arguments on the stack when using 16 byte stack
-; alignment.
-
-define void @varargs_func(i32 %arg1, ...) {
-  call void @llvm.va_start(i8* bitcast (i8** @va_list to i8*))
-  call void @external_func(i8* bitcast (i8** @va_list to i8*))
-  ret void
-}
-; CHECK-LABEL: varargs_func:
-; Reserve space for the varargs save area.  This currently reserves
-; more than enough (16 bytes rather than the 12 bytes needed).
-; CHECK: sub sp, sp, #12
-; CHECK: push {r11, lr}
-; Align the stack pointer to a multiple of 16.
-; CHECK: sub sp, sp, #12
-; Calculate the address of the varargs save area and save varargs
-; arguments into it.
-; CHECK-NEXT: add r0, sp, #20
-; CHECK-NEXT: stm r0, {r1, r2, r3}

llvm/test/CodeGen/Generic/no-target.ll

-; RUN: not llc -mtriple le32-unknown-nacl %s -o - 2>&1 | FileCheck %s
-
-; CHECK: error: unable to get target for 'le32-unknown-nacl'

llvm/test/CodeGen/Mips/fastcc.ll

 ; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu -relocation-model=pic -mips-tail-calls=1\
-; RUN:  | FileCheck %s -check-prefix=CHECK-NACL
 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic -mips-tail-calls=1| FileCheck %s -check-prefix=NOODDSPREG
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic -mips-tail-calls=1 | FileCheck %s -check-prefix=FP64-NOODDSPREG
 
 
 @gi0 = external global i32
 @gi1 = external global i32
 @gi2 = external global i32
 @gi3 = external global i32

 ; CHECK: lw  $10
 ; CHECK: lw  $9
 ; CHECK: lw  $8
 ; CHECK: lw  $7
 ; CHECK: lw  $6
 ; CHECK: lw  $5
 ; CHECK: lw  $4
 
-; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
-; CHECK-NACL-NOT: lw  $14
-; CHECK-NACL-NOT: lw  $15
-; CHECK-NACL-NOT: lw  $24
-
   %0 = load i32, i32* @gi0, align 4
   %1 = load i32, i32* @gi1, align 4
   %2 = load i32, i32* @gi2, align 4
   %3 = load i32, i32* @gi3, align 4
   %4 = load i32, i32* @gi4, align 4
   %5 = load i32, i32* @gi5, align 4
   %6 = load i32, i32* @gi6, align 4
   %7 = load i32, i32* @gi7, align 4

 ; CHECK-DAG: sw  $11
 ; CHECK-DAG: sw  $12
 ; CHECK-DAG: sw  $13
 ; CHECK-DAG: sw  $14
 ; CHECK-DAG: sw  $15
 ; CHECK-DAG: sw  $24
 ; CHECK-DAG: sw  $3
 
-; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
-; CHECK-NACL-NOT: sw  $14
-; CHECK-NACL-NOT: sw  $15
-; CHECK-NACL-NOT: sw  $24
-
   store i32 %a0, i32* @g0, align 4
   store i32 %a1, i32* @g1, align 4
   store i32 %a2, i32* @g2, align 4
   store i32 %a3, i32* @g3, align 4
   store i32 %a4, i32* @g4, align 4
   store i32 %a5, i32* @g5, align 4
   store i32 %a6, i32* @g6, align 4
   store i32 %a7, i32* @g7, align 4

llvm/test/CodeGen/Mips/fp-indexed-ls.ll

 ; RUN: llc -march=mipsel   -mcpu=mips32   -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1
 ; RUN: llc -march=mipsel   -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2
 ; RUN: llc -march=mipsel   -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6
 ; RUN: llc -march=mips64el -mcpu=mips4    -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
 ; RUN: llc -march=mips64el -mcpu=mips64   -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
 ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6
 
-; Check that [ls][dwu]xc1 are not emitted for nacl.
-; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
-
 %struct.S = type <{ [4 x float] }>
 %struct.S2 = type <{ [4 x double] }>
 %struct.S3 = type <{ i8, float }>
 
 @s = external global [4 x %struct.S]
 @gf = external global float
 @gd = external global double
 @s2 = external global [4 x %struct.S2]

 ; MIPS4:         dsll $[[T1:[0-9]+]], $[[T0]], 2
 ; MIPS4:         lwxc1 $f0, $[[T1]]($4)
 
 ; MIPS64R6:      sll $[[T0:[0-9]+]], $5, 0
 ; MIPS64R6:      dsll $[[T1:[0-9]+]], $[[T0]], 2
 ; MIPS64R6:      daddu $[[T3:[0-9]+]], $4, $[[T1]]
 ; MIPS64R6:      lwc1 $f0, 0($[[T3]])
 
-; CHECK-NACL-NOT: lwxc1
-
   %arrayidx = getelementptr inbounds float, float* %b, i32 %o
   %0 = load float, float* %arrayidx, align 4
   ret float %0
 }
 
 define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
 entry:
 ; ALL-LABEL: foo1:

 ; MIPS4:         dsll $[[T1:[0-9]+]], $[[T0]], 3
 ; MIPS4:         ldxc1 $f0, $[[T1]]($4)
 
 ; MIPS64R6:      sll $[[T0:[0-9]+]], $5, 0
 ; MIPS64R6:      dsll $[[T1:[0-9]+]], $[[T0]], 3
 ; MIPS64R6:      daddu $[[T3:[0-9]+]], $4, $[[T1]]
 ; MIPS64R6:      ldc1 $f0, 0($[[T3]])
 
-; CHECK-NACL-NOT: ldxc1
-
   %arrayidx = getelementptr inbounds double, double* %b, i32 %o
   %0 = load double, double* %arrayidx, align 8
   ret double %0
 }
 
 define float @foo2(i32 %b, i32 %c) nounwind readonly {
 entry:
 ; ALL-LABEL: foo2:

 
 ; MIPS4:         lwc1 $[[T0:f0]], 0(${{[0-9]+}})
 ; MIPS4:         swxc1 $[[T0]], ${{[0-9]+}}($4)
 
 ; MIPS64R6-DAG:  lwc1 $[[T0:f0]], 0(${{[0-9]+}})
 ; MIPS64R6-DAG:  daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
 ; MIPS64R6-DAG:  swc1 $[[T0]], 0($[[T1]])
 
-; CHECK-NACL-NOT: swxc1
-
   %0 = load float, float* @gf, align 4
   %arrayidx = getelementptr inbounds float, float* %b, i32 %o
   store float %0, float* %arrayidx, align 4
   ret void
 }
 
 define void @foo4(double* nocapture %b, i32 %o) nounwind {
 entry:

 
 ; MIPS4:         ldc1 $[[T0:f0]], 0(${{[0-9]+}})
 ; MIPS4:         sdxc1 $[[T0]], ${{[0-9]+}}($4)
 
 ; MIPS64R6-DAG:  ldc1 $[[T0:f0]], 0(${{[0-9]+}})
 ; MIPS64R6-DAG:  daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
 ; MIPS64R6-DAG:  sdc1 $[[T0]], 0($[[T1]])
 
-; CHECK-NACL-NOT: sdxc1
-
   %0 = load double, double* @gd, align 8
   %arrayidx = getelementptr inbounds double, double* %b, i32 %o
   store double %0, double* %arrayidx, align 8
   ret void
 }
 
 define void @foo5(i32 %b, i32 %c) nounwind {
 entry:

llvm/test/CodeGen/Mips/longbranch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;       Except for the NACL version which isn't parsed by update_llc_test_checks.py
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -O3 -relocation-model=pic < %s \
 ; RUN:   | FileCheck %s -check-prefix=NOLONGBRANCH
 
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=pic < %s \
 ; RUN:   | FileCheck %s -check-prefix=O32-PIC
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=static < %s \
 ; RUN:   | FileCheck %s -check-prefix=O32-STATIC
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -force-mips-long-branch -O3 \

 ; RUN:   -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSSTATIC
 
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
 ; RUN:   -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSR6STATIC
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
 ; RUN:   -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPSR6PIC
 
 
-; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \
-; RUN:   | FileCheck %s -check-prefix=NACL
-
 
 @x = external global i32
 
 define void @test1(i32 signext %s) {
 ; NOLONGBRANCH-LABEL: test1:
 ; NOLONGBRANCH:       # %bb.0: # %entry
 ; NOLONGBRANCH-NEXT:    lui $2, %hi(_gp_disp)
 ; NOLONGBRANCH-NEXT:    addiu $2, $2, %lo(_gp_disp)

 ; MICROMIPSR6PIC-NEXT:    jic $1, 0
 ; MICROMIPSR6PIC-NEXT:  $BB0_3: # %then
 ; MICROMIPSR6PIC-NEXT:    lw $2, %got(x)($2)
 ; MICROMIPSR6PIC-NEXT:    li16 $3, 1
 ; MICROMIPSR6PIC-NEXT:    sw16 $3, 0($2)
 ; MICROMIPSR6PIC-NEXT:  $BB0_4: # %end
 ; MICROMIPSR6PIC-NEXT:    jrc $ra
 
-; NACL-LABEL: test1:
-; NACL:       # %bb.0:
-; NACL-NEXT:    lui $2, %hi(_gp_disp)
-; NACL-NEXT:    addiu $2, $2, %lo(_gp_disp)
-; NACL-NEXT:    bnez  $4, $BB0_3
-; NACL-NEXT:    addu  $2, $2, $25
-; NACL-NEXT:  # %bb.1:
-; NACL-NEXT:    addiu $sp, $sp, -8
-; NACL-NEXT:    sw  $ra, 0($sp)
-; NACL-NEXT:    lui $1, %hi(($BB0_4)-($BB0_2))
-; NACL-NEXT:    bal $BB0_2
-; NACL-NEXT:    addiu $1, $1, %lo(($BB0_4)-($BB0_2))
-; NACL-NEXT:  $BB0_2:
-; NACL-NEXT:    addu  $1, $ra, $1
-; NACL-NEXT:    lw  $ra, 0($sp)
-; NACL-NEXT:    addiu $sp, $sp, 8
-; NACL-NEXT:    jr  $1
-; NACL-NEXT:    nop
-; NACL-NEXT:  $BB0_3:
-; NACL-NEXT:    lw  $1, %got(x)($2)
-; NACL-NEXT:    addiu $2, $zero, 1
-; NACL-NEXT:    sw  $2, 0($1)
-; NACL-NEXT:    .p2align  4
-; NACL-NEXT:  $BB0_4:
-; NACL-NEXT:    jr  $ra
-; NACL-NEXT:    nop
-
-
-; Check the NaCl version.  Check that sp change is not in the branch delay slot
-; of "jr $1" instruction.  Check that target of indirect branch "jr $1" is
-; bundle aligned.
 
 entry:
   %cmp = icmp eq i32 %s, 0
   br i1 %cmp, label %end, label %then
 
 then:
   store i32 1, i32* @x, align 4
   br label %end
 
 end:
   ret void
 
 }

llvm/test/CodeGen/Mips/nacl-align.ll

-; RUN: llc -filetype=asm -mtriple=mipsel-none-nacl -relocation-model=static \
-; RUN:     -O3 < %s | FileCheck %s
-
-
-; This test tests that NaCl functions are bundle-aligned.
-
-define void @test0() {
-  ret void
-
-; CHECK:          .p2align  4
-; CHECK-NOT:      .p2align
-; CHECK-LABEL:    test0:
-
-}
-
-
-; This test tests that blocks that are jumped to through jump table are
-; bundle-aligned.
-
-define i32 @test1(i32 %i) {
-entry:
-  switch i32 %i, label %default [
-    i32 0, label %bb1
-    i32 1, label %bb2
-    i32 2, label %bb3
-    i32 3, label %bb4
-  ]
-
-bb1:
-  ret i32 111
-bb2:
-  ret i32 222
-bb3:
-  ret i32 333
-bb4:
-  ret i32 444
-default:
-  ret i32 555
-
-
-; CHECK-LABEL:       test1:
-
-; CHECK:             .p2align  4
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 111
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 555
-; CHECK-NEXT:        .p2align  4
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 222
-; CHECK-NEXT:        .p2align  4
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 333
-
-}
-
-
-; This test tests that a block whose address is taken is bundle-aligned in NaCl.
-
-@bb_array = constant [2 x i8*] [i8* blockaddress(@test2, %bb1),
-                                i8* blockaddress(@test2, %bb2)], align 4
-
-define i32 @test2(i32 %i) {
-entry:
-  %elementptr = getelementptr inbounds [2 x i8*], [2 x i8*]* @bb_array, i32 0, i32 %i
-  %0 = load i8*, i8** %elementptr, align 4
-  indirectbr i8* %0, [label %bb1, label %bb2]
-
-bb1:
-  ret i32 111
-bb2:
-  ret i32 222
-
-
-; CHECK-LABEL:       test2:
-
-; Note that there are two consecutive labels - one temporary and one for
-; basic block.
-
-; CHECK:             .p2align  4
-; CHECK-NEXT:    ${{[a-zA-Z0-9]+}}:
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 111
-; CHECK-NEXT:        .p2align  4
-; CHECK-NEXT:    ${{[a-zA-Z0-9]+}}:
-; CHECK-NEXT:    ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT:        jr      $ra
-; CHECK-NEXT:        addiu   $2, $zero, 222
-
-}

llvm/test/CodeGen/Mips/nacl-branch-delay.ll

-; RUN: llc -filetype=asm -mtriple=mipsel-none-linux -relocation-model=static \
-; RUN:     -O3 < %s | FileCheck %s
-
-; RUN: llc -filetype=asm -mtriple=mipsel-none-nacl -relocation-model=static \
-; RUN:     -O3 < %s | FileCheck %s -check-prefix=CHECK-NACL
-
-@x = global i32 0, align 4
-declare void @f1(i32)
-declare void @f2()
-
-
-define void @test1() {
-  %1 = load i32, i32* @x, align 4
-  call void @f1(i32 %1)
-  ret void
-
-
-; CHECK-LABEL:       test1
-
-; We first make sure that for non-NaCl targets branch-delay slot contains
-; dangerous instructions.
-
-; Check that branch-delay slot is used to load argument from x before function
-; call.
-
-; CHECK:             jal
-; CHECK-NEXT:        lw      $4, %lo(x)(${{[0-9]+}})
-
-; Check that branch-delay slot is used for adjusting sp before return.
-
-; CHECK:             jr      $ra
-; CHECK-NEXT:        addiu   $sp, $sp, {{[0-9]+}}
-
-
-; For NaCl, check that branch-delay slot doesn't contain dangerous instructions.
-
-; CHECK-NACL:             jal
-; CHECK-NACL-NEXT:        nop
-
-; CHECK-NACL:             jr      $ra
-; CHECK-NACL-NEXT:        nop
-}
-
-
-define void @test2() {
-  store i32 1, i32* @x, align 4
-  call void @f2()
-  ret void
-
-
-; CHECK-LABEL:       test2
-
-; Check that branch-delay slot is used for storing to x before function call.
-
-; CHECK:             jal
-; CHECK-NEXT:        sw      ${{[0-9]+}}, %lo(x)(${{[0-9]+}})
-
-; Check that branch-delay slot is used for adjusting sp before return.
-
-; CHECK:             jr      $ra
-; CHECK-NEXT:        addiu   $sp, $sp, {{[0-9]+}}
-
-
-; For NaCl, check that branch-delay slot doesn't contain dangerous instructions.
-
-; CHECK-NACL:             jal
-; CHECK-NACL-NEXT:        nop
-
-; CHECK-NACL:             jr      $ra
-; CHECK-NACL-NEXT:        nop
-}

llvm/test/CodeGen/Mips/nacl-reserved-regs.ll

-; RUN: llc -march=mipsel -O3 < %s | FileCheck %s
-; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \
-; RUN:  | FileCheck %s -check-prefix=CHECK-NACL
-
-@var = external global i32
-
-define void @f() {
-  %val1 = load volatile i32, i32* @var
-  %val2 = load volatile i32, i32* @var
-  %val3 = load volatile i32, i32* @var
-  %val4 = load volatile i32, i32* @var
-  %val5 = load volatile i32, i32* @var
-  %val6 = load volatile i32, i32* @var
-  %val7 = load volatile i32, i32* @var
-  %val8 = load volatile i32, i32* @var
-  %val9 = load volatile i32, i32* @var
-  %val10 = load volatile i32, i32* @var
-  %val11 = load volatile i32, i32* @var
-  %val12 = load volatile i32, i32* @var
-  %val13 = load volatile i32, i32* @var
-  %val14 = load volatile i32, i32* @var
-  %val15 = load volatile i32, i32* @var
-  %val16 = load volatile i32, i32* @var
-  store volatile i32 %val1, i32* @var
-  store volatile i32 %val2, i32* @var
-  store volatile i32 %val3, i32* @var
-  store volatile i32 %val4, i32* @var
-  store volatile i32 %val5, i32* @var
-  store volatile i32 %val6, i32* @var
-  store volatile i32 %val7, i32* @var
-  store volatile i32 %val8, i32* @var
-  store volatile i32 %val9, i32* @var
-  store volatile i32 %val10, i32* @var
-  store volatile i32 %val11, i32* @var
-  store volatile i32 %val12, i32* @var
-  store volatile i32 %val13, i32* @var
-  store volatile i32 %val14, i32* @var
-  store volatile i32 %val15, i32* @var
-  store volatile i32 %val16, i32* @var
-  ret void
-
-; Check that t6, t7 and t8 are used in non-NaCl code.
-; CHECK:    lw  $14
-; CHECK:    lw  $15
-; CHECK:    lw  $24
-
-; t6, t7 and t8 are reserved in NaCl.
-; CHECK-NACL-NOT:    lw  $14
-; CHECK-NACL-NOT:    lw  $15
-; CHECK-NACL-NOT:    lw  $24
-}

llvm/test/CodeGen/X86/constructor.ll

 ; RUN: llc -mtriple x86_64 < %s | FileCheck --check-prefix=INIT-ARRAY %s
 ; RUN: llc -mtriple x86_64-pc-linux -use-ctors < %s | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple x86_64-unknown-freebsd -use-ctors < %s | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple x86_64-pc-solaris2.11 -use-ctors < %s | FileCheck --check-prefix=CTOR %s
 ; RUN: llc -mtriple x86_64-pc-linux < %s | FileCheck --check-prefix=INIT-ARRAY %s
 ; RUN: llc -mtriple x86_64-unknown-freebsd < %s | FileCheck --check-prefix=INIT-ARRAY %s
 ; RUN: llc -mtriple x86_64-pc-solaris2.11 < %s | FileCheck --check-prefix=INIT-ARRAY %s
-; RUN: llc -mtriple x86_64-unknown-nacl < %s | FileCheck --check-prefix=NACL %s
 ; RUN: llc -mtriple i586-intel-elfiamcu -use-ctors < %s | FileCheck %s --check-prefix=MCU-CTORS
 ; RUN: llc -mtriple i586-intel-elfiamcu < %s | FileCheck %s --check-prefix=MCU-INIT-ARRAY
 ; RUN: llc -mtriple x86_64-win32-gnu < %s | FileCheck --check-prefix=COFF-CTOR %s
 @llvm.global_ctors = appending global [3 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* null}, { i32, void ()*, i8* } { i32 15, void ()* @g, i8* @v }, { i32, void ()*, i8* } { i32 55555, void ()* @h, i8* @v }]
 
 @v = weak_odr global i8 0
 
 define void @f() {

 ; INIT-ARRAY-NEXT:  .quad g
 ; INIT-ARRAY-NEXT:  .section  .init_array.55555,"aGw",@init_array,v,comdat
 ; INIT-ARRAY-NEXT:  .p2align  3
 ; INIT-ARRAY-NEXT:  .quad h
 ; INIT-ARRAY-NEXT:  .section  .init_array,"aw",@init_array
 ; INIT-ARRAY-NEXT:  .p2align  3
 ; INIT-ARRAY-NEXT:  .quad f
 
-; NACL:   .section  .init_array.15,"aGw",@init_array,v,comdat
-; NACL-NEXT:  .p2align  2
-; NACL-NEXT:  .long g
-; NACL-NEXT:  .section  .init_array.55555,"aGw",@init_array,v,comdat
-; NACL-NEXT:  .p2align  2
-; NACL-NEXT:  .long h
-; NACL-NEXT:  .section  .init_array,"aw",@init_array
-; NACL-NEXT:  .p2align  2
-; NACL-NEXT:  .long f
-
 ; MCU-CTORS:         .section        .ctors,"aw",@progbits
 ; MCU-INIT-ARRAY:    .section        .init_array,"aw",@init_array
 
 ; COFF-CTOR:    .section  .ctors.65520,"dw",associative,v
 ; COFF-CTOR-NEXT: .p2align  3
 ; COFF-CTOR-NEXT: .quad g
 ; COFF-CTOR-NEXT: .section  .ctors.09980,"dw",associative,v
 ; COFF-CTOR-NEXT: .p2align  3
 ; COFF-CTOR-NEXT: .quad h
 ; COFF-CTOR-NEXT: .section  .ctors,"dw"
 ; COFF-CTOR-NEXT: .p2align  3
 ; COFF-CTOR-NEXT: .quad f

llvm/test/CodeGen/X86/fast-isel-x32.ll

 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s
 
 ; Test that alloca addresses are materialized with the right size instruction.
 
 declare void @bar(i32* %arg)
 
 ; CHECK-LABEL: @foo
 define void @foo() {
   %a = alloca i32
 ; CHECK: leal {{.*}}, %edi
   call void @bar(i32* %a)
   ret void
 }

llvm/test/CodeGen/X86/frameaddr.ll

 ; RUN: llc < %s -mtriple=i686--                                | FileCheck %s --check-prefix=CHECK-32
 ; RUN: llc < %s -mtriple=i686--    -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-32
 ; RUN: llc < %s -mtriple=x86_64-pc-win32 -fast-isel | FileCheck %s --check-prefix=CHECK-W64
 ; RUN: llc < %s -mtriple=x86_64-unknown                             | FileCheck %s --check-prefix=CHECK-64
 ; RUN: llc < %s -mtriple=x86_64-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-64
 ; RUN: llc < %s -mtriple=x86_64-gnux32                    | FileCheck %s --check-prefix=CHECK-X32ABI
 ; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-X32ABI
-; RUN: llc < %s -mtriple=x86_64-nacl                    | FileCheck %s --check-prefix=CHECK-NACL64
-; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-NACL64
 
 define i8* @test1() nounwind {
 entry:
 ; CHECK-32-LABEL: test1
 ; CHECK-32:       push
 ; CHECK-32-NEXT:  movl %esp, %ebp
 ; CHECK-32-NEXT:  movl %ebp, %eax
 ; CHECK-32-NEXT:  pop

llvm/test/CodeGen/X86/lea-2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-linux          | FileCheck %s --check-prefix=X32
 ; RUN: llc < %s -mtriple=x86_64-linux        | FileCheck %s --check-prefix=X64
 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefix=X64
-; RUN: llc < %s -mtriple=x86_64-nacl         | FileCheck %s --check-prefix=X64
 
 ; The computation of %t4 should match a single lea, without using actual add instructions.
 
 define i32 @test1(i32 %A, i32 %B) {
 ; X32-LABEL: test1:
 ; X32:       # %bb.0:
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx

llvm/test/CodeGen/X86/lea-3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux        | FileCheck %s --check-prefixes=CHECK,LNX
 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefixes=CHECK,LNX32
-; RUN: llc < %s -mtriple=x86_64-nacl         | FileCheck %s --check-prefixes=CHECK,NACL
 ; RUN: llc < %s -mtriple=x86_64-win32        | FileCheck %s --check-prefixes=WIN32
 
 define i64 @test2(i64 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    leaq (,%rdi,4), %rax
 ; CHECK-NEXT:    orq %rdi, %rax
 ; CHECK-NEXT:    retq

llvm/test/CodeGen/X86/lea-4.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux        | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-nacl         | FileCheck %s
 
 define zeroext i16 @t1(i32 %on_off) nounwind {
 ; CHECK-LABEL: t1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    leal -2(%rdi,%rdi), %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq

llvm/test/CodeGen/X86/lea-5.ll

 ; test for more complicated forms of lea operands which can be generated
 ; in loop optimized cases.
 ; See also http://llvm.org/bugs/show_bug.cgi?id=20016
 
 ; RUN: llc < %s -mtriple=x86_64-linux -O2        | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -O2 | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-nacl -O2 | FileCheck %s -check-prefix=X32
 
 ; Function Attrs: nounwind readnone uwtable
 define void @foo(i32 %x, i32 %d) #0 {
 entry:
   %a = alloca [8 x i32], align 16
   br label %while.cond
 
 while.cond:                                       ; preds = %while.cond, %entry

llvm/test/CodeGen/X86/lea.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=LINUX
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefixes=WIN
 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefixes=LINUX
-; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefixes=LINUX
 
 define i32 @test1(i32 %x) nounwind {
 ; LINUX-LABEL: test1:
 ; LINUX:       # %bb.0:
 ; LINUX-NEXT:    # kill: def $edi killed $edi def $rdi
 ; LINUX-NEXT:    leal 7(,%rdi,8), %eax
 ; LINUX-NEXT:    retq
 ;

llvm/test/CodeGen/X86/x86-64-baseptr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-pc-linux -stackrealign -stack-alignment=32 < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -stackrealign -stack-alignment=32 < %s | FileCheck -check-prefix=X32ABI %s
 
-; This should run with NaCl as well ( -mtriple=x86_64-pc-nacl ) but currently doesn't due to PR22655
-
-; Make sure the correct register gets set up as the base pointer
-; This should be rbx for x64 and 64-bit NaCl and ebx for x32
-; NACL-LABEL: base
-; NACL: subq $32, %rsp
-; NACL: movq %rsp, %rbx
-
 declare i32 @helper() nounwind
 define void @base() #0 {
 ; CHECK-LABEL: base:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushq %rbp
 ; CHECK-NEXT:    movq %rsp, %rbp
 ; CHECK-NEXT:    pushq %rbx
 ; CHECK-NEXT:    andq $-32, %rsp

llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll

 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
-; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
 
 ; x32 uses %esp, %ebp as stack and frame pointers
 
 ; CHECK-LABEL: foo
 ; CHECK: pushq %rbp
 ; CHECK: movq %rsp, %rbp
 ; CHECK: movq %rdi, -8(%rbp)
 ; CHECK: popq %rbp
 ; X32ABI-LABEL: foo
 ; X32ABI: pushq %rbp
 ; X32ABI: movl %esp, %ebp
 ; X32ABI: movl %edi, -4(%ebp)
 ; X32ABI: popq %rbp
-; NACL-LABEL: foo
-; NACL: pushq %rbp
-; NACL: movq %rsp, %rbp
-; NACL: movl %edi, -4(%rbp)
-; NACL: popq %rbp
 
 
 define void @foo(i32* %a) #0 {
 entry:
   %a.addr = alloca i32*, align 4
   %b = alloca i32*, align 4
   store i32* %a, i32** %a.addr, align 4
   ret void
 }
 
 attributes #0 = { nounwind uwtable "frame-pointer"="all"}
 
 

llvm/test/MC/ARM/arm_instructions.s

 @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s \
 @ RUN:  | FileCheck %s -check-prefix=ALL
-@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7-unknown-nacl -show-encoding %s \
-@ RUN:  | FileCheck %s -check-prefix=NACL
-@ RUN: llvm-mc -mcpu=cortex-a8 -mattr=+nacl-trap -triple armv7 -show-encoding %s \
-@ RUN:  | FileCheck %s -check-prefix=NACL
 
 @ ALL: trap
 @ ALL: encoding: [0xfe,0xde,0xff,0xe7]
-@ NACL: trap
-@ NACL: encoding: [0xf0,0xde,0xfe,0xe7]
         trap
 
 @ CHECK: bx lr
 @ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
         bx lr
 
 @ CHECK: vqdmull.s32  q8, d17, d16
 @ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]

llvm/test/MC/Mips/nacl-mask.s

-# RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
-# RUN:   | llvm-objdump -d -z --no-show-raw-insn - | FileCheck %s
-
-# This test tests that address-masking sandboxing is added when given assembly
-# input.
-
-
-# Test that address-masking sandboxing is added before indirect branches and
-# returns.
-
-  .align  4
-test1:
-  .set  noreorder
-
-        jr  $a0
-        nop
-        jr  $ra
-        nop
-
-# CHECK-LABEL:   <test1>:
-
-# CHECK:         and     $4, $4, $14
-# CHECK-NEXT:    jr      $4
-
-# Check that additional nop is inserted, to align mask and jr to the next
-# bundle.
-
-# CHECK-NEXT:    nop
-# CHECK-NEXT:    nop
-
-# CHECK:         and     $ra, $ra, $14
-# CHECK-NEXT:    jr      $ra
-
-
-
-# Test that address-masking sandboxing is added before load instructions.
-
-  .align  4
-test2:
-  .set  noreorder
-
-        lb      $4, 0($1)
-        nop
-        lbu     $4, 0($2)
-        lh      $4, 0($3)
-        lhu     $1, 0($4)
-        lw      $4, 0($5)
-        lwc1    $f0, 0($6)
-        ldc1    $f2, 0($7)
-        ll      $4, 0($8)
-        lwl     $4, 0($9)
-        lwr     $4, 0($10)
-
-        lw      $4, 0($sp)
-        lw      $4, 0($t8)
-
-# CHECK-LABEL:   <test2>:
-
-# CHECK:         and     $1, $1, $15
-# CHECK-NEXT:    lb      $4, 0($1)
-
-# Check that additional nop is inserted, to align mask and load to the next
-# bundle.
-
-# CHECK:         nop
-# CHECK:         nop
-
-# CHECK:         and     $2, $2, $15
-# CHECK-NEXT:    lbu     $4, 0($2)
-
-# CHECK:         and     $3, $3, $15
-# CHECK-NEXT:    lh      $4, 0($3)
-
-# CHECK:         and     $4, $4, $15
-# CHECK-NEXT:    lhu     $1, 0($4)
-
-# CHECK:         and     $5, $5, $15
-# CHECK-NEXT:    lw      $4, 0($5)
-
-# CHECK:         and     $6, $6, $15
-# CHECK-NEXT:    lwc1    $f0, 0($6)
-
-# CHECK:         and     $7, $7, $15
-# CHECK-NEXT:    ldc1    $f2, 0($7)
-
-# CHECK:         and     $8, $8, $15
-# CHECK-NEXT:    ll      $4, 0($8)
-
-# CHECK:         and     $9, $9, $15
-# CHECK-NEXT:    lwl     $4, 0($9)
-
-# CHECK:         and     $10, $10, $15
-# CHECK-NEXT:    lwr     $4, 0($10)
-
-
-# Check that loads where base register is $sp or $t8 (thread pointer register)
-# are not masked.
-
-# CHECK-NOT:     and
-# CHECK:         lw      $4, 0($sp)
-# CHECK-NOT:     and
-# CHECK:         lw      $4, 0($24)
-
-
-
-# Test that address-masking sandboxing is added before store instructions.
-
-  .align  4
-test3:
-  .set  noreorder
-
-        sb      $4, 0($1)
-        nop
-        sh      $4, 0($2)
-        sw      $4, 0($3)
-        swc1    $f0, 0($4)
-        sdc1    $f2, 0($5)
-        swl     $4, 0($6)
-        swr     $4, 0($7)
-        sc      $4, 0($8)
-
-        sw      $4, 0($sp)
-        sw      $4, 0($t8)
-
-# CHECK-LABEL:   <test3>:
-
-# CHECK:         and     $1, $1, $15
-# CHECK-NEXT:    sb      $4, 0($1)
-
-# Check that additional nop is inserted, to align mask and store to the next
-# bundle.
-
-# CHECK:         nop
-# CHECK:         nop
-
-# CHECK:         and     $2, $2, $15
-# CHECK-NEXT:    sh      $4, 0($2)
-
-# CHECK:         and     $3, $3, $15
-# CHECK-NEXT:    sw      $4, 0($3)
-
-# CHECK:         and     $4, $4, $15
-# CHECK-NEXT:    swc1    $f0, 0($4)
-
-# CHECK:         and     $5, $5, $15
-# CHECK-NEXT:    sdc1    $f2, 0($5)
-
-# CHECK:         and     $6, $6, $15
-# CHECK-NEXT:    swl     $4, 0($6)
-
-# CHECK:         and     $7, $7, $15
-# CHECK-NEXT:    swr     $4, 0($7)
-
-# CHECK:         and     $8, $8, $15
-# CHECK-NEXT:    sc      $4, 0($8)
-
-
-# Check that stores where base register is $sp or $t8 (thread pointer register)
-# are not masked.
-
-# CHECK-NOT:     and
-# CHECK:         sw      $4, 0($sp)
-# CHECK-NOT:     and
-# CHECK:         sw      $4, 0($24)
-
-
-
-# Test that address-masking sandboxing is added after instructions that change
-# stack pointer.
-
-  .align  4
-test4:
-  .set  noreorder
-
-        addiu   $sp, $sp, 24
-        nop
-        addu    $sp, $sp, $1
-        lw      $sp, 0($2)
-        lw      $sp, 123($sp)
-        sw      $sp, 123($sp)
-
-# CHECK-LABEL:   <test4>:
-
-# CHECK:         addiu   $sp, $sp, 24
-# CHECK-NEXT:    and     $sp, $sp, $15
-
-# Check that additional nop is inserted, to align instruction and mask to the
-# next bundle.
-
-# CHECK:         nop
-# CHECK:         nop
-
-# CHECK:         addu    $sp, $sp, $1
-# CHECK-NEXT:    and     $sp, $sp, $15
-
-# Since we next check sandboxing sequence which consists of 3 instructions,
-# check that 2 additional nops are inserted, to align it to the next bundle.
-
-# CHECK:         nop
-# CHECK:         nop
-
-
-# Check that for instructions that change stack-pointer and load from memory
-# masks are added before and after the instruction.
-
-# CHECK:         and     $2, $2, $15
-# CHECK-NEXT:    lw      $sp, 0($2)
-# CHECK-NEXT:    and     $sp, $sp, $15
-
-# For loads where $sp is destination and base, check that mask is added after
-# but not before.
-
-# CHECK-NOT:     and
-# CHECK:         lw      $sp, 123($sp)
-# CHECK-NEXT:    and     $sp, $sp, $15
-
-# For stores where $sp is destination and base, check that mask is added neither
-# before nor after.
-
-# CHECK-NOT:     and
-# CHECK:         sw      $sp, 123($sp)
-# CHECK-NOT:     and
-
-
-
-# Test that call + branch delay is aligned at bundle end.  Test that mask is
-# added before indirect calls.
-
-  .align  4
-test5:
-  .set  noreorder
-
-        jal func1
-        addiu $4, $zero, 1
-
-        nop
-        bal func2
-        addiu $4, $zero, 2
-
-        nop
-        nop
-        bltzal $t1, func3
-        addiu $4, $zero, 3
-
-        nop
-        nop
-        nop
-        bgezal $t2, func4
-        addiu $4, $zero, 4
-
-        jalr $t9
-        addiu $4, $zero, 5
-
-
-# CHECK:             nop
-# CHECK-NEXT:        nop
-# CHECK-LABEL:       <test5>:
-# CHECK-NEXT:        jal
-# CHECK-NEXT:        addiu   $4, $zero, 1
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        bal
-# CHECK-NEXT:        addiu   $4, $zero, 2
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        bltzal
-# CHECK-NEXT:        addiu   $4, $zero, 3
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        bgezal
-# CHECK-NEXT:        addiu   $4, $zero, 4
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        and     $25, $25, $14
-# CHECK-NEXT:        jalr    $25
-# CHECK-NEXT:        addiu   $4, $zero, 5
-
-
-
-# Test that we can put non-dangerous loads and stores in branch delay slot.
-
-  .align  4
-test6:
-  .set  noreorder
-
-        jal func1
-        sw      $4, 0($sp)
-
-        bal func2
-        lw      $5, 0($t8)
-
-        jalr $t9
-        sw      $sp, 0($sp)
-
-
-
-# CHECK:             nop
-# CHECK-NEXT:        nop
-# CHECK-LABEL:       <test6>:
-# CHECK-NEXT:        jal
-# CHECK-NEXT:        sw      $4, 0($sp)
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        bal
-# CHECK-NEXT:        lw      $5, 0($24)
-
-# CHECK-NEXT:        nop
-# CHECK-NEXT:        and     $25, $25, $14
-# CHECK-NEXT:        jalr
-# CHECK-NEXT:        sw      $sp, 0($sp)

llvm/test/MC/X86/AlignedBundling/labeloffset.s

-# RUN: llvm-mc -triple=i686-linux -filetype=obj %s -o - | \
-# RUN: llvm-objdump -d --no-show-raw-insn -r - | FileCheck %s
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \
-# RUN: llvm-objdump -d --no-show-raw-insn -r - | FileCheck %s
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \
-# RUN: llvm-objdump -d --no-show-raw-insn -r - | FileCheck %s
-
-        .bundle_align_mode 5
-        .text
-        .globl  main
-        .align  32, 0x90
-        .type   main,@function
-main:                                   # @main
-# CHECK-LABEL: <main>:
-# Call + pop sequence for determining the PIC base.
-        .bundle_lock align_to_end
-        calll   .L0$pb
-        .bundle_unlock
-.L0$pb:
-        popl    %eax
-# CHECK: 20: popl
-# 26 bytes of instructions between the pop and the use of the pic base symbol.
-        movl    $3, 2(%ebx, %ebx)
-        movl    $3, 2(%ebx, %ebx)
-        movl    $3, 2(%ebx, %ebx)
-        hlt
-        hlt
-# CHECK: nop
-.Ltmp0:
-        addl    (.Ltmp0-.L0$pb), %eax
-# The addl has bundle padding to push it from 0x3b to 0x40.
-# The difference between the labels should be 0x20 (0x40-0x20) not 0x1b
-# (0x3b-0x20)
-# CHECK: 40: addl 32, %eax
-        popl    %ecx
-        jmp     *%ecx
-
-
-# Also make sure it works with a non-relaxable instruction (cmp vs add)
-# and for 2 adjacent labels that both point to the correct instruction
-        .section .text.bar, "ax"
-        .globl  bar
-        .align  32, 0x90
-        .type   bar,@function
-bar:
-# CHECK-LABEL: bar:
-        .bundle_lock align_to_end
-        calll   .L1$pb
-        .bundle_unlock
-.L1$pb:
-        popl %eax
-# CHECK: 20: popl
-# 26 bytes of instructions between the pop and the use of the pic base symbol.
-        movl    $3, 2(%ebx, %ebx)
-        movl    $3, 2(%ebx, %ebx)
-        movl    $3, 2(%ebx, %ebx)
-        hlt
-        hlt
-# CHECK: nop
-.Ltmp1:
-.Ltmp2:
-        cmpl    %eax, .Ltmp1
-# CHECK: 40: cmpl %eax, 64
-        cmpl     %eax, (.Ltmp2-.L1$pb)
-# CHECK: 46: cmpl %eax, 32
-        popl    %ecx
-        jmp *%ecx
-
-
-# Switch sections in the middle of a function
-        .section .text.foo, "ax"
-        .globl  foo
-        .align  32, 0x90
-        .type   foo,@function
-# CHECK-LABEL: foo:
-foo:
-        inc %eax
-tmp3:
-        .rodata
-        .type   obj,@object
-        .comm   obj,4,4
-        .section .text.foo
-        inc %eax
-# CHECK: <tmp3>:
-# CHECK-NEXT: 1: incl

llvm/test/MC/X86/AlignedBundling/rodata-section.s

-# RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - \
-# RUN:    | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - \
-# RUN:    | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
-
-  .bundle_align_mode 5
-  .text
-  .align  32, 0x90
-# CHECK: 0: movl $14, 8(%esp)
-  movl  $.str2, 8(%esp)
-# CHECK: 8: movl $7, 4(%esp)
-  movl  $.str1, 4(%esp)
-# CHECK: 10: movl $0, (%esp)
-  movl  $.str, (%esp)
-
-  .type .str,@object
-  .section  .rodata,"a",@progbits
-.str:
-  .asciz  "hello1"
-  .size .str, 7
-
-  .type .str1,@object
-.str1:
-  .asciz  "hello2"
-  .size .str1, 7
-
-  .type .str2,@object
-.str2:
-  .asciz  "hello3"
-  .size .str2, 7

llvm/unittests/ADT/TripleTest.cpp

EXPECT_EQ("i686-pc-windows-elf",
             Triple::normalize("i686-pc-windows-elf-elf"));
 
   EXPECT_TRUE(Triple("x86_64-pc-win32").isWindowsMSVCEnvironment());
 }
 
 TEST(TripleTest, getARMCPUForArch) {
   // Platform specific defaults.
   {
-    llvm::Triple Triple("arm--nacl");
-    EXPECT_EQ("cortex-a8", Triple.getARMCPUForArch());
-  }
-  {
     llvm::Triple Triple("arm--openbsd");
     EXPECT_EQ("cortex-a8", Triple.getARMCPUForArch());
   }
   {
     llvm::Triple Triple("armv6-unknown-freebsd");
     EXPECT_EQ("arm1176jzf-s", Triple.getARMCPUForArch());
   }
   {

llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn

sources = [
     "Targets/AArch64.cpp",
     "Targets/AMDGPU.cpp",
     "Targets/ARC.cpp",
     "Targets/ARM.cpp",
     "Targets/AVR.cpp",
     "Targets/BPF.cpp",
     "Targets/Hexagon.cpp",
     "Targets/Lanai.cpp",
-    "Targets/Le64.cpp",
     "Targets/MSP430.cpp",
     "Targets/Mips.cpp",
     "Targets/NVPTX.cpp",
     "Targets/OSTargets.cpp",
-    "Targets/PNaCl.cpp",
     "Targets/PPC.cpp",
     "Targets/RISCV.cpp",
     "Targets/SPIR.cpp",
     "Targets/Sparc.cpp",
     "Targets/SystemZ.cpp",
     "Targets/TCE.cpp",
     "Targets/WebAssembly.cpp",
     "Targets/X86.cpp",

llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn

sources = [
     "ToolChains/InterfaceStubs.cpp",
     "ToolChains/Linux.cpp",
     "ToolChains/MSP430.cpp",
     "ToolChains/MSVC.cpp",
     "ToolChains/MinGW.cpp",
     "ToolChains/Minix.cpp",
     "ToolChains/MipsLinux.cpp",
     "ToolChains/Myriad.cpp",
-    "ToolChains/NaCl.cpp",
     "ToolChains/NetBSD.cpp",
     "ToolChains/OpenBSD.cpp",
     "ToolChains/PPCLinux.cpp",
     "ToolChains/PS4CPU.cpp",
     "ToolChains/RISCVToolchain.cpp",
     "ToolChains/Solaris.cpp",
     "ToolChains/TCE.cpp",
     "ToolChains/WebAssembly.cpp",
     "ToolChains/XCore.cpp",
     "Types.cpp",
     "XRayArgs.cpp",
   ]
 }

llvm/utils/gn/secondary/llvm/lib/Target/Mips/MCTargetDesc/BUILD.gn

sources = [
     "MipsAsmBackend.cpp",
     "MipsELFObjectWriter.cpp",
     "MipsELFStreamer.cpp",
     "MipsInstPrinter.cpp",
     "MipsMCAsmInfo.cpp",
     "MipsMCCodeEmitter.cpp",
     "MipsMCExpr.cpp",
     "MipsMCTargetDesc.cpp",
-    "MipsNaClELFStreamer.cpp",
     "MipsOptionRecord.cpp",
     "MipsTargetStreamer.cpp",
   ]
 }