[MC] Adding MCContext parameter to MCAsmBackend::relaxInstruction

[DavidFerencSzabo]

Summary

The motivation is to be able to relax out of range conditional branches when the input is assembly. The existing pass not works at this level. To achieve this the conditional branch must be relaxed into an instructions pair, which then put into a BUNDLE. The change allows targets to create MCInst objects using MCContext object inside the relaxation function.

[MaskRay]

which then put into a BUNDLE.

Does the BUNDLE here mean .bundle_{align_mode,lock,unlock}? (something I want to get rid of (D78441))

[DavidFerencSzabo]

@MaskRay No. Its a Machine Instruction Bundle. (https://lists.llvm.org/pipermail/llvm-dev/2011-December/045851.html).

But reading this I stumbled upon this line

There is no need to add the equivalent of MI bundle to MCInst. A MI bundle should be concatenated into a single MCInst by storing opcodes as integer operands. e.g.

This whole change might be unnecessary and the idiomatic way to do this is concatenation?

[MaskRay]

In D95375#2520592, @DavidFerencSzabo wrote:

@MaskRay No. Its a Machine Instruction Bundle. (https://lists.llvm.org/pipermail/llvm-dev/2011-December/045851.html).

But reading this I stumbled upon this line

OK. Currently MCRelaxableFragment encodes just one MCInst. Do you intend to loose the requirement?

[gargaroff]

In D95375#2520987, @MaskRay wrote:

OK. Currently MCRelaxableFragment encodes just one MCInst. Do you intend to loose the requirement?

Well, not sure. What we much rather would like to know is what the intended way to implement this correctly is. Apart from Hexagon, I am not aware of any other target that implements this relaxation. Hexagon does use BUNDLE, but in order to get the required MCContext, they have to resort to some hacky implementation leveraging fixupNeedsRelaxation IIRC.

We could implement this using a pseudo instruction, that we then expand in our target's MCCodeEmitter. But we thought that maybe there is no context available in relaxInstructions, because no other target implements this yet, so instead of working around this limitation using a pseudo, we should simply make the context available.

We really are unsure what the intended way should be, so we would definitely like some feedback here.

[DavidFerencSzabo]

@MaskRay I added you as a reviewer. Also I would like to ask you to add more people if you know any, who might should have an eye on this.

llvm/include/llvm/MC/MCAsmBackend.h

 //===- llvm/MC/MCAsmBackend.h - MC Asm Backend ------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCASMBACKEND_H
 #define LLVM_MC_MCASMBACKEND_H
 
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/Optional.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCFragment.h"
 #include "llvm/Support/Endian.h"
 #include <cstdint>
 
 namespace llvm {
 
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                     const MCRelaxableFragment *DF,
                                     const MCAsmLayout &Layout) const = 0;
 
   /// Relax the instruction in the given fragment to the next wider instruction.
   ///
   /// \param [out] Inst The instruction to relax, which is also the relaxed
   /// instruction.
   /// \param STI the subtarget information for the associated instruction.
-  virtual void relaxInstruction(MCInst &Inst,
-                                const MCSubtargetInfo &STI) const {};
+  virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                                MCContext &Ctx) const {};
 
   /// @}
 
   /// Returns the minimum size of a nop in bytes on this target. The assembler
   /// will use this to emit excess padding in situations where the padding
   /// required for simple alignment would be less than the minimum nop size.
   ///
   virtual unsigned getMinimumNopSize() const { return 1; }

llvm/include/llvm/MCA/CodeEmitter.h

 namespace llvm {
 namespace mca {
 
 /// A utility class used to compute instruction encodings for a code region.
 ///
 /// It provides a simple API to compute and return instruction encodings as
 /// strings. Encodings are cached internally for later usage.
 class CodeEmitter {
+  MCContext &Ctx;
   const MCSubtargetInfo &STI;
   const MCAsmBackend &MAB;
   const MCCodeEmitter &MCE;
 
   SmallString<256> Code;
   raw_svector_ostream VecOS;
   ArrayRef<MCInst> Sequence;
 
   // An EncodingInfo pair stores <base, length> information.  Base (i.e. first)
   // is an index to the `Code`. Length (i.e. second) is the encoding size.
   using EncodingInfo = std::pair<unsigned, unsigned>;
 
   // A cache of encodings.
   SmallVector<EncodingInfo, 16> Encodings;
 
   EncodingInfo getOrCreateEncodingInfo(unsigned MCID);
 
 public:
-  CodeEmitter(const MCSubtargetInfo &ST, const MCAsmBackend &AB,
+  CodeEmitter(MCContext &C, const MCSubtargetInfo &ST, const MCAsmBackend &AB,
               const MCCodeEmitter &CE, ArrayRef<MCInst> S)
-      : STI(ST), MAB(AB), MCE(CE), VecOS(Code), Sequence(S),
+      : Ctx(C), STI(ST), MAB(AB), MCE(CE), VecOS(Code), Sequence(S),
         Encodings(S.size()) {}
 
   StringRef getEncoding(unsigned MCID) {
     EncodingInfo EI = getOrCreateEncodingInfo(MCID);
     return StringRef(&Code[EI.first], EI.second);
   }
 };
 
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_CODEEMITTER_H

llvm/lib/MC/MCAssembler.cpp

bool MCAssembler::relaxInstruction(MCAsmLayout &Layout,
   ++stats::RelaxedInstructions;
 
   // FIXME-PERF: We could immediately lower out instructions if we can tell
   // they are fully resolved, to avoid retesting on later passes.
 
   // Relax the fragment.
 
   MCInst Relaxed = F.getInst();
-  getBackend().relaxInstruction(Relaxed, *F.getSubtargetInfo());
+  getBackend().relaxInstruction(Relaxed, *F.getSubtargetInfo(),
+                                Layout.getAssembler().getContext());
 
   // Encode the new instruction.
   //
   // FIXME-PERF: If it matters, we could let the target do this. It can
   // probably do so more efficiently in many cases.
   SmallVector<MCFixup, 4> Fixups;
   SmallString<256> Code;
   raw_svector_ostream VecOS(Code);

llvm/lib/MC/MCObjectStreamer.cpp

void MCObjectStreamer::emitInstructionImpl(const MCInst &Inst,
   // - The RelaxAll flag was passed
   // - Bundling is enabled and this instruction is inside a bundle-locked
   //   group. We want to emit all such instructions into the same data
   //   fragment.
   if (Assembler.getRelaxAll() ||
       (Assembler.isBundlingEnabled() && Sec->isBundleLocked())) {
     MCInst Relaxed = Inst;
     while (Backend.mayNeedRelaxation(Relaxed, STI))
-      Backend.relaxInstruction(Relaxed, STI);
+      Backend.relaxInstruction(Relaxed, STI, Assembler.getContext());
     emitInstToData(Relaxed, STI);
     return;
   }
 
   // Otherwise emit to a separate fragment.
   emitInstToFragment(Inst, STI);
 }
 

llvm/lib/MCA/CodeEmitter.cpp

CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) {
   EncodingInfo &EI = Encodings[MCID];
   if (EI.second)
     return EI;
 
   SmallVector<llvm::MCFixup, 2> Fixups;
   const MCInst &Inst = Sequence[MCID];
   MCInst Relaxed(Sequence[MCID]);
   if (MAB.mayNeedRelaxation(Inst, STI))
-    MAB.relaxInstruction(Relaxed, STI);
+    MAB.relaxInstruction(Relaxed, STI, Ctx);
 
   EI.first = Code.size();
   MCE.encodeInstruction(Relaxed, VecOS, Fixups, STI);
   EI.second = Code.size() - EI.first;
   return EI;
 }
 
 } // namespace mca
 } // namespace llvm

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

public:
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override;
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override;
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
 
   void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
 
   unsigned getPointerSize() const { return 8; }
 
   unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
 
bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
   // FIXME:  This isn't correct for AArch64. Just moving the "generic" logic
   // into the targets for now.
   //
   // Relax if the value is too big for a (signed) i8.
   return int64_t(Value) != int64_t(int8_t(Value));
 }
 
 void AArch64AsmBackend::relaxInstruction(MCInst &Inst,
-                                         const MCSubtargetInfo &STI) const {
+                                         const MCSubtargetInfo &STI,
+                                         MCContext &Ctx) const {
   llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
 }
 
 bool AArch64AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
   // If the count is not 4-byte aligned, we must be writing data into the text
   // section (otherwise we have unaligned instructions, and thus have far
   // bigger problems), so just write zeros instead.
   OS.write_zeros(Count % 4);

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

public:
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override;
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override;
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
 
   unsigned getMinimumNopSize() const override;
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 };
 
 } //End anonymous namespace
 
 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
-                                        const MCSubtargetInfo &STI) const {
+                                        const MCSubtargetInfo &STI,
+                                        MCContext &Ctx) const {
   MCInst Res;
   unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
   Res.setOpcode(RelaxedOpcode);
   Res.addOperand(Inst.getOperand(0));
   Inst = std::move(Res);
   return;
 }
 

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h

public:
 
   const char *reasonForFixupRelaxation(const MCFixup &Fixup,
                                        uint64_t Value) const;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override;
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override;
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
 
   void handleAssemblerFlag(MCAssemblerFlag Flag) override;
 
   unsigned getPointerSize() const { return 4; }
   bool isThumb() const { return isThumbMode; }
   void setIsThumb(bool it) { isThumbMode = it; }
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

 }
 
 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                          const MCRelaxableFragment *DF,
                                          const MCAsmLayout &Layout) const {
   return reasonForFixupRelaxation(Fixup, Value);
 }
 
-void ARMAsmBackend::relaxInstruction(MCInst &Inst,
-                                     const MCSubtargetInfo &STI) const {
+void ARMAsmBackend::relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                                     MCContext &Ctx) const {
   unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
 
   // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
   if (RelaxedOp == Inst.getOpcode()) {
     SmallString<256> Tmp;
     raw_svector_ostream OS(Tmp);
     Inst.dump_pretty(OS);
     OS << "\n";

llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h

public:
   unsigned int getNumFixupKinds() const override;
   void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                   const MCValue &Target, MutableArrayRef<char> Data,
                   uint64_t Value, bool IsResolved,
                   const MCSubtargetInfo *STI) const override;
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override;
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override;
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
   std::unique_ptr<MCObjectTargetWriter>
   createObjectTargetWriter() const override;
 };
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H

llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp

 //===-- CSKYAsmBackend.cpp - CSKY Assembler Backend -----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "CSKYAsmBackend.h"
 #include "MCTargetDesc/CSKYMCTargetDesc.h"
 #include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "csky-asmbackend"

 }
 
 bool CSKYAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                           const MCRelaxableFragment *DF,
                                           const MCAsmLayout &Layout) const {
   return false;
 }
 
-void CSKYAsmBackend::relaxInstruction(MCInst &Inst,
-                                      const MCSubtargetInfo &STI) const {
+void CSKYAsmBackend::relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                                      MCContext &Ctx) const {
   llvm_unreachable("CSKYAsmBackend::relaxInstruction() unimplemented");
 }
 
 bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
   if (Count % 2)
     return false;
 
   // MOV32 r0, r0

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

public:
 
   /// Simple predicate for targets where !Resolved implies requiring relaxation
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
   }
 
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override {
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override {
     assert(HexagonMCInstrInfo::isBundle(Inst) &&
            "Hexagon relaxInstruction only works on bundles");
 
     MCInst Res;
     Res.setOpcode(Hexagon::BUNDLE);
     Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm()));
     // Copy the results into the bundle.
     bool Update = false;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup,
                             uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override {
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override {
     // FIXME.
     llvm_unreachable("relaxInstruction() unimplemented");
   }
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
     uint64_t NumNops = Count / 4;
     for (uint64_t i = 0; i != NumNops; ++i)
       support::endian::write<uint32_t>(OS, 0x60000000, Endian);

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

public:
   Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
 
   const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
   unsigned getRelaxedOpcode(unsigned Op) const;
 
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override;
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override;
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
 
   const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
 };
 }
 
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

case RISCV::fixup_riscv_rvc_branch:
     return Offset > 254 || Offset < -256;
   case RISCV::fixup_riscv_rvc_jump:
     // For compressed jump instructions the immediate must be
     // in the range [-2048, 2046].
     return Offset > 2046 || Offset < -2048;
   }
 }
 
-void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
-                                       const MCSubtargetInfo &STI) const {
+void RISCVAsmBackend::relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                                       MCContext &Ctx) const {
   // TODO: replace this with call to auto generated uncompressinstr() function.
   MCInst Res;
   switch (Inst.getOpcode()) {
   default:
     llvm_unreachable("Opcode not expected!");
   case RISCV::C_BEQZ:
     // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
     Res.setOpcode(RISCV::BEQ);

llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

public:
     bool fixupNeedsRelaxation(const MCFixup &Fixup,
                               uint64_t Value,
                               const MCRelaxableFragment *DF,
                               const MCAsmLayout &Layout) const override {
       // FIXME.
       llvm_unreachable("fixupNeedsRelaxation() unimplemented");
       return false;
     }
-    void relaxInstruction(MCInst &Inst,
-                          const MCSubtargetInfo &STI) const override {
+    void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                          MCContext &Ctx) const override {
       // FIXME.
       llvm_unreachable("relaxInstruction() unimplemented");
     }
 
     bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
       // Cannot emit NOP with size not multiple of 32 bits.
       if (Count % 4 != 0)
         return false;

llvm/lib/Target/VE/MCTargetDesc/VEAsmBackend.cpp

 //===-- VEAsmBackend.cpp - VE Assembler Backend ---------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/VEFixupKinds.h"
 #include "MCTargetDesc/VEMCTargetDesc.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCELFObjectWriter.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCValue.h"
public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override {
     // Not implemented yet.  For example, if we have a branch with
     // lager than SIMM32 immediate value, we want to relaxation such
     // branch instructions.
     return false;
   }
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override {
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override {
     // Aurora VE doesn't support relaxInstruction yet.
     llvm_unreachable("relaxInstruction() should not be called");
   }
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override {
     if ((Count % 8) != 0)
       return false;
 

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

public:
 
   bool mayNeedRelaxation(const MCInst &Inst,
                          const MCSubtargetInfo &STI) const override;
 
   bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                             const MCRelaxableFragment *DF,
                             const MCAsmLayout &Layout) const override;
 
-  void relaxInstruction(MCInst &Inst,
-                        const MCSubtargetInfo &STI) const override;
+  void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                        MCContext &Ctx) const override;
 
   bool padInstructionViaRelaxation(MCRelaxableFragment &RF,
-                                   MCCodeEmitter &Emitter,
+                                   const MCAssembler &Asm,
                                    unsigned &RemainingSize) const;
 
-  bool padInstructionViaPrefix(MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
+  bool padInstructionViaPrefix(MCRelaxableFragment &RF, const MCAssembler &Asm,
                                unsigned &RemainingSize) const;
 
-  bool padInstructionEncoding(MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
+  bool padInstructionEncoding(MCRelaxableFragment &RF, const MCAssembler &Asm,
                               unsigned &RemainingSize) const;
 
   void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const override;
 
   unsigned getMaximumNopSize() const override;
 
   bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
 };
bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
                                          const MCRelaxableFragment *DF,
                                          const MCAsmLayout &Layout) const {
   // Relax if the value is too big for a (signed) i8.
   return !isInt<8>(Value);
 }
 
 // FIXME: Can tblgen help at all here to verify there aren't other instructions
 // we can relax?
-void X86AsmBackend::relaxInstruction(MCInst &Inst,
-                                     const MCSubtargetInfo &STI) const {
+void X86AsmBackend::relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI,
+                                     MCContext &Ctx) const {
   // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
   bool Is16BitMode = STI.getFeatureBits()[X86::Mode16Bit];
   unsigned RelaxedOp = getRelaxedOpcode(Inst, Is16BitMode);
 
   if (RelaxedOp == Inst.getOpcode()) {
     SmallString<256> Tmp;
     raw_svector_ostream OS(Tmp);
     Inst.dump_pretty(OS);

 static bool isFullyRelaxed(const MCRelaxableFragment &RF) {
   auto &Inst = RF.getInst();
   auto &STI = *RF.getSubtargetInfo();
   bool Is16BitMode = STI.getFeatureBits()[X86::Mode16Bit];
   return getRelaxedOpcode(Inst, Is16BitMode) == Inst.getOpcode();
 }
 
 bool X86AsmBackend::padInstructionViaPrefix(MCRelaxableFragment &RF,
-                                            MCCodeEmitter &Emitter,
+                                            const MCAssembler &Asm,
                                             unsigned &RemainingSize) const {
   if (!RF.getAllowAutoPadding())
     return false;
   // If the instruction isn't fully relaxed, shifting it around might require a
   // larger value for one of the fixups then can be encoded.  The outer loop
   // will also catch this before moving to the next instruction, but we need to
   // prevent padding this single instruction as well.
   if (!isFullyRelaxed(RF))
     return false;
 
   const unsigned OldSize = RF.getContents().size();
   if (OldSize == 15)
     return false;
 
   const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
   const unsigned RemainingPrefixSize = [&]() -> unsigned {
     SmallString<15> Code;
     raw_svector_ostream VecOS(Code);
-    Emitter.emitPrefix(RF.getInst(), VecOS, STI);
+    Asm.getEmitter().emitPrefix(RF.getInst(), VecOS, STI);
     assert(Code.size() < 15 && "The number of prefixes must be less than 15.");
 
     // TODO: It turns out we need a decent amount of plumbing for the target
     // specific bits to determine number of prefixes its safe to add.  Various
     // targets (older chips mostly, but also Atom family) encounter decoder
     // stalls with too many prefixes.  For testing purposes, we set the value
     // externally for the moment.
     unsigned ExistingPrefixSize = Code.size();
for (auto &F : RF.getFixups()) {
     F.setOffset(F.getOffset() + PrefixBytesToAdd);
   }
 
   RemainingSize -= PrefixBytesToAdd;
   return true;
 }
 
 bool X86AsmBackend::padInstructionViaRelaxation(MCRelaxableFragment &RF,
-                                                MCCodeEmitter &Emitter,
+                                                const MCAssembler &Asm,
                                                 unsigned &RemainingSize) const {
   if (isFullyRelaxed(RF))
     // TODO: There are lots of other tricks we could apply for increasing
     // encoding size without impacting performance.
     return false;
 
   MCInst Relaxed = RF.getInst();
-  relaxInstruction(Relaxed, *RF.getSubtargetInfo());
+  relaxInstruction(Relaxed, *RF.getSubtargetInfo(), Asm.getContext());
 
   SmallVector<MCFixup, 4> Fixups;
   SmallString<15> Code;
   raw_svector_ostream VecOS(Code);
-  Emitter.encodeInstruction(Relaxed, VecOS, Fixups, *RF.getSubtargetInfo());
+  Asm.getEmitter().encodeInstruction(Relaxed, VecOS, Fixups,
+                                     *RF.getSubtargetInfo());
   const unsigned OldSize = RF.getContents().size();
   const unsigned NewSize = Code.size();
   assert(NewSize >= OldSize && "size decrease during relaxation?");
   unsigned Delta = NewSize - OldSize;
   if (Delta > RemainingSize)
     return false;
   RF.setInst(Relaxed);
   RF.getContents() = Code;
   RF.getFixups() = Fixups;
   RemainingSize -= Delta;
   return true;
 }
 
 bool X86AsmBackend::padInstructionEncoding(MCRelaxableFragment &RF,
-                                           MCCodeEmitter &Emitter,
+                                           const MCAssembler &Asm,
                                            unsigned &RemainingSize) const {
   bool Changed = false;
   if (RemainingSize != 0)
-    Changed |= padInstructionViaRelaxation(RF, Emitter, RemainingSize);
+    Changed |= padInstructionViaRelaxation(RF, Asm, RemainingSize);
   if (RemainingSize != 0)
-    Changed |= padInstructionViaPrefix(RF, Emitter, RemainingSize);
+    Changed |= padInstructionViaPrefix(RF, Asm, RemainingSize);
   return Changed;
 }
 
 void X86AsmBackend::finishLayout(MCAssembler const &Asm,
                                  MCAsmLayout &Layout) const {
   // See if we can further relax some instructions to cut down on the number of
   // nop bytes required for code alignment.  The actual win is in reducing
   // instruction count, not number of bytes.  Modern X86-64 can easily end up
#endif
       // particular instructions over others, we can adjust.
       MCFragment *FirstChangedFragment = nullptr;
       unsigned RemainingSize = OrigSize;
       while (!Relaxable.empty() && RemainingSize != 0) {
         auto &RF = *Relaxable.pop_back_val();
         // Give the backend a chance to play any tricks it wishes to increase
         // the encoding size of the given instruction.  Target independent code
         // will try further relaxation, but target's may play further tricks.
-        if (padInstructionEncoding(RF, Asm.getEmitter(), RemainingSize))
+        if (padInstructionEncoding(RF, Asm, RemainingSize))
           FirstChangedFragment = &RF;
 
         // If we have an instruction which hasn't been fully relaxed, we can't
         // skip past it and insert bytes before it.  Changing its starting
         // offset might require a larger negative offset than it can encode.
         // We don't need to worry about larger positive offsets as none of the
         // possible offsets between this and our align are visible, and the
         // ones afterwards aren't changing.

llvm/tools/llvm-mca/llvm-mca.cpp

if (Region->startLoc().isValid() || Region->endLoc().isValid()) {
       StringRef Desc = Region->getDescription();
       if (!Desc.empty())
         TOF->os() << " - " << Desc;
       TOF->os() << "\n\n";
     }
 
     // Lower the MCInst sequence into an mca::Instruction sequence.
     ArrayRef<MCInst> Insts = Region->getInstructions();
-    mca::CodeEmitter CE(*STI, *MAB, *MCE, Insts);
+    mca::CodeEmitter CE(Ctx, *STI, *MAB, *MCE, Insts);
     std::vector<std::unique_ptr<mca::Instruction>> LoweredSequence;
     for (const MCInst &MCI : Insts) {
       Expected<std::unique_ptr<mca::Instruction>> Inst =
           IB.createInstruction(MCI);
       if (!Inst) {
         if (auto NewE = handleErrors(
                 Inst.takeError(),
                 [&IP, &STI](const mca::InstructionError<MCInst> &IE) {