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[DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)
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Authored by RKSimon on Apr 9 2020, 7:20 AM.

Details

Summary

This patch enables us to peek through the shifted value if we don't demand all the bits/elts.

This is another step towards removing SelectionDAG::GetDemandedBits and just using TargetLowering::SimplifyMultipleUseDemandedBits.

There's a number of regressions that I'm still investigating, notably:

ARM's UXTB matching code
DAGCombiner::MatchRotate is struggling as it only matches with legal types + operations
X86 ends up splitting a funnel shift from another shift/lea

There a few cases where we end up with extra register moves which I think we can accept in exchange for the increased ILP.

Diff Detail

Unit TestsFailed

TimeTest
50 msx64 windows > Clang.SemaCXX::vla.cpp
Script: -- : 'RUN: at line 1'; c:\ws\w32-1\llvm-project\premerge-checks\build\bin\clang.exe -cc1 -internal-isystem c:\ws\w32-1\llvm-project\premerge-checks\build\lib\clang\12.0.0\include -nostdsysteminc -verify C:\ws\w32-1\llvm-project\premerge-checks\clang\test\SemaCXX\vla.cpp

Event Timeline

RKSimon created this revision.Apr 9 2020, 7:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 9 2020, 7:20 AM
RKSimon added a subscriber: foad.Apr 9 2020, 8:20 AM
RKSimon added inline comments.
llvm/test/CodeGen/AMDGPU/trunc-combine.ll
148

@arsenm @foad Not sure if pulling out the immediate is a good idea or not - shouldn't a u16 immediate be cheap?

arsenm added inline comments.Apr 9 2020, 9:26 AM
llvm/test/CodeGen/AMDGPU/trunc-combine.ll
148

This is worse. Integer constants -16 to 64 and a handful of FP values are free, but 0xffff is not so it requires materialization.

RKSimon planned changes to this revision.Jun 22 2020, 12:15 PM
RKSimon planned changes to this revision.Aug 2 2020, 10:22 AM

still looking at the remaining regressions

RKSimon planned changes to this revision.Sep 9 2020, 8:57 AM
RKSimon updated this revision to Diff 309539.Dec 4 2020, 7:57 AM
RKSimon edited the summary of this revision. (Show Details)

rebase

yubing added a subscriber: yubing.Dec 7 2020, 5:04 AM
RKSimon added inline comments.Jan 26 2021, 4:25 AM
llvm/test/CodeGen/RISCV/rv64Zbp.ll
1105

Looks like we've defeated the RISCVISD::GORCI matching code

craig.topper added inline comments.Jan 26 2021, 12:43 PM
llvm/test/CodeGen/RISCV/rv64Zbp.ll
1105

Running the tests through instcombine also breaks GORCI matching.

craig.topper added inline comments.Jan 26 2021, 12:47 PM
llvm/test/CodeGen/RISCV/rv64Zbp.ll
1105

It's also worth noting, the tests that are failing are repeating the same pattern gorc pattern twice, which is redundant. The test was trying to test that we could detect the redundancy. I guess this patch may have seen some of the redundancy?