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llvm/test/CodeGen/X86/vector-rotate-128.ll | ||
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2334 | This seems to be the last regression - we fold (and (shift x, c1), c2) but fail to do the same for (and (rotate x, c1), c2) |
I think i can't spot any more regressions.
Looks good to me, but one more review would be best.
llvm/test/CodeGen/X86/vector-rotate-128.ll | ||
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2332–2333 | So we exchanged this or + and-by-folded-load for constant pool load + vpternlogq ? |
llvm/test/CodeGen/RISCV/rv64zbp.ll | ||
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1863 | @craig.topper Is this change OK? The test is called grev16_32 and neither target generates a grev op. |
llvm/test/CodeGen/RISCV/rv64zbp.ll | ||
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1863 | I think it is ok. It's now matches grev16_i32_fshl and grev16_i32_fshr which are the same as this using intrinsics instead of shifts and or. Our assumption was that a rotate would be at least as good as a grev instruction. |
@craig.topper Is this change OK? The test is called grev16_32 and neither target generates a grev op.