- User Since
- Feb 24 2015, 1:18 AM (241 w, 6 d)
Sat, Oct 12
Patch updated (SystemZInstrFormats.td).
Fri, Oct 11
Tue, Oct 8
Thu, Oct 3
Filed a bugreport for ScalarEvolution relating to this as this is an issue also without this particular patch: https://bugs.llvm.org/show_bug.cgi?id=43545
I noticed that the output of Loop Strength Reduce differs with this simple patch, and the diff includes actual instructions and opcodes, and this is when LoopDataPrefetch does not emit any prefetches.
Tue, Oct 1
Mon, Sep 30
ping! Please fix test cases that have been found broken (on trunk without this patch!).
Thu, Sep 26
Use a new diag::err_opt_not_valid_without_opt value instead of "..._with_opt"
Thanks for review - r372950.
Wed, Sep 25
The backend check for fentry could perhaps be performed in MachineFunction::init() somehow, but doing it fairly early in SystemZDAGToDAG::runOnMachineFunction() seems reasonable, or (we don't have any pre-isel passes that are always run)?
Check that -mnop-mcount is only passed for systemz, and check as well that -fentry was passed.
Thanks for review - patch updated.
Tue, Sep 24
Put 'NextMIIt->getOperand(3).getImm() == CCValid' in an assert instead since this must be true.
Mon, Sep 23
Also recognize CLR and CLGR instructions which also can be commuted in order to fold the spilled operand. Compare logical register sets CC the same way as signed comparisons, so the trySwapCompareOperands() should work as is. This folds another ~200 reloads on benchmarks.
Fri, Sep 20
Thu, Sep 19
See https://reviews.llvm.org/D67765 for the SystemZ backend part of this patch set.
Tue, Sep 17
Tried to make some more tests in multiselect.ll to cover merging of Select pseudos. Trunk fails on @test1.
Mon, Sep 16
Sep 13 2019
Updated per review.
The only issue with multi-threaded programs would be persistant state...
OK, thanks for the explanation.
Sep 12 2019
In general, 'lg; cgrje' should have the same performance as 'cg; je' (both have one single-issue and one dual-issue opcode on current micro-archs). However, the 'cg; je' version does not require a GPR to hold the value to be compared against, so it may be preferable due to register pressure concerns.
Wait - is it safe to have SystemZRegisterInfo::isHighReg() be a static function? I remember that you said that static functions were bad in multi-threaded programs. Is the "Reg" argument safe if two threads call this method simultaneously?
I moved the functions and renamed them trySelectLOCRMux() and trySelectSELRMux() to avoid confusion (they do not "expand" the LOCRMux). Is there a point in passing the opcodes as arguments to them?
Sep 11 2019
Remove the assert "A logical opcode was selected in presence of the nsw flag." This is too aggressive, as a zero extension can be folded into the instruction regardless of "nsw" (e.g. ALGFR).
Sep 10 2019
- Added assert when detecting an add with immediate, that this is not an immediate offset of a memory instruction but indeed an immediate operand.
Sep 9 2019
Sep 5 2019
Sep 4 2019
Updated per review.
Updated per the review so far.
Fix: Remember to check for MBB equality in SystemZPostRASchedStrategy::enterMBB()
Sep 3 2019
Aug 28 2019
Aug 27 2019
Aug 25 2019
It would be very nice if people with knowledge of the Hexagon and X86 backends could help out on fixing the failing tests. Note that these tests have been discovered to have a broken MIR (!), so please help...
Jul 16 2019
Jul 4 2019
Thanks for the review of the patch so far!
Jul 2 2019
Thank you for review.
Jun 29 2019
Jun 25 2019
- Don't use VRM for VirtReg in analyzeOperands(). In case of an eviction (where VirtReg already has a physreg in VRM), this previous regclass should not be reused initially.
Jun 18 2019
Here's an updated list of stats for SPEC 2006, with the latest fixes applied, and also with "soft hints" at the bottom.
Don't skip all 2-address hints in getRegallocationHints() just because it's a GRH32 register: AHIMuxK actually can expand to a 2-address instruction using a high register.
Jun 17 2019
- SystemZSelectMux.cpp merged into SystemZPostRewrite.cpp.
Jun 8 2019
This test has now been added as int-sub-11.ll by r362868 "Favor 3-address instructions during instruction selection".
Jun 7 2019
Thanks for review! Committed as r362868.