♟ tpr

[AMDGPU] Avoid DAG combining assert with fneg(fadd(A,0))

[AMDGPU] Flag new raw/struct atomic ops as source of divergence

V3: Further reduced test case.

V2: Addressed review comments.

V2: Addressed review comment: moved tests.

Bug for adding remaining test cases is https://bugs.llvm.org/show_bug.cgi?id=41500

V3: Addressed review comments.

PS I'm only speaking for LLPC. I don't know if Mesa uses it.

I think the only obstacle is getting round to doing the LLPC changes. So this is hopefully a short term fix until we can get around to it.

[AMDGPU] Fixed incorrect test in vcnd/vcmp optimization

I have cut down the test a bit more and put it into fneg-combines.ll. I did not manage to repro any problems with the other cases that I added fixes for.

V2: Cut down test a bit more and put it in fneg-combines.ll.

I did not add a test because I believe that we do not currently set the source modifiers in codegen, so this code never gets exercised.

That's the best bugpoint could do with the test.

Hopefully fixed by D60457.

LGTM modulo the wrong license on the new file.

InstCombineSimplifyDemanded: Allow v3 results for AMDGCN buffer and image…

[AMDGPU] Use three- and five-dword result type in image ops

[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics

[AMDGPU] Added v5i32 and v5f32 register classes

[AMDGPU] Support for v3i32/v3f32

[AMDGPU] Do not generate spurious PAL metadata

Thanks for the better test Matt. But I'll abandon this one in favor of Michael's improved fix D59608.

Thanks Michael; that is much better than my fix in D59556. Let's go with this one and I'll abandon my one.

[AMDGPU] Added MsgPack format PAL metadata

[AMDGPU] Factored PAL metadata handling out into its own class

The test is already reduced as much as I can. Removing anything in there makes the problem disappear. Constructing a new test case using llvm.uadd.with.overflow does not show the problem. Can we go with this test case?

V4: Generate vendor=AMDGPU, type=32 for the metadata note record, as now expected by PAL.

V3: Rebased, and addressed "single char in single quotes" review comment from the other change.

V3: Fixed review comments.

[AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic

[AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers

[MsgPack][AMDGPU] Fix unflushed raw_string_ostream bugs on windows expensive…

V2: Like the previous commit, no longer supports a method for LLPC to

call to write the PAL metadata into IR metadata. The plan now is
that LLPC will use MsgPackDocument and put the msgpack binary blob
into IR metadata itself.

V2: Removed AMDGPUPALMetadata API used directly by LLPC. The plan now is

that LLPC will continue to put the PAL metadata binary blob
into IR metadata itself.

[CodeGen] Defined MVTs v3i32, v3f32, v5i32, v5f32

[CodeGen] Prepare for introduction of v3 and v5 MVTs

[AMDGPU] Prepare for introduction of v3 and v5 MVTs

[ARM] Fixed an assumption of power-of-2 vector MVT

V5: Added vec3 to AMDGPUCallingConvention.td. Fixed call-return-types test for dwordx3 buffer/flat.
(I will add vec5 to AMDGPUCallingConvention.td in the vec5 change.)

V5: Added vec3/vec5 non-shader arg and ret type test cases, including passing by stack.

V4: Properly addressed review comment.

V3: Adjusted the MIR roundtrip fix to use scoping instead of explicit flush.

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