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steven.zhang (qshanz)
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May 15 2018, 2:45 AM (88 w, 6 d)

Recent Activity

Wed, Jan 15

steven.zhang updated the diff for D72031: [Scheduling] Create the missing dependency edges for store cluster.

Address the comments. And all the case changes disappear with the patch https://reviews.llvm.org/D72706 landed. So, I didn't see the negative impact from this patch any more. And from the design, it is doing the right thing, without increasing the compiling time.

Wed, Jan 15, 2:37 AM · Restricted Project

Tue, Jan 14

steven.zhang updated the diff for D72676: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions.
Tue, Jan 14, 12:07 AM · Restricted Project

Mon, Jan 13

steven.zhang updated the diff for D72676: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions.

Only alias the safe one.

Mon, Jan 13, 9:26 PM · Restricted Project
steven.zhang set the repository for D72676: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions to rG LLVM Github Monorepo.
Mon, Jan 13, 9:26 PM · Restricted Project
steven.zhang created D72676: [PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions.
Mon, Jan 13, 7:45 PM · Restricted Project
steven.zhang added a comment to D72250: [NFC][PowerPC] Refactor the tryAndWithMask().

Ping ...

Mon, Jan 13, 2:53 AM · Restricted Project

Wed, Jan 8

steven.zhang committed rGd48ac7d54d8a: [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z) (authored by steven.zhang).
[DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z)
Wed, Jan 8, 8:48 PM
steven.zhang closed D72312: [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z).
Wed, Jan 8, 8:48 PM · Restricted Project
steven.zhang added a comment to D69836: [MIR] Target specific MIR formating and parsing.

Hmm, cause the sanity failure.

/home/qshanz/work/commit/build/bin/llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < /home/qshanz/work/commit/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll 2>&1 | /home/qshanz/work/commit/build/bin/FileCheck /home/qshanz/work/commit/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll
/home/qshanz/work/commit/llvm/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll:19:10: error: CHECK: expected string not found in input
; CHECK: t2STRDi8
         ^
<stdin>:1:1: note: scanning from here
Args: /home/qshanz/work/commit/build/bin/llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null
^
<stdin>:21:25: note: possible intended match here
.. opcode 39 is aliased to 38
Wed, Jan 8, 7:47 PM · Restricted Project
steven.zhang added a comment to D72031: [Scheduling] Create the missing dependency edges for store cluster.

This adds new dependencies, hence I think it would be good to gather code size/perf numbers with this change for some impacted targets (e.g. AArch64) to be reasonably sure that there are no unexpected knock-on effects.

Wed, Jan 8, 2:43 AM · Restricted Project

Tue, Jan 7

steven.zhang updated the diff for D72312: [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z).

Use the isNegatibleForFree/getNegatibleExpression mechanism.

Tue, Jan 7, 11:02 PM · Restricted Project
steven.zhang committed rG44f78f368c2c: [NFC][Test] Add the option -enable-no-signed-zeros-fp-math for test fma-combine. (authored by steven.zhang).
[NFC][Test] Add the option -enable-no-signed-zeros-fp-math for test fma-combine.
Tue, Jan 7, 10:52 PM
steven.zhang added inline comments to D72031: [Scheduling] Create the missing dependency edges for store cluster.
Tue, Jan 7, 5:13 AM · Restricted Project
steven.zhang added a comment to D72312: [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z).

This is really a good suggestion. I will go with that mechanism, though it seems that, it didn't respect the TLI.isFNegFree() and UnsafeFPMath which didn't make sense. (When it is FNEG opcode, we just return 2 to indicate that it is profitable. What if some target is free for FNEG operations ...)

Tue, Jan 7, 3:32 AM · Restricted Project
steven.zhang added inline comments to D72031: [Scheduling] Create the missing dependency edges for store cluster.
Tue, Jan 7, 3:23 AM · Restricted Project

Mon, Jan 6

steven.zhang updated the diff for D72312: [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z).

Format the patch.

Mon, Jan 6, 9:09 PM · Restricted Project
steven.zhang created D72312: [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z).
Mon, Jan 6, 7:47 PM · Restricted Project
steven.zhang committed rGd877229b5b21: [NFC][Test] Add a test to verify the DAGCombine of fma (authored by steven.zhang).
[NFC][Test] Add a test to verify the DAGCombine of fma
Mon, Jan 6, 7:20 PM
steven.zhang updated the diff for D72250: [NFC][PowerPC] Refactor the tryAndWithMask().
Mon, Jan 6, 7:01 PM · Restricted Project
steven.zhang added a comment to D72031: [Scheduling] Create the missing dependency edges for store cluster.

Ping ...

Mon, Jan 6, 6:15 PM · Restricted Project
steven.zhang created D72250: [NFC][PowerPC] Refactor the tryAndWithMask().
Mon, Jan 6, 2:35 AM · Restricted Project

Sun, Jan 5

steven.zhang added a comment to D72070: [NFC] Refactor memory ops cluster method.

I like this patch, as it really takes me a while to understand what it is before your patch.

Sun, Jan 5, 11:02 PM · Restricted Project
steven.zhang committed rGb9780f4f80ba: [DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG (authored by steven.zhang).
[DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG
Sun, Jan 5, 7:12 PM
steven.zhang closed D70230: [DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG.
Sun, Jan 5, 7:11 PM · Restricted Project
steven.zhang accepted D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.

LGTM. But please hold on some days in case someone else has other comments.

Sun, Jan 5, 6:43 PM · Restricted Project
steven.zhang added a comment to D71983: [PowerPC] Set the SideEffects of branch & call instructions from 1 to 0.

Do you expect any effect at all from doing this? These are all scheduling barriers?

Sun, Jan 5, 6:25 PM · Restricted Project

Thu, Jan 2

steven.zhang committed rG2133d3c5586b: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for… (authored by steven.zhang).
[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for…
Thu, Jan 2, 7:31 PM
steven.zhang closed D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'.
Thu, Jan 2, 7:30 PM · Restricted Project
steven.zhang added a comment to D71693: [NFC][PowerPC] Add a function tryAndWithMask.

Yes, it is just moving the code into a new function to avoid too much code in the switch case. And it is definition more clear if moving the condition into small functions. As there are several different conditions that could produce the same instruction with different arguments. I will do it as follows.

bool tryAndWithMask(...) {
Thu, Jan 2, 6:44 PM · Restricted Project
steven.zhang added a comment to D58378: [PowerPC]Leverage the addend in the TOC relocation to do the address calculation.
Thu, Jan 2, 6:34 PM · Restricted Project
steven.zhang added a comment to D58378: [PowerPC]Leverage the addend in the TOC relocation to do the address calculation.

I get the reason about 0x8000 now.

#ha(value) Denotes the high adjusted value: bits 16 - 63 of the indicated value, compensating
for #lo() being treated as a signed number. That is:
#ha(x) = (x + 0x8000) >> 16
The TOC region commonly includes data items within the .got, .toc, .sdata, and .sbss sections. In the medium
code model, they can be addressed with 32-bit signed offsets from the TOC pointer register. The TOC pointer
register typically points to the beginning of the .got section + 0x8000, which permits a 2 GB TOC with the
medium and large code models.
Thu, Jan 2, 5:14 AM · Restricted Project
steven.zhang added a comment to D72069: [NFC] Add explicit instantiation to releaseNode.

If you want to pass it with parameter, why not change the signature of releaseNode directly instead of adding a wrapper. We need to make decision about template arguments vs function parameter :)

+1. I think just passing InPQueue would keep things simpler and it should get inlined anyways ;)

Thu, Jan 2, 2:34 AM · Restricted Project
steven.zhang added a comment to D58378: [PowerPC]Leverage the addend in the TOC relocation to do the address calculation.

b.c:(.text+0x8): relocation truncated to fit: R_PPC64_TOC16_HA against symbol `b' defined in COMMON section in /tmp/b-9d97be.o+7ffffff8

The r_addend is 0x7ffffff8, a value close to 2**31.

The distance between the TOC entry and the variable address cannot be too far. More accurately, -0x80008000 <= address - .TOC. + r_addend < 0x7fff8000

GNU ld correctly reports a relocation overflow. lld currently does not check R_PPC64_TOC16_HA overflow.

% powerpc64le-linux-gnu-ld -pie b.o main.o
powerpc64le-linux-gnu-ld: warning: cannot find entry symbol _start; defaulting to 0000000000000230
powerpc64le-linux-gnu-ld: b.o: in function `foo':
b.c:(.text+0x8): relocation truncated to fit: R_PPC64_TOC16_HA against symbol `b' defined in COMMON section in b.o+7ffffff8

The largest address a pair of HA/L can materialize is something like:

addis 3, 2, 32767  # adding 1 will overflow to -32768
lfd 1, 32767(3)
Thu, Jan 2, 1:30 AM · Restricted Project
steven.zhang added a comment to D72069: [NFC] Add explicit instantiation to releaseNode.

If you want to pass it with parameter, why not change the signature of releaseNode directly instead of adding a wrapper. We need to make decision about template arguments vs function parameter :)

Thu, Jan 2, 12:25 AM · Restricted Project
steven.zhang added a comment to D65506: [MachineScheduler] improve reuse of 'releaseNode'method.

Hi,

bad luck, got a build failure.
Link to the report: http://lab [.] llvm [.] org:8011/builders/clang-ppc64be-linux-lnt/builds/33875

Build Reason: scheduler
Build Source Stamp: [branch master] f9f78cf6ac73d9148be9b626f418bf6770e512f6
Blamelist: Lorenzo Casalino <lorenzo.casalino93@gmail.com>

BUILD FAILED: failed test-suite
Thu, Jan 2, 12:16 AM · Restricted Project

Wed, Jan 1

steven.zhang planned changes to D58378: [PowerPC]Leverage the addend in the TOC relocation to do the address calculation.
Wed, Jan 1, 10:24 PM · Restricted Project
steven.zhang updated the diff for D58378: [PowerPC]Leverage the addend in the TOC relocation to do the address calculation.

Still need to investigate why it is 27 bit limit.

Wed, Jan 1, 10:24 PM · Restricted Project
steven.zhang added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Wed, Jan 1, 10:00 PM · Restricted Project
steven.zhang updated the diff for D72031: [Scheduling] Create the missing dependency edges for store cluster.

Address comments about the test case.

Wed, Jan 1, 9:50 PM · Restricted Project
steven.zhang updated the diff for D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'.

Rebase the patch due to the AArch64 commit 65651f197a2c which try to legalize sext_inreg for vector type for SVE. We need to specify it explicitly instead of relying on the default value. I will hold on this patch for several days in case someone has comments on the change of "SVE" part.

Wed, Jan 1, 9:38 PM · Restricted Project

Tue, Dec 31

steven.zhang added inline comments to D72031: [Scheduling] Create the missing dependency edges for store cluster.
Tue, Dec 31, 2:06 AM · Restricted Project
steven.zhang updated the diff for D72031: [Scheduling] Create the missing dependency edges for store cluster.
Tue, Dec 31, 2:06 AM · Restricted Project
steven.zhang updated the summary of D72031: [Scheduling] Create the missing dependency edges for store cluster.
Tue, Dec 31, 1:58 AM · Restricted Project
steven.zhang created D72031: [Scheduling] Create the missing dependency edges for store cluster.
Tue, Dec 31, 1:58 AM · Restricted Project

Mon, Dec 30

steven.zhang added a comment to D71693: [NFC][PowerPC] Add a function tryAndWithMask.

I realize that most reviewers were on vacation during this patch was reviewed and committed. It is a bit too haste to commit this patch. Please add the comments here if have any concern. Sorry about this.

Mon, Dec 30, 5:44 AM · Restricted Project
steven.zhang added a comment to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..

I realize that most reviewers were on vacation during this patch was reviewed and committed. It is a bit too haste to commit this patch. Please add the comments here if have any concern. Sorry about this.

Mon, Dec 30, 5:42 AM · Restricted Project
steven.zhang added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Mon, Dec 30, 3:54 AM · Restricted Project
steven.zhang added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Mon, Dec 30, 2:14 AM · Restricted Project
steven.zhang requested changes to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.

The RLWINMo should also be removed,

Mon, Dec 30, 1:56 AM · Restricted Project

Sun, Dec 29

steven.zhang accepted D71886: [NFC] Add test case for load-insert-store pattern in InstCombine.

I think, you don't need to post phabricator review for adding tests, except that, you are not confident on the way how it is wrote. LGTM.

Sun, Dec 29, 11:49 PM · Restricted Project
steven.zhang added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Sun, Dec 29, 10:43 PM · Restricted Project
steven.zhang added inline comments to D70651: [Power8] Add the MacroFusion support for Power8 .
Sun, Dec 29, 10:24 PM · Restricted Project
steven.zhang accepted D71921: [NFC] [PowerPC] Use isPredicable bits in instruction definitions.

LGTM as it makes sense. But please hold on for some days in case someone else have other concern. And I suggest you commit follow up patches to set this bit for other branch instructions.

Sun, Dec 29, 10:24 PM · Restricted Project
steven.zhang updated the diff for D70651: [Power8] Add the MacroFusion support for Power8 .

Address comments.

Sun, Dec 29, 10:15 PM · Restricted Project
steven.zhang committed rG874a8004f935: [PowerPC] Exploit the rlwinm instructions for "and" with constant (authored by steven.zhang).
[PowerPC] Exploit the rlwinm instructions for "and" with constant
Sun, Dec 29, 7:23 PM
steven.zhang closed D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Sun, Dec 29, 7:23 PM · Restricted Project
steven.zhang added a comment to D71921: [NFC] [PowerPC] Use isPredicable bits in instruction definitions.

You need to revisit the place that use the isPredicable bit of the MI, which might cause functionality change. i.e.

bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
  if (!MI.isTerminator()) return false;
Sun, Dec 29, 7:14 PM · Restricted Project
steven.zhang added inline comments to D70651: [Power8] Add the MacroFusion support for Power8 .
Sun, Dec 29, 6:37 PM · Restricted Project

Dec 26 2019

steven.zhang added a comment to D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'.

Ping ...

Dec 26 2019, 2:55 AM · Restricted Project
steven.zhang added a parent revision for D71893: [PowerPC] Exploit the rldicl + rldicr when "and" with constant: D71891: [PowerPC] Exploit the rlwinm + rlwinm when "and" with constant.
Dec 26 2019, 2:49 AM · Restricted Project
steven.zhang added a child revision for D71891: [PowerPC] Exploit the rlwinm + rlwinm when "and" with constant: D71893: [PowerPC] Exploit the rldicl + rldicr when "and" with constant.
Dec 26 2019, 2:49 AM · Restricted Project
steven.zhang created D71893: [PowerPC] Exploit the rldicl + rldicr when "and" with constant.
Dec 26 2019, 2:49 AM · Restricted Project
steven.zhang added parent revisions for D71891: [PowerPC] Exploit the rlwinm + rlwinm when "and" with constant: D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding, D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 26 2019, 2:22 AM · Restricted Project
steven.zhang added a child revision for D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding: D71891: [PowerPC] Exploit the rlwinm + rlwinm when "and" with constant.
Dec 26 2019, 2:22 AM · Restricted Project
steven.zhang added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 26 2019, 2:22 AM · Restricted Project
steven.zhang added a child revision for D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant.: D71891: [PowerPC] Exploit the rlwinm + rlwinm when "and" with constant.
Dec 26 2019, 2:22 AM · Restricted Project
steven.zhang created D71891: [PowerPC] Exploit the rlwinm + rlwinm when "and" with constant.
Dec 26 2019, 2:17 AM · Restricted Project
steven.zhang updated the diff for D71831: [PowerPC] Exploit the rldicl + rldicl when and with mask.

Rebase the patch. Testing with spec and get about ~4k instructions reduce.

Dec 26 2019, 12:33 AM · Restricted Project

Dec 25 2019

steven.zhang updated the diff for D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..

Remove the 16-bit limit as we will have benefit even it is within 16bit, as rlwinm won't define the CR register while ANDIo did.

Dec 25 2019, 11:30 PM · Restricted Project
steven.zhang added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 25 2019, 11:29 PM · Restricted Project
steven.zhang added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 25 2019, 9:51 PM · Restricted Project
steven.zhang added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 25 2019, 9:44 PM · Restricted Project
steven.zhang added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 25 2019, 8:59 PM · Restricted Project
steven.zhang committed rGe973783916d3: [NFC][PowerPC] Add a function tryAndWithMask to handle all the cases that 'and'… (authored by steven.zhang).
[NFC][PowerPC] Add a function tryAndWithMask to handle all the cases that 'and'…
Dec 25 2019, 6:51 PM
steven.zhang closed D71693: [NFC][PowerPC] Add a function tryAndWithMask.
Dec 25 2019, 6:51 PM · Restricted Project
steven.zhang accepted D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

LGTM with some minor nit.

Dec 25 2019, 6:14 PM · Restricted Project

Dec 23 2019

steven.zhang added inline comments to D71693: [NFC][PowerPC] Add a function tryAndWithMask.
Dec 23 2019, 6:40 PM · Restricted Project
steven.zhang added a comment to D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

We need another patch to fix the dead instruction removal for record form I think.

Dec 23 2019, 6:31 PM · Restricted Project
steven.zhang added a comment to D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

Thanks for finding the bug in the testcases. I have modified them in NFC patch https://reviews.llvm.org/rG79b3325be0b016fdc1a2c55bce65ec9f1e5f4eb6

Could you please help to be more specific about the invalid case in the description?

Below c code gives a valid result:

#include <stdio.h>

#define rlwinm( output, input, sh, mb, me ) \
   __asm__( "rlwinm %0, %1, %2, %3, %4" \
          : "=r"(output) \
          : "r"(input), "i"(sh), "i"(mb), "i"(me) \
          : )

int main()
{
   unsigned long y,z,t ;

   int i = 0;

   for (unsigned x = 0; x < 4294967295; x++)  {
     rlwinm( y, x, 27, 30, 10) ;
     rlwinm( z, y, 19, 0, 12);
     rlwinm(t, x, 14, 11, 12);
     if (z != t) {
       printf("0x%016lX -> 0x%016lX, 0x%016lX\n", x, y, z);
       printf("0x%016lX -> 0x%016lX\n", x, t);
       i = 100;
       break;
    }
   }
   if (i == 0)
     printf("valid\n");
   else
     printf("invalid\n");
   return 0;
}

So I guess

%2:gprc = RLWINM %1:gprc, 27, 30, 10
%3:gprc = RLWINM %2:gprc, 19, 0, 12

should always be equal to

%3:gprc = RLWINM %1, 14, 11, 12

for type i32 and i64 also?

Dec 23 2019, 6:31 PM · Restricted Project
steven.zhang added a comment to D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

Transfer to Zheng to continue working on this.

Dec 23 2019, 6:31 PM · Restricted Project
steven.zhang updated the summary of D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.
Dec 23 2019, 3:54 AM · Restricted Project
steven.zhang updated the summary of D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.
Dec 23 2019, 3:53 AM · Restricted Project
steven.zhang created D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.
Dec 23 2019, 3:46 AM · Restricted Project
steven.zhang added a parent revision for D71831: [PowerPC] Exploit the rldicl + rldicl when and with mask: D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 23 2019, 1:14 AM · Restricted Project
steven.zhang created D71831: [PowerPC] Exploit the rldicl + rldicl when and with mask.
Dec 23 2019, 1:14 AM · Restricted Project
steven.zhang added a child revision for D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant.: D71831: [PowerPC] Exploit the rldicl + rldicl when and with mask.
Dec 23 2019, 1:14 AM · Restricted Project
steven.zhang added a parent revision for D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant.: D71693: [NFC][PowerPC] Add a function tryAndWithMask.
Dec 23 2019, 1:01 AM · Restricted Project
steven.zhang added a child revision for D71693: [NFC][PowerPC] Add a function tryAndWithMask: D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 23 2019, 1:01 AM · Restricted Project
steven.zhang created D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Dec 23 2019, 1:01 AM · Restricted Project
steven.zhang updated the diff for D71693: [NFC][PowerPC] Add a function tryAndWithMask.
Dec 23 2019, 12:52 AM · Restricted Project

Dec 22 2019

steven.zhang committed rG6d5e35e89d73: [Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics… (authored by steven.zhang).
[Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics…
Dec 22 2019, 11:48 PM
steven.zhang closed D70657: [Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics of ISD::BSWAP.
Dec 22 2019, 11:48 PM · Restricted Project
steven.zhang committed rG9d1071eac401: [NFC][Test][PowerPC] Add more tests for 'and mask' (authored by steven.zhang).
[NFC][Test][PowerPC] Add more tests for 'and mask'
Dec 22 2019, 11:02 PM

Dec 20 2019

steven.zhang accepted D71391: [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0.

LGTM.

Dec 20 2019, 2:44 AM · Restricted Project

Dec 19 2019

steven.zhang created D71693: [NFC][PowerPC] Add a function tryAndWithMask.
Dec 19 2019, 1:28 AM · Restricted Project
steven.zhang abandoned D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.
Dec 19 2019, 12:49 AM · Restricted Project

Dec 18 2019

steven.zhang added inline comments to D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.
Dec 18 2019, 11:50 PM · Restricted Project
steven.zhang added inline comments to D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.
Dec 18 2019, 6:28 PM · Restricted Project
steven.zhang planned changes to D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.
Dec 18 2019, 2:07 AM · Restricted Project
steven.zhang requested review of D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.
Dec 18 2019, 1:53 AM · Restricted Project