- User Since
- May 15 2018, 2:45 AM (53 w, 3 d)
https://reviews.llvm.org/D62370 is created to update the test llvm/test/CodeGen/SystemZ/codegenprepare-splitstore.ll
Thu, May 23
LGTM. But please hold on for some days if someone else might have comments.
Tue, May 21
Address jinong's comments.
Mon, May 20
Gentle ping ... Thank you!
LGTM, except some minor comments. However, please hold on for some days, if others have comments.
Tue, May 14
Mon, May 13
FYI. This is the thread of the discussion. http://lists.llvm.org/pipermail/llvm-dev/2016-September/105291.html
That was discussed widely when https://reviews.llvm.org/D26149 is reviewed. This is the commit log saying something about the delay.
This optimization was discussed on llvm-dev some time ago in "Load combine pass" thread. We came to the conclusion that we want to do this transformation late in the pipeline because in presence of atomic loads load widening is irreversible transformation and it might hinder other optimizations.
Sun, May 12
Gentle ping ...
Wed, May 8
ok. Use the hasValue instead of the implicit bool convert operator to make the code clear.
Sat, May 4
Update local variable name.
Mon, Apr 29
Use opt instead of llc to do the check.
Sun, Apr 28
@fhahn I have completed all the needed patches, and it would be great if you have the time to continue the review. This is the whole picture.
https://reviews.llvm.org/D61248 is the 1st patch to allow the schedule strategy to forward the schedule state between MBB.
https://reviews.llvm.org/D61249 is the 2nd patch to update the schedule strategy for SystemZ target to adapt with 1st patch.
https://reviews.llvm.org/D59480(this patch) is the 3rd patch to add the scheduled state data structure, so that, it could be kept somewhere.
https://reviews.llvm.org/D61250 is the last patch to forward the scheduled state 3rd patch added for PostGenericScheduler and enable it for PowerPC target.
Update the patch according to the reviewer comments.
Sat, Apr 27
Thu, Apr 25
Apr 15 2019
I am ok now for the doc part change. Thank you.
Apr 10 2019
Looks good, just one minor comments.
It seems that, we have already had the PowerPC section in the rst. It would be better to put them together.
PowerPC Language Extensions ------------------------------
Apr 7 2019
It would be great if we could add some documentation for these new added builtins, to make more people to know what we have done. i.e. clang/docs/LanguageExtensions.rst
Mar 27 2019
Mar 26 2019
ok. I will prepare another two patches first, so that, we could continue the review.
Thank you for the review comments. I have addressed all the comments.
Mar 24 2019
gentle ping ...
Mar 18 2019
Mar 17 2019
gentle ping ..
Mar 12 2019
Mar 5 2019
Mar 4 2019
Feb 19 2019
Dec 25 2018
Dec 18 2018
LGTM. However, please hold on until another reviewer accept this patch,
Dec 17 2018
Dec 6 2018
It seems that, there are more registers in ABI about the additional register than we present in this patch. It would be great if we would list all of them here or add some comments to indicate this at least.
Dec 5 2018
Dec 3 2018
Dec 2 2018
Nov 29 2018
Update the comments.
Nov 27 2018
Nov 26 2018
Thank you for the detail explanation. So, there are Pro & Cons for both and they are targeting for different purpose. For this case, we shouldn't use this script as we have clear testing point.
Nov 21 2018
Personally, I don't like writing the test case using such script. Because, it will check all the instructions and make your test point unclear. And it hard code the register name, which make this test fragile。
You don't need create a review for the new added NFC test case. LGTM.
Oct 25 2018
Oct 21 2018
Oct 16 2018
The patch will disable some valid transformation post RA(i.e. LXSDX --> LXSD if the def reg is valid for D-form). We can continue to check the dst Reg to see if it is valid, instead of disabling it completely.
Oct 11 2018
This is for pre-RA and my fix is for Post RA. Maybe, we can extend my fix to cover the pre-RA case. I will re-submit a new fix to cover this test case. I think, we could abandon this fix.
Oct 9 2018
@wuzish You could apply the commit access from community. I will commit the patch for you.
Sep 19 2018
I will commit the patch for you.
I will commit the patch for you.
Sep 12 2018
Aug 21 2018
Aug 17 2018
I have done the following tests with this patch:
- LLVM check-all uniitests
- LLVM test-suites
- bootstrap build the clang with the clang including my fix, and then, run the llvm check-all and test-suites, and it passed.
Jul 30 2018
I have updated the patch and we can continue the review now.
Jul 20 2018
Jul 19 2018
Clean up all the failures from llvm test-suite. We miss to check the RegMO operand for the ADDI.
Jul 16 2018
Yes, you are right.
y = ADDI x, imm.
w = LFDX 0, y
Jul 6 2018
Jul 1 2018
It is done.
Jun 12 2018
Remove the data layout and triple in the IR and specify it in the command line.
Add the triple for the new created test case toc-float.ll
Jun 10 2018
Jun 8 2018
Update the change basing on Nemanjai's comment. Thank you.
May 31 2018
If I understand correctly, we may also need to handle the DFLOADf32/DFLOADf64 and store pair here, as this is done pre-RA.
There are two changes:
- add a query to check if it is imm operand as Nemanjai suggested. Didn't find other places that could use this query.
- add a new test case to address the global case.
Thank you for the comment. I will fix that. BTW, I cannot get the assertion from your case, but this case.(miss some options ?) It seems that, clang put the floating variable into the TOC with some condition, which is different from gcc/xlc. I will deliver some other change to fix this issue.