[DAG] Enable ISD::SHL/SRL SimplifyMultipleUseDemandedBits handling (WIP)

[RKSimon]

Summary

This patch enables us to peek through the shifted value if we don't demand all the bits/elts.

This is another step towards removing SelectionDAG::GetDemandedBits and just using TargetLowering::SimplifyMultipleUseDemandedBits.

There's a number of regressions that I'm still investigating, notably:

ARM's UXTB matching code
DAGCombiner::MatchRotate is struggling as it only matches with legal types + operations
X86 ends up splitting a funnel shift from another shift/lea

There a few cases where we end up with extra register moves which I think we can accept in exchange for the increaed ILP.

[RKSimon]

llvm/test/CodeGen/AMDGPU/trunc-combine.ll

148

@arsenm @foad Not sure if pulling out the immediate is a good idea or not - shouldn't a u16 immediate be cheap?

[arsenm]

llvm/test/CodeGen/AMDGPU/trunc-combine.ll

148

This is worse. Integer constants -16 to 64 and a handful of FP values are free, but 0xffff is not so it requires materialization.

[RKSimon]

rebase

[RKSimon]

still looking at the remaining regressions