[AsmPrinter] Print FP constant in hexadecimal form instead

[jsji]

Summary

Printing floating point number in decimal is inconvenient for humans.
Verbose asm output will print out floating point values in comments, it
helps.

But in lots of cases, users still need additional work to covert the
decimal back to hex or binary to check the bit patterns,
especially when there are small precision difference.

Hexadecimal form is one of the supported form in LLVM IR, and easier for
debugging.

This patch try to print all FP constant in hex form instead.

[merge_guards_bot]

Unit tests: pass. 62268 tests passed, 0 failed and 827 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

[jsji]

Ping.. Any feedback and comments are appreciated. Thanks.

[RKSimon]

@craig.topper Any comments?

[craig.topper]

In D73566#1857359, @RKSimon wrote:

@craig.topper Any comments?

Seems reasonable to me. @RKSimon did you have a concern?

[RKSimon]

In D73566#1857569, @craig.topper wrote:

In D73566#1857359, @RKSimon wrote:

@craig.topper Any comments?

Seems reasonable to me. @RKSimon did you have a concern?

Sorry no, I was getting this confused with your old D37184 patch

My only question is whether we should have leading zeros to guarantee a specific width for a given type?

llvm/test/CodeGen/X86/pr40730.ll

23

Should all these be the full .quad width (i.e. leading zeros)?

[jsji]

Thanks @RKSimon and @craig.topper .

Yes, good suggestion.
Updated to include leading zero paddings.

[merge_guards_bot]

Unit tests: pass. 62268 tests passed, 0 failed and 827 were skipped.

clang-tidy: unknown.

clang-format: unknown.

Build artifacts: CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

[RKSimon]

llvm/include/llvm/MC/MCExpr.h

134

unsigned SizeInBytes = 0;

[jsji]

Rename Size to SizeInBytes.

[jsji]

[merge_guards_bot]

Unit tests: pass. 62268 tests passed, 0 failed and 827 were skipped.

clang-tidy: pass.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

[jsji]

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

I believe this is bug in pre-merge bot. I did run clang-format before updating.
And I double confirmed again, nothing needs change on my
$ git clang-format HEAD^
clang-format did not modify any files

[RKSimon]

LGTM - thanks

llvm/include/llvm/MC/MCExpr.h

inline raw_ostream &operator<<(raw_ostream &OS, const MCExpr &E) {
   E.print(OS, nullptr);
   return OS;
 }
 
 ////  Represent a constant integer expression.
 class MCConstantExpr : public MCExpr {
   int64_t Value;
   bool PrintInHex = false;
+  unsigned SizeInBytes = 0;
 
   explicit MCConstantExpr(int64_t Value)
       : MCExpr(MCExpr::Constant, SMLoc()), Value(Value) {}
 
   MCConstantExpr(int64_t Value, bool PrintInHex)
       : MCExpr(MCExpr::Constant, SMLoc()), Value(Value),
         PrintInHex(PrintInHex) {}
 
+  MCConstantExpr(int64_t Value, bool PrintInHex, unsigned SizeInBytes)
+      : MCExpr(MCExpr::Constant, SMLoc()), Value(Value), PrintInHex(PrintInHex),
+        SizeInBytes(SizeInBytes) {}
+
 public:
   /// \name Construction
   /// @{
 
   static const MCConstantExpr *create(int64_t Value, MCContext &Ctx,
-                                      bool PrintInHex = false);
+                                      bool PrintInHex = false,
+                                      unsigned SizeInBytes = 0);
 
   /// @}
   /// \name Accessors
   /// @{
 
   int64_t getValue() const { return Value; }
+  unsigned getSizeInBytes() const { return SizeInBytes; }
 
   bool useHexFormat() const { return PrintInHex; }
 
   /// @}
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Constant;
   }

llvm/include/llvm/MC/MCStreamer.h

public:
 
   /// Special case of EmitValue that avoids the client having to pass
   /// in a MCExpr for constant integers & prints in Hex format for certain
   /// modes.
   virtual void EmitIntValueInHex(uint64_t Value, unsigned Size) {
     EmitIntValue(Value, Size);
   }
 
+  /// Special case of EmitValue that avoids the client having to pass
+  /// in a MCExpr for constant integers & prints in Hex format for certain
+  /// modes, pads the field with leading zeros to Size width
+  virtual void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) {
+    EmitIntValue(Value, Size);
+  }
+
   virtual void EmitULEB128Value(const MCExpr *Value);
 
   virtual void EmitSLEB128Value(const MCExpr *Value);
 
   /// Special case of EmitULEB128Value that avoids the client having to
   /// pass in a MCExpr for constant integers.
   void EmitULEB128IntValue(uint64_t Value, unsigned PadTo = 0);
 

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

static void emitGlobalConstantFP(APFloat APF, Type *ET, AsmPrinter &AP) {
   const uint64_t *p = API.getRawData();
 
   // PPC's long double has odd notions of endianness compared to how LLVM
   // handles it: p[0] goes first for *big* endian on PPC.
   if (AP.getDataLayout().isBigEndian() && !ET->isPPC_FP128Ty()) {
     int Chunk = API.getNumWords() - 1;
 
     if (TrailingBytes)
-      AP.OutStreamer->EmitIntValue(p[Chunk--], TrailingBytes);
+      AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk--], TrailingBytes);
 
     for (; Chunk >= 0; --Chunk)
-      AP.OutStreamer->EmitIntValue(p[Chunk], sizeof(uint64_t));
+      AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], sizeof(uint64_t));
   } else {
     unsigned Chunk;
     for (Chunk = 0; Chunk < NumBytes / sizeof(uint64_t); ++Chunk)
-      AP.OutStreamer->EmitIntValue(p[Chunk], sizeof(uint64_t));
+      AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], sizeof(uint64_t));
 
     if (TrailingBytes)
-      AP.OutStreamer->EmitIntValue(p[Chunk], TrailingBytes);
+      AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], TrailingBytes);
   }
 
   // Emit the tail padding for the long double.
   const DataLayout &DL = AP.getDataLayout();
   AP.OutStreamer->EmitZeros(DL.getTypeAllocSize(ET) - DL.getTypeStoreSize(ET));
 }
 
 static void emitGlobalConstantFP(const ConstantFP *CFP, AsmPrinter &AP) {

llvm/lib/MC/MCAsmStreamer.cpp

public:
   void EmitBinaryData(StringRef Data) override;
 
   void EmitBytes(StringRef Data) override;
 
   void EmitValueImpl(const MCExpr *Value, unsigned Size,
                      SMLoc Loc = SMLoc()) override;
   void EmitIntValue(uint64_t Value, unsigned Size) override;
   void EmitIntValueInHex(uint64_t Value, unsigned Size) override;
+  void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) override;
 
   void EmitULEB128Value(const MCExpr *Value) override;
 
   void EmitSLEB128Value(const MCExpr *Value) override;
 
   void EmitDTPRel32Value(const MCExpr *Value) override;
   void EmitDTPRel64Value(const MCExpr *Value) override;
   void EmitTPRel32Value(const MCExpr *Value) override;

 void MCAsmStreamer::EmitIntValue(uint64_t Value, unsigned Size) {
   EmitValue(MCConstantExpr::create(Value, getContext()), Size);
 }
 
 void MCAsmStreamer::EmitIntValueInHex(uint64_t Value, unsigned Size) {
   EmitValue(MCConstantExpr::create(Value, getContext(), true), Size);
 }
 
+void MCAsmStreamer::EmitIntValueInHexWithPadding(uint64_t Value,
+                                                 unsigned Size) {
+  EmitValue(MCConstantExpr::create(Value, getContext(), true, Size), Size);
+}
+
 void MCAsmStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size,
                                   SMLoc Loc) {
   assert(Size <= 8 && "Invalid size");
   assert(getCurrentSectionOnly() &&
          "Cannot emit contents before setting section!");
   const char *Directive = nullptr;
   switch (Size) {
   default: break;

llvm/lib/MC/MCExpr.cpp

 
 void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens) const {
   switch (getKind()) {
   case MCExpr::Target:
     return cast<MCTargetExpr>(this)->printImpl(OS, MAI);
   case MCExpr::Constant: {
     auto Value = cast<MCConstantExpr>(*this).getValue();
     auto PrintInHex = cast<MCConstantExpr>(*this).useHexFormat();
+    auto SizeInBytes = cast<MCConstantExpr>(*this).getSizeInBytes();
     if (PrintInHex)
+      switch (SizeInBytes) {
+      default:
         OS << "0x" << Twine::utohexstr(Value);
+        break;
+      case 1:
+        OS << format("0x%02" PRIx64, Value);
+        break;
+      case 2:
+        OS << format("0x%04" PRIx64, Value);
+        break;
+      case 4:
+        OS << format("0x%08" PRIx64, Value);
+        break;
+      case 8:
+        OS << format("0x%016" PRIx64, Value);
+        break;
+      }
     else
       OS << Value;
     return;
   }
   case MCExpr::SymbolRef: {
     const MCSymbolRefExpr &SRE = cast<MCSymbolRefExpr>(*this);
     const MCSymbol &Sym = SRE.getSymbol();
     // Parenthesize names that start with $ so that they don't look like

 }
 
 const MCUnaryExpr *MCUnaryExpr::create(Opcode Opc, const MCExpr *Expr,
                                        MCContext &Ctx, SMLoc Loc) {
   return new (Ctx) MCUnaryExpr(Opc, Expr, Loc);
 }
 
 const MCConstantExpr *MCConstantExpr::create(int64_t Value, MCContext &Ctx,
-                                             bool PrintInHex) {
-  return new (Ctx) MCConstantExpr(Value, PrintInHex);
+                                             bool PrintInHex,
+                                             unsigned SizeInBytes) {
+  return new (Ctx) MCConstantExpr(Value, PrintInHex, SizeInBytes);
 }
 
 /* *** */
 
 MCSymbolRefExpr::MCSymbolRefExpr(const MCSymbol *Symbol, VariantKind Kind,
                                  const MCAsmInfo *MAI, SMLoc Loc)
     : MCExpr(MCExpr::SymbolRef, Loc), Kind(Kind),
       UseParensForSymbolVariant(MAI->useParensForSymbolVariant()),

llvm/test/CodeGen/AArch64/arm64-fp-imm-size.ll

 ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
 
 ; CHECK: literal8
-; CHECK: .quad  4614256656552045848
+; CHECK: .quad  0x400921fb54442d18
 define double @foo() optsize {
 ; CHECK: _foo:
 ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE
 ; CHECK: ldr  d0, [x[[REG]], lCPI0_0@PAGEOFF]
 ; CHECK-NEXT: ret
   ret double 0x400921FB54442D18
 }
 
 ; CHECK: literal8
-; CHECK: .quad  137438953409
+; CHECK: .quad 0x0000001fffffffc
 define double @foo2() optsize {
 ; CHECK: _foo2:
 ; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0@PAGE
 ; CHECK: ldr  d0, [x[[REG]], lCPI1_0@PAGEOFF]
 ; CHECK-NEXT: ret
   ret double 0x1FFFFFFFC1
 }
 

llvm/test/CodeGen/AArch64/arm64-fp-imm.ll

 ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
 
 ; CHECK: literal8
-; CHECK: .quad  4614256656552045848
+; CHECK: .quad 0x400921fb54442d18
 define double @foo() {
 ; CHECK: _foo:
 ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE
 ; CHECK: ldr  d0, [x[[REG]], lCPI0_0@PAGEOFF]
 ; CHECK-NEXT: ret
   ret double 0x400921FB54442D18
 }
 

llvm/test/CodeGen/AArch64/f16-imm.ll

 entry:
   ret half 0xH3C00
 }
 ; CHECK-DAG-LABEL: Const1:
 ; CHECK-DAG-NEXT:   fmov h0, #1.00000000
 ; CHECK-DAG-NEXT:   ret
 
 ; CHECK-NOFP16:        .[[LBL1:LCPI1_[0-9]]]:
-; CHECK-NOFP16-NEXT:   .hword  15360 // half 1
+; CHECK-NOFP16-NEXT:   .hword  0x3c00 // half 1
 ; CHECK-NOFP16-LABEL:  Const1:
 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL1]]
 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL1]]]
 
 define half @Const2() {
 entry:
   ret half 0xH3000
 }
 ; CHECK-DAG-LABEL: Const2:
 ; CHECK-DAG-NEXT:   fmov h0, #0.12500000
 ; CHECK-DAG-NEXT:   ret
 
 ; CHECK-NOFP16:        .[[LBL2:LCPI2_[0-9]]]:
-; CHECK-NOFP16-NEXT:   .hword  12288 // half 0.125
+; CHECK-NOFP16-NEXT:   .hword  0x3000 // half 0.125
 ; CHECK-NOFP16-LABEL:  Const2:
 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL2]]
 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL2]]]
 
 define half @Const3() {
 entry:
   ret half 0xH4F80
 }
 ; CHECK-DAG-LABEL: Const3:
 ; CHECK-DAG-NEXT:   fmov h0, #30.00000000
 ; CHECK-DAG-NEXT:   ret
 
 ; CHECK-NOFP16:        .[[LBL3:LCPI3_[0-9]]]:
-; CHECK-NOFP16-NEXT:   .hword  20352 // half 30
+; CHECK-NOFP16-NEXT:   .hword  0x4f80 // half 30
 ; CHECK-NOFP16-LABEL:  Const3:
 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL3]]
 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL3]]]
 
 
 define half @Const4() {
 entry:
   ret half 0xH4FC0
 }
 ; CHECK-DAG-LABEL: Const4:
 ; CHECK-DAG-NEXT:  fmov h0, #31.00000000
 ; CHECK-DAG-NEXT:  ret
 
 ; CHECK-NOFP16:        .[[LBL4:LCPI4_[0-9]]]:
-; CHECK-NOFP16-NEXT:   .hword  20416                    // half 31
+; CHECK-NOFP16-NEXT:   .hword  0x4fc0                    // half 31
 ; CHECK-NOFP16-LABEL:  Const4:
 ; CHECK-NOFP16:        adrp x[[NUM:[0-9]+]], .[[LBL4]]
 ; CHECK-NOFP16-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL4]]]
 
 define half @Const5() {
 entry:
   ret half 0xH2FF0
 }
 ; CHECK-ILLEGAL:        .[[LBL5:LCPI5_[0-9]]]:
-; CHECK-ILLEGAL-NEXT:   .hword  12272                   // half 0.12402
+; CHECK-ILLEGAL-NEXT:   .hword  0x2ff0                  // half 0.12402
 ; CHECK-ILLEGAL-LABEL:  Const5:
 ; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL5]]
 ; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL5]]]
 
 define half @Const6() {
 entry:
   ret half 0xH4FC1
 }
 ; CHECK-ILLEGAL:        .[[LBL6:LCPI6_[0-9]]]:
-; CHECK-ILLEGAL-NEXT:   .hword  20417                   // half 31.016
+; CHECK-ILLEGAL-NEXT:   .hword  0x4fc1                 // half 31.016
 ; CHECK-ILLEGAL-LABEL:  Const6:
 ; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL6]]
 ; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL6]]]
 
 
 define half @Const7() {
 entry:
   ret half 0xH5000
 }
 ; CHECK-ILLEGAL:        .[[LBL7:LCPI7_[0-9]]]:
-; CHECK-ILLEGAL-NEXT:   .hword  20480                   // half 32
+; CHECK-ILLEGAL-NEXT:   .hword  0x5000                 // half 32
 ; CHECK-ILLEGAL-LABEL:  Const7:
 ; CHECK-ILLEGAL:        adrp x[[NUM:[0-9]+]], .[[LBL7]]
 ; CHECK-ILLEGAL-NEXT:   ldr h0, [x[[NUM]], :lo12:.[[LBL7]]]
 
 

llvm/test/CodeGen/AArch64/win_cst_pool.ll

 ; RUN: llc < %s -mtriple=aarch64-win32-msvc | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64-win32-gnu | FileCheck -check-prefix=MINGW %s
 
 define double @double() {
   ret double 0x2000000000800001
 }
 ; CHECK:              .globl  __real@2000000000800001
 ; CHECK-NEXT:         .section        .rdata,"dr",discard,__real@2000000000800001
 ; CHECK-NEXT:         .p2align  3
 ; CHECK-NEXT: __real@2000000000800001:
-; CHECK-NEXT:         .xword   2305843009222082561
+; CHECK-NEXT:         .xword   0x2000000000800001
 ; CHECK:      double:
 ; CHECK:               adrp    x8, __real@2000000000800001
 ; CHECK-NEXT:          ldr     d0, [x8, __real@2000000000800001]
 ; CHECK-NEXT:          ret
 
 ; MINGW:              .section        .rdata,"dr"
 ; MINGW-NEXT:         .p2align  3
 ; MINGW-NEXT: [[LABEL:\.LC.*]]:
-; MINGW-NEXT:         .xword   2305843009222082561
+; MINGW-NEXT:         .xword  0x2000000000800001
 ; MINGW:      double:
 ; MINGW:               adrp    x8, [[LABEL]]
 ; MINGW-NEXT:          ldr     d0, [x8, [[LABEL]]]
 ; MINGW-NEXT:          ret

llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll

 ; CHECK-NEXT:    vrev32.16 d16, d16
 ; CHECK-NEXT:    vadd.f16 d16, d16, d17
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vstr d16, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI2_0:
-; CHECK-NEXT:    .long 3212836864 @ float -1
-; CHECK-NEXT:    .long 1065353216 @ float 1
+; CHECK-NEXT:    .long 0xbf800000 @ float -1
+; CHECK-NEXT:    .long 0x3f800000 @ float 1
 entry:
   %c = fadd <2 x float> %a, <float -1.0, float 1.0>
   %v = bitcast <2 x float> %c to <4 x half>
   %w = load <4 x half>, <4 x half>* %store
   %z = fadd <4 x half> %v, %w
   store <4 x half> %z, <4 x half>* %store
   ret void
 }

 ; CHECK-NEXT:    vrev32.16 q8, q8
 ; CHECK-NEXT:    vadd.f16 q8, q8, q9
 ; CHECK-NEXT:    vrev64.16 q8, q8
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI8_0:
-; CHECK-NEXT:    .long 3212836864 @ float -1
-; CHECK-NEXT:    .long 1065353216 @ float 1
-; CHECK-NEXT:    .long 3212836864 @ float -1
-; CHECK-NEXT:    .long 1065353216 @ float 1
+; CHECK-NEXT:    .long 0xbf800000 @ float -1
+; CHECK-NEXT:    .long 0x3f800000 @ float 1
+; CHECK-NEXT:    .long 0xbf800000 @ float -1
+; CHECK-NEXT:    .long 0x3f800000 @ float 1
 entry:
   %c = fadd <4 x float> %a, <float -1.0, float 1.0, float -1.0, float 1.0>
   %v = bitcast <4 x float> %c to <8 x half>
   %w = load <8 x half>, <8 x half>* %store
   %z = fadd <8 x half> %v, %w
   store <8 x half> %z, <8 x half>* %store
   ret void
 }

 ; CHECK-NEXT:    subs r1, r1, #1
 ; CHECK-NEXT:    sbc r2, r2, #0
 ; CHECK-NEXT:    str r2, [r0]
 ; CHECK-NEXT:    str r1, [r0, #4]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI12_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 entry:
   %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <4 x half> %z to i64
   %w = add i64 %y, -1
   store i64 %w, i64* %store
   ret void
 }
 
 define void @conv_v4f16_to_f64( <4 x half> %a, double* %store ) {
 ; CHECK-LABEL: conv_v4f16_to_f64:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldr d16, .LCPI13_0
 ; CHECK-NEXT:    vrev64.16 d17, d0
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vadd.f16 d16, d17, d16
 ; CHECK-NEXT:    vmov.f64 d17, #-1.000000e+00
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vadd.f64 d16, d16, d17
 ; CHECK-NEXT:    vstr d16, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI13_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 entry:
   %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <4 x half> %z to double
   %w = fadd double %y, -1.0
   store double %w, double* %store
   ret void
 }
 

 ; CHECK-NEXT:    vrev32.16 d16, d16
 ; CHECK-NEXT:    vadd.i32 d16, d16, d17
 ; CHECK-NEXT:    vrev64.32 d16, d16
 ; CHECK-NEXT:    vstr d16, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI14_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 ; CHECK-NEXT:  .LCPI14_1:
 ; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
 ; CHECK-NEXT:    .long 1 @ 0x1
 entry:
   %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <4 x half> %z to <2 x i32>
   %w = add <2 x i32> %y, <i32 -1, i32 1>
   store <2 x i32> %w, <2 x i32>* %store

 ; CHECK-NEXT:    vrev32.16 d16, d16
 ; CHECK-NEXT:    vadd.f32 d16, d16, d17
 ; CHECK-NEXT:    vrev64.32 d16, d16
 ; CHECK-NEXT:    vstr d16, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI15_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 ; CHECK-NEXT:  .LCPI15_1:
-; CHECK-NEXT:    .long 3212836864 @ float -1
-; CHECK-NEXT:    .long 1065353216 @ float 1
+; CHECK-NEXT:    .long 0xbf800000 @ float -1
+; CHECK-NEXT:    .long 0x3f800000 @ float 1
 entry:
   %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <4 x half> %z to <2 x float>
   %w = fadd <2 x float> %y, <float -1.0, float 1.0>
   store <2 x float> %w, <2 x float>* %store
   ret void
 }
 
 define void @conv_v4f16_to_v4i16( <4 x half> %a, <4 x i16>* %store ) {
 ; CHECK-LABEL: conv_v4f16_to_v4i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldr d16, .LCPI16_0
 ; CHECK-NEXT:    vrev64.16 d17, d0
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vadd.f16 d16, d17, d16
 ; CHECK-NEXT:    vldr d17, .LCPI16_1
 ; CHECK-NEXT:    vrev64.16 d17, d17
 ; CHECK-NEXT:    vadd.i16 d16, d16, d17
 ; CHECK-NEXT:    vrev64.16 d16, d16
 ; CHECK-NEXT:    vstr d16, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI16_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 ; CHECK-NEXT:  .LCPI16_1:
 ; CHECK-NEXT:    .short 65535 @ 0xffff
 ; CHECK-NEXT:    .short 1 @ 0x1
 ; CHECK-NEXT:    .short 0 @ 0x0
 ; CHECK-NEXT:    .short 7 @ 0x7
 entry:
   %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <4 x half> %z to <4 x i16>

 ; CHECK-NEXT:    vrev16.8 d16, d16
 ; CHECK-NEXT:    vadd.i8 d16, d16, d17
 ; CHECK-NEXT:    vrev64.8 d16, d16
 ; CHECK-NEXT:    vstr d16, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 3
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI17_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 entry:
   %z = fadd <4 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <4 x half> %z to <8 x i8>
   %w = add <8 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   store <8 x i8> %w, <8 x i8>* %store
   ret void
 }
 

 ; CHECK-NEXT:    sbc r1, r1, #0
 ; CHECK-NEXT:    stm r0, {r1, r3}
 ; CHECK-NEXT:    str r2, [r0, #8]
 ; CHECK-NEXT:    str r12, [r0, #12]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI18_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 entry:
   %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <8 x half> %z to i128
   %w = add i128 %y, -1
   store i128 %w, i128* %store
   ret void
 }
 

 ; CHECK-NEXT:    vmov.f64 d19, #-1.000000e+00
 ; CHECK-NEXT:    vadd.f64 d21, d17, d18
 ; CHECK-NEXT:    vadd.f64 d20, d16, d19
 ; CHECK-NEXT:    vst1.64 {d20, d21}, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI19_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 entry:
   %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <8 x half> %z to <2 x double>
   %w = fadd <2 x double> %y, <double -1.0, double 1.0>
   store <2 x double> %w, <2 x double>* %store
   ret void
 }
 

 ; CHECK-NEXT:    vrev32.16 q8, q8
 ; CHECK-NEXT:    vadd.i32 q8, q8, q9
 ; CHECK-NEXT:    vrev64.32 q8, q8
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI20_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 ; CHECK-NEXT:  .LCPI20_1:
 ; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
 ; CHECK-NEXT:    .long 1 @ 0x1
 ; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
 ; CHECK-NEXT:    .long 1 @ 0x1
 entry:
   %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <8 x half> %z to <4 x i32>

 ; CHECK-NEXT:    vrev32.16 q8, q8
 ; CHECK-NEXT:    vadd.f32 q8, q8, q9
 ; CHECK-NEXT:    vrev64.32 q8, q8
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI21_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 ; CHECK-NEXT:  .LCPI21_1:
-; CHECK-NEXT:    .long 3212836864 @ float -1
-; CHECK-NEXT:    .long 1065353216 @ float 1
-; CHECK-NEXT:    .long 3212836864 @ float -1
-; CHECK-NEXT:    .long 1065353216 @ float 1
+; CHECK-NEXT:    .long 0xbf800000 @ float -1
+; CHECK-NEXT:    .long 0x3f800000 @ float 1
+; CHECK-NEXT:    .long 0xbf800000 @ float -1
+; CHECK-NEXT:    .long 0x3f800000 @ float 1
 entry:
   %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <8 x half> %z to <4 x float>
   %w = fadd <4 x float> %y, <float -1.0, float 1.0, float -1.0, float 1.0>
   store <4 x float> %w, <4 x float>* %store
   ret void
 }
 

 ; CHECK-NEXT:    vrev64.16 q9, q9
 ; CHECK-NEXT:    vadd.i16 q8, q8, q9
 ; CHECK-NEXT:    vrev64.16 q8, q8
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI22_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 ; CHECK-NEXT:  .LCPI22_1:
 ; CHECK-NEXT:    .short 65535 @ 0xffff
 ; CHECK-NEXT:    .short 1 @ 0x1
 ; CHECK-NEXT:    .short 0 @ 0x0
 ; CHECK-NEXT:    .short 7 @ 0x7
 ; CHECK-NEXT:    .short 65535 @ 0xffff
 ; CHECK-NEXT:    .short 1 @ 0x1
 ; CHECK-NEXT:    .short 0 @ 0x0

 ; CHECK-NEXT:    vrev16.8 q8, q8
 ; CHECK-NEXT:    vadd.i8 q8, q8, q9
 ; CHECK-NEXT:    vrev64.8 q8, q8
 ; CHECK-NEXT:    vst1.64 {d16, d17}, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI23_0:
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
-; CHECK-NEXT:    .short 48128 @ half -1
-; CHECK-NEXT:    .short 15360 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
+; CHECK-NEXT:    .short 0xbc00 @ half -1
+; CHECK-NEXT:    .short 0x3c00 @ half 1
 entry:
   %z = fadd <8 x half> %a, <half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0, half -1.0, half 1.0>
   %y = bitcast <8 x half> %z to <16 x i8>
   %w = add <16 x i8> %y, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   store <16 x i8> %w, <16 x i8>* %store
   ret void
 }

llvm/test/CodeGen/ARM/constant-islands.ll

 ; RUN: llc -mtriple=thumbv7-linux-gnueabihf -O0 -fast-isel=0 -o - %s | FileCheck %s
 
 define void @test_no_duplicate_branches(float %in) {
 ; CHECK-LABEL: test_no_duplicate_branches:
 ; CHECK: vldr {{s[0-9]+}}, [[CONST:\.LCPI[0-9]+_[0-9]+]]
 ; CHECK: b .LBB
 ; CHECK-NOT: b .LBB
 ; CHECK: [[CONST]]:
-; CHECK-NEXT: .long 1150963712
+; CHECK-NEXT: .long 0x449a5000
 
   %tst = fcmp oeq float %in, 1234.5
 
   %chain = zext i1 %tst to i32
 
   br i1 %tst, label %true, label %false
 
 true:
   call i32 @llvm.arm.space(i32 2000, i32 undef)
   ret void
 
 false:
   ret void
 }
 
 declare i32 @llvm.arm.space(i32, i32)

llvm/test/CodeGen/ARM/constantfp.ll

 
 define arm_aapcs_vfpcc float @lower_fpconst_select(float %f) {
 
 ; CHECK-NO-XO-LABEL: lower_fpconst_select
 ; CHECK-NO-XO: adr [[REG:r[0-9]+]], [[LABEL:.?LCPI[0-9]+_[0-9]+]]
 ; CHECK-NO-XO: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}}
 ; CHECK-NO-XO-NOT: .rodata
 ; CHECK-NO-XO: [[LABEL]]:
-; CHECK-NO-XO: .long   1335165689
-; CHECK-NO-XO: .long   1307470632
+; CHECK-NO-XO: .long   0x4f9502f9
+; CHECK-NO-XO: .long   0x4dee6b28
 
 ; CHECK-XO-FLOAT-LABEL: lower_fpconst_select
 ; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], :lower16:[[LABEL:.?LCP[0-9]+_[0-9]+]]
 ; CHECK-XO-FLOAT: movt [[REG]], :upper16:[[LABEL]]
 ; CHECK-XO-FLOAT: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}}
 ; CHECK-XO-FLOAT: .rodata
 ; CHECK-XO-FLOAT-NOT: .text
 ; CHECK-XO-FLOAT: [[LABEL]]:
-; CHECK-XO-FLOAT: .long   1335165689
-; CHECK-XO-FLOAT: .long   1307470632
+; CHECK-XO-FLOAT: .long   0x4f9502f9
+; CHECK-XO-FLOAT: .long   0x4dee6b28
 
 ; CHECK-XO-ROPI-LABEL: lower_fpconst_select
 ; CHECK-XO-ROPI: movw [[REG:r[0-9]+]], :lower16:([[LABEL1:.?LCP[0-9]+_[0-9]+]]-([[LABEL2:.?LPC[0-9]+_[0-9]+]]+4))
 ; CHECK-XO-ROPI: movt [[REG]], :upper16:([[LABEL1]]-([[LABEL2]]+4))
 ; CHECK-XO-ROPI: [[LABEL2]]:
 ; CHECK-XO-ROPI: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}}
 ; CHECK-XO-ROPI: .rodata
 ; CHECK-XO-ROPI-NOT: .text
 ; CHECK-XO-ROPI: [[LABEL1]]:
-; CHECK-XO-ROPI: .long   1335165689
-; CHECK-XO-ROPI: .long   1307470632
+; CHECK-XO-ROPI: .long   0x4f9502f9
+; CHECK-XO-ROPI: .long   0x4dee6b28
 
   %cmp = fcmp nnan oeq float %f, 0.000000e+00
   %sel = select i1 %cmp, float 5.000000e+08, float 5.000000e+09
   ret float %sel
 }

llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll

 ; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vadd.f32 s0, s2, s0
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    pop {r11, lr}
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a)
   ret half %b
 }
 
 define float @test_v1f32(<1 x float> %a) nounwind {
 ; CHECK-LABEL: test_v1f32:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI1_0
 ; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vadd.f32 s0, s2, s0
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI1_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a)
   ret float %b
 }
 
 define double @test_v1f64(<1 x double> %a) nounwind {
 ; CHECK-LABEL: test_v1f64:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov.i32 d16, #0x0

 ; CHECK-NEXT:    vadd.f32 s0, s4, s0
 ; CHECK-NEXT:    vadd.f32 s0, s0, s5
 ; CHECK-NEXT:    vadd.f32 s0, s0, s6
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI4_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a)
   ret float %b
 }
 
 define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
 ; CHECK-LABEL: test_v2f128:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r4, r5, r11, lr}

 ; CHECK-NEXT:    vadd.f32 s0, s0, s5
 ; CHECK-NEXT:    vadd.f32 s0, s0, s6
 ; CHECK-NEXT:    vadd.f32 s0, s0, s7
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI6_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a)
   ret float %b
 }

llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll

 ; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    pop {r11, lr}
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half 0.0, <1 x half> %a)
   ret half %b
 }
 
 define float @test_v1f32(<1 x float> %a) nounwind {
 ; CHECK-LABEL: test_v1f32:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vldr s0, .LCPI1_0
 ; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI1_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float 0.0, <1 x float> %a)
   ret float %b
 }
 
 define double @test_v1f64(<1 x double> %a) nounwind {
 ; CHECK-LABEL: test_v1f64:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov.i32 d16, #0x0

 ; CHECK-NEXT:    vmul.f32 s0, s4, s0
 ; CHECK-NEXT:    vmul.f32 s0, s0, s5
 ; CHECK-NEXT:    vmul.f32 s0, s0, s6
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI4_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float 0.0, <3 x float> %a)
   ret float %b
 }
 
 define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
 ; CHECK-LABEL: test_v2f128:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r4, r5, r11, lr}

 ; CHECK-NEXT:    vmul.f32 s0, s0, s5
 ; CHECK-NEXT:    vmul.f32 s0, s0, s6
 ; CHECK-NEXT:    vmul.f32 s0, s0, s7
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    mov pc, lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI6_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
   %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float 0.0, <16 x float> %a)
   ret float %b
 }

llvm/test/CodeGen/Mips/cconv/memory-layout.ll

 
 ; ALL:           .p2align 2
 ; ALL-LABEL: word:
 ; ALL:           .4byte 16909060
 ; ALL:           .size word, 4
 
 ; ALL:           .p2align 2
 ; ALL-LABEL: float:
-; ALL:           .4byte 1065353216
+; ALL:           .4byte 0x3f800000
 ; ALL:           .size float, 4
 
 ; ALL:           .p2align 3
 ; ALL-LABEL: dword:
 ; ALL:           .8byte 283686952306183
 ; ALL:           .size dword, 8
 
 ; ALL:           .p2align 3
 ; ALL-LABEL: double:
-; ALL:           .8byte 4607182418800017408
+; ALL:           .8byte 0x3ff0000000000000
 ; ALL:           .size double, 8
 
 ; O32:           .p2align 2
 ; N32:           .p2align 2
 ; N64:           .p2align 3
 ; ALL-LABEL: pointer:
 ; O32:           .4byte byte
 ; O32:           .size pointer, 4

 ; ALL:           .p2align 2
 ; ALL-LABEL: word_array:
 ; ALL:           .4byte 1
 ; ALL:           .4byte 2
 ; ALL:           .size word_array, 8
 
 ; ALL:           .p2align 2
 ; ALL-LABEL: float_array:
-; ALL:           .4byte 1065353216
-; ALL:           .4byte 1073741824
+; ALL:           .4byte 0x3f800000
+; ALL:           .4byte 0x40000000
 ; ALL:           .size float_array, 8
 
 ; ALL:           .p2align 3
 ; ALL-LABEL: dword_array:
 ; ALL:           .8byte 1
 ; ALL:           .8byte 2
 ; ALL:           .size dword_array, 16
 
 ; ALL:           .p2align 3
 ; ALL-LABEL: double_array:
-; ALL:           .8byte 4607182418800017408
-; ALL:           .8byte 4611686018427387904
+; ALL:           .8byte 0x3ff0000000000000
+; ALL:           .8byte 0x4000000000000000
 ; ALL:           .size double_array, 16
 
 ; O32:           .p2align 2
 ; N32:           .p2align 2
 ; N64:           .p2align 3
 ; ALL-LABEL: pointer_array:
 ; O32:           .4byte byte
 ; O32:           .4byte byte
 ; O32:           .size pointer_array, 8
 ; N32:           .4byte byte
 ; N32:           .4byte byte
 ; N32:           .size pointer_array, 8
 ; N64:           .8byte byte
 ; N64:           .8byte byte
 ; N64:           .size pointer_array, 16
 
 %mixed = type { i8, double, i16 }
 @mixed = global %mixed { i8 1, double 1.0, i16 515 }, align 1
 
 ; ALL:           .p2align 3
 ; ALL-LABEL: mixed:
 ; ALL:           .byte 1
 ; ALL:           .space 7
-; ALL:           .8byte 4607182418800017408
+; ALL:           .8byte 0x3ff0000000000000
 ; ALL:           .2byte 515
 ; ALL:           .space 6
 ; ALL:           .size mixed, 24
 
 ; Bitfields are not available in LLVM IR so we can't test them here.

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %const.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
 
 ; 32SMALL-ASM:         .csect .rodata[RO]
 ; 32SMALL-ASM:         .align  2
 ; 32SMALL-ASM: .LCPI0_0:
-; 32SMALL-ASM:         .long  1085276160
+; 32SMALL-ASM:         .long  0x40b00000
 ; 32SMALL-ASM: .test_float:
 ; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
 ; 32LARGE-ASM:         .csect .rodata[RO]
 ; 32LARGE-ASM:         .align  2
 ; 32LARGE-ASM: .LCPI0_0:
-; 32LARGE-ASM:         .long   1085276160
+; 32LARGE-ASM:         .long   0x40b00000
 ; 32LARGE-ASM: .test_float:
 ; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
 ; 64SMALL-ASM:         .csect .rodata[RO]
 ; 64SMALL-ASM:         .align  2
 ; 64SMALL-ASM: .LCPI0_0:
-; 64SMALL-ASM:         .long   1085276160
+; 64SMALL-ASM:         .long   0x40b00000
 ; 64SMALL-ASM: .test_float:
 ; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
 ; 64LARGE-ASM:         .csect .rodata[RO]
 ; 64LARGE-ASM:         .align  2
 ; 64LARGE-ASM: .LCPI0_0:
-; 64LARGE-ASM:         .long   1085276160
+; 64LARGE-ASM:         .long   0x40b00000
 ; 64LARGE-ASM: .test_float:
 ; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
 ; CHECK: .toc
 ; CHECK: .tc .LCPI0_0[TC],.LCPI0_0

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

 ; CHECK:      .globl  svar
 ; CHECK-NEXT: .align  1
 ; CHECK-NEXT: svar:
 ; CHECK-NEXT: .short  37
 
 ; CHECK:      .globl  fvar
 ; CHECK-NEXT: .align  2
 ; CHECK-NEXT: fvar:
-; CHECK-NEXT: .long   1145569280
+; CHECK-NEXT: .long   0x44480000
 
 ; CHECK:      .globl  dvar
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: dvar:
-; CHECK-NEXT: .llong  4651127699538968576
+; CHECK-NEXT: .llong  0x408c200000000000
 
 ; CHECK:      .globl  over_aligned
 ; CHECK-NEXT: .align  5
 ; CHECK-NEXT: over_aligned:
-; CHECK-NEXT: .llong  4651127699538968576
+; CHECK-NEXT: .llong  0x408c200000000000
 
 ; CHECK:      .globl  chrarray
 ; CHECK-NEXT: chrarray:
 ; CHECK-NEXT: .byte   97
 ; CHECK-NEXT: .byte   98
 ; CHECK-NEXT: .byte   99
 ; CHECK-NEXT: .byte   100
 
 ; CHECK:      .globl  dblarr
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: dblarr:
-; CHECK-NEXT: .llong  4607182418800017408
-; CHECK-NEXT: .llong  4611686018427387904
-; CHECK-NEXT: .llong  4613937818241073152
-; CHECK-NEXT: .llong  4616189618054758400
+; CHECK-NEXT: .llong  0x3ff0000000000000
+; CHECK-NEXT: .llong  0x4000000000000000
+; CHECK-NEXT: .llong  0x4008000000000000
+; CHECK-NEXT: .llong  0x4010000000000000
 
 ; CHECK:      .globl  d_0
 ; CHECK-NEXT: .align 3
 ; CHECK-NEXT: d_0:
 ; CHECK-NEXT: .llong 0
 
 ; CHECK:      .globl  s_0
 ; CHECK-NEXT: .align  1

llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll

 ; CHECK-NEXT:          .llong  36
 ; CHECK-NEXT:          .globl  const_svar
 ; CHECK-NEXT:          .align  1
 ; CHECK-NEXT:  const_svar:
 ; CHECK-NEXT:          .short  37
 ; CHECK-NEXT:          .globl  const_fvar
 ; CHECK-NEXT:          .align  2
 ; CHECK-NEXT:  const_fvar:
-; CHECK-NEXT:          .long   1145569280
+; CHECK-NEXT:          .long   0x44480000
 ; CHECK-NEXT:          .globl  const_dvar
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_dvar:
-; CHECK-NEXT:          .llong  4651127699538968576
+; CHECK-NEXT:          .llong  0x408c200000000000
 ; CHECK-NEXT:          .globl  const_over_aligned
 ; CHECK-NEXT:          .align  5
 ; CHECK-NEXT:  const_over_aligned:
-; CHECK-NEXT:          .llong  4651127699538968576
+; CHECK-NEXT:          .llong  0x408c200000000000
 ; CHECK-NEXT:          .globl  const_chrarray
 ; CHECK-NEXT:  const_chrarray:
 ; CHECK-NEXT:          .byte   97
 ; CHECK-NEXT:          .byte   98
 ; CHECK-NEXT:          .byte   99
 ; CHECK-NEXT:          .byte   100
 ; CHECK-NEXT:          .globl  const_dblarr
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_dblarr:
-; CHECK-NEXT:          .llong  4607182418800017408
-; CHECK-NEXT:          .llong  4611686018427387904
-; CHECK-NEXT:          .llong  4613937818241073152
-; CHECK-NEXT:          .llong  4616189618054758400
+; CHECK-NEXT:          .llong  0x3ff0000000000000
+; CHECK-NEXT:          .llong  0x4000000000000000
+; CHECK-NEXT:          .llong  0x4008000000000000
+; CHECK-NEXT:          .llong  0x4010000000000000
 
 
 ; OBJ:      File: {{.*}}aix-xcoff-rodata.ll.tmp.o
 ; OBJ-NEXT: Format: aixcoff-rs6000
 ; OBJ-NEXT: Arch: powerpc
 ; OBJ-NEXT: AddressSize: 32bit
 ; OBJ-NEXT: FileHeader {
 ; OBJ-NEXT:   Magic: 0x1DF

llvm/test/CodeGen/PowerPC/float-asmprint.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-none-linux < %s | FileCheck %s
 
 ; Check that all current floating-point types are correctly emitted to assembly
 ; on a big-endian target. x86_fp80 can't actually print for unrelated reasons,
 ; but that's not really a problem.
 
 @var128 = global fp128 0xL00000000000000008000000000000000, align 16
 @varppc128 = global ppc_fp128 0xM80000000000000000000000000000000, align 16
 @var64 = global double -0.0, align 8
 @var32 = global float -0.0, align 4
 @var16 = global half -0.0, align 2
 
 ; CHECK: var128:
-; CHECK-NEXT: .quad -9223372036854775808      # fp128 -0
+; CHECK-NEXT: .quad 0x8000000000000000      # fp128 -0
 ; CHECK-NEXT: .quad 0
 ; CHECK-NEXT: .size
 
 ; CHECK: varppc128:
-; CHECK-NEXT: .quad -9223372036854775808      # ppc_fp128 -0
+; CHECK-NEXT: .quad 0x8000000000000000      # ppc_fp128 -0
 ; CHECK-NEXT: .quad 0
 ; CHECK-NEXT: .size
 
 ; CHECK: var64:
-; CHECK-NEXT: .quad -9223372036854775808      # double -0
+; CHECK-NEXT: .quad 0x8000000000000000      # double -0
 ; CHECK-NEXT: .size
 
 ; CHECK: var32:
-; CHECK-NEXT: .long 2147483648                # float -0
+; CHECK-NEXT: .long 0x80000000              # float -0
 ; CHECK-NEXT: .size
 
 ; CHECK: var16:
-; CHECK-NEXT: .short 32768                    # half -0
+; CHECK-NEXT: .short 0x8000                 # half -0
 ; CHECK-NEXT: .size
 

llvm/test/CodeGen/PowerPC/mcm-12.ll

 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
 ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
-; CHECK: .quad 4562098671269285104
+; CHECK: .quad 0x3f4fd4920b498cf0
 ; CHECK-LABEL: test_double_const:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 
 ; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
-; CHECK-VSX: .quad 4562098671269285104
+; CHECK-VSX: .quad 0x3f4fd4920b498cf0
 ; CHECK-VSX-LABEL: test_double_const:
 ; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l({{[0-9]+}}) 
 
 ; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]:
-; CHECK-P9: .quad 4562098671269285104
+; CHECK-P9: .quad 0x3f4fd4920b498cf0
 ; CHECK-P9-LABEL: test_double_const:
 ; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])

llvm/test/CodeGen/PowerPC/mcm-4.ll

 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
-; MEDIUM: .quad 4562098671269285104
+; MEDIUM: .quad 0x3f4fd4920b498cf0
 ; MEDIUM-LABEL: test_double_const:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
-; MEDIUM-VSX: .quad 4562098671269285104
+; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0
 ; MEDIUM-VSX-LABEL: test_double_const:
 ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
-; LARGE: .quad 4562098671269285104
+; LARGE: .quad 0x3f4fd4920b498cf0
 ; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
-; LARGE-VSX: .quad 4562098671269285104
+; LARGE-VSX: .quad 0x3f4fd4920b498cf0
 ; LARGE-VSX-LABEL: test_double_const:
 ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
 
 ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
-; MEDIUM-P9: .quad 4562098671269285104
+; MEDIUM-P9: .quad 0x3f4fd4920b498cf0
 ; MEDIUM-P9-LABEL: test_double_const:
 ; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]:
-; LARGE-P9: .quad 4562098671269285104
+; LARGE-P9: .quad 0x3f4fd4920b498cf0
 ; LARGE-P9-LABEL: test_double_const:
 ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]])

llvm/test/CodeGen/PowerPC/ppcf128-endian.ll

 declare void @test(ppc_fp128)
 
 define void @caller_const() {
 entry:
   call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)
   ret void
 }
 ; CHECK: .LCPI[[LC:[0-9]+]]_0:
-; CHECK: .long   1065353216
+; CHECK: .long   0x3f800000
 ; CHECK: .LCPI[[LC]]_1:
 ; CHECK: .long   0
 ; CHECK: @caller_const
 ; CHECK: addis [[REG0:[0-9]+]], 2, .LCPI[[LC]]_0@toc@ha
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LCPI[[LC]]_1@toc@ha
 ; CHECK: lfs 1, .LCPI[[LC]]_0@toc@l([[REG0]])
 ; CHECK: lfs 2, .LCPI[[LC]]_1@toc@l([[REG1]])
 ; CHECK: bl test

llvm/test/CodeGen/PowerPC/pr16573.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test() {
   %1 = fptrunc ppc_fp128 0xM818F2887B9295809800000000032D000 to double
   ret double %1
 }
 
-; CHECK: .quad -9111018957755033591
+; CHECK: .quad 0x818f2887b9295809
 

llvm/test/CodeGen/SystemZ/fp-const-03.ll

 ; Test loads of 32-bit floating-point constants.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define float @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: le %f0, 0([[REGISTER]])
 ; CHECK: br %r14
 ;
-; CONST: .long 1065353217
+; CONST: .long 0x3f800001
   ret float 0x3ff0000020000000
 }

llvm/test/CodeGen/SystemZ/fp-const-04.ll

 ; Test loads of 64-bit floating-point constants that can be represented
 ; as 32-bit constants.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: ldeb %f0, 0([[REGISTER]])
 ; CHECK: br %r14
 ;
-; CONST: .long 1065353217
+; CONST: .long 0x3f800001
   ret double 0x3ff0000020000000
 }

llvm/test/CodeGen/SystemZ/fp-const-05.ll

 ; Test loads of 128-bit floating-point constants that can be represented
 ; as 32-bit constants.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxeb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
 ;
-; CONST: .long 1065353217
+; CONST: .long 0x3f800001
   store fp128 0xL00000000000000003fff000002000000, fp128 *%x
   ret void
 }

llvm/test/CodeGen/SystemZ/fp-const-06.ll

 ; Test loads of 64-bit floating-point constants.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: br %r14
 ;
-; CONST: .quad 4607182419068452864
+; CONST: .quad 0x3ff0000010000000
   ret double 0x3ff0000010000000
 }

llvm/test/CodeGen/SystemZ/fp-const-07.ll

 ; Test loads of 128-bit floating-point constants that can be represented
 ; as 64-bit constants.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxdb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
 ;
-; CONST: .quad 4607182419068452864
+; CONST: .quad 0x3ff0000010000000
   store fp128 0xL00000000000000003fff000001000000, fp128 *%x
   ret void
 }

llvm/test/CodeGen/SystemZ/fp-const-08.ll

 ; Test loads of 128-bit floating-point constants.  This value would actually
 ; fit within the x86 80-bit format, so the test make sure we don't try to
 ; extend from an f80.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
 ;
-; CONST: .quad 4611404543450677248
-; CONST: .quad 576460752303423488
+; CONST: .quad 0x3fff000000000000
+; CONST: .quad 0x0800000000000000
   store fp128 0xL08000000000000003fff000000000000, fp128 *%x
   ret void
 }

llvm/test/CodeGen/SystemZ/fp-const-09.ll

 ; Test loads of 128-bit floating-point constants in which the low bit of
 ; the significand is set.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
 ; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
 ;
-; CONST: .quad 4611404543450677248
-; CONST: .quad 1
+; CONST: .quad 0x3fff000000000000
+; CONST: .quad 0x0000000000000001
   store fp128 0xL00000000000000013fff000000000000, fp128 *%x
   ret void
 }

llvm/test/CodeGen/SystemZ/fp-const-10.ll

 ; Test loads of SNaN.
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; Test that we don't do an FP extending load, as this would result in a
 ; converstion to QNaN.
 define double @f1() {
 ; CHECK-LABEL: .LCPI0_0
-; CHECK:      .quad   9219994337134247936
+; CHECK:      .quad   0x7ff4000000000000
 ; CHECK-LABEL: f1:
 ; CHECK:      larl    %r1, .LCPI0_0
 ; CHECK-NOT:  ldeb    %f0, 0(%r1)
 ; CHECK:      ld      %f0, 0(%r1)
   ret double 0x7FF4000000000000
 }

llvm/test/CodeGen/SystemZ/fp-const-11.ll

 ; actually fit within the 32-bit format, but we don't have extending
 ; loads into vector registers.
 define void @f3(fp128 *%x) {
 ; CHECK-LABEL: f3:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: vl [[REG:%v[0-9]+]], 0([[REGISTER]])
 ; CHECK: vst [[REG]], 0(%r2)
 ; CHECK: br %r14
-; CONST: .quad 4611404543484231680
-; CONST: .quad 0
+; CONST: .quad 0x3fff000002000000
+; CONST: .quad 0x0
   store fp128 0xL00000000000000003fff000002000000, fp128 *%x
   ret void
 }
 
 ; Test that VGBM works.
 define void @f4(fp128 *%x) {
 ; CHECK-LABEL: f4:
 ; CHECK:      vgbm %v0, 21845

llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

 ; CHECK-NEXT:    pop {r7, pc}
 ; CHECK-NEXT:  .LBB1_4:
 ; CHECK-NEXT:    vldr s0, .LCPI1_0
 ; CHECK-NEXT:    @ kill: def $s0 killed $s0 killed $q0
 ; CHECK-NEXT:    pop {r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.5:
 ; CHECK-NEXT:  .LCPI1_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %vector.ph
 
 vector.ph:                                        ; preds = %entry
   %n.rnd.up = add i32 %N, 3
   %n.vec = and i32 %n.rnd.up, -4
   %trip.count.minus.1 = add i32 %N, -1

 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  @ %bb.24:
 ; CHECK-NEXT:  .LCPI2_1:
 ; CHECK-NEXT:    .long 0 @ 0x0
 ; CHECK-NEXT:    .long 1 @ 0x1
 ; CHECK-NEXT:    .long 2 @ 0x2
 ; CHECK-NEXT:    .long 3 @ 0x3
 ; CHECK-NEXT:  .LCPI2_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %vector.ph
 
 vector.ph:                                        ; preds = %entry
   %n.rnd.up = add i32 %N, 3
   %n.vec = and i32 %n.rnd.up, -4
   %trip.count.minus.1 = add i32 %N, -1

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll

 ; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    le lr, .LBB9_8
 ; CHECK-NEXT:  .LBB9_9: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.10:
 ; CHECK-NEXT:  .LCPI9_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
 
 for.body.preheader:                               ; preds = %entry
   %0 = add i32 %N, -1
   %xtraiter = and i32 %N, 3
   %1 = icmp ult i32 %0, 3

 ; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    le lr, .LBB10_8
 ; CHECK-NEXT:  .LBB10_9: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.10:
 ; CHECK-NEXT:  .LCPI10_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %cmp9 = icmp eq i32 %N, 0
   br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader
 
 for.body.preheader:                               ; preds = %entry
   %0 = add i32 %N, -1
   %xtraiter = and i32 %N, 3
   %1 = icmp ult i32 %0, 3

 ; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    le lr, .LBB11_8
 ; CHECK-NEXT:  .LBB11_9: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.10:
 ; CHECK-NEXT:  .LCPI11_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %cmp10 = icmp eq i32 %N, 0
   br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader
 
 for.body.preheader:                               ; preds = %entry
   %0 = add i32 %N, -1
   %xtraiter = and i32 %N, 3
   %1 = icmp ult i32 %0, 3

llvm/test/CodeGen/Thumb2/aligned-constants.ll

 ; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-ios"
 
 ; The double in the constant pool is 8-byte aligned, forcing the function
 ; alignment.
 ; CHECK: .p2align 3
 ; CHECK: func
 ;
 ; Constant pool with 8-byte entry before 4-byte entry:
 ; CHECK: .p2align 3
 ; CHECK: LCPI
 ; CHECK:  .long 2370821947
 ; CHECK:  .long 1080815255
 ; CHECK: LCPI
-; CHECK:  .long 1123477881
+; CHECK:  .long 0x42f6e979
 define void @func(float* nocapture %x, double* nocapture %y) nounwind ssp {
 entry:
   %0 = load float, float* %x, align 4
   %add = fadd float %0, 0x405EDD2F20000000
   store float %add, float* %x, align 4
   %1 = load double, double* %y, align 4
   %add1 = fadd double %1, 2.234560e+02
   store double %add1, double* %y, align 4
   ret void
 }

llvm/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-ios %s -o - | FileCheck %s
 
 @g0 = common global i32 0, align 4
 @d0 = common global double 0.000000e+00, align 8
 @f0 = common global float 0.000000e+00, align 4
 @g1 = common global i32 0, align 4
 
 declare i32 @llvm.arm.space(i32, i32)
 
 ; Check that the constant island pass moves the float constant pool entry inside
 ; the function.
 
-; CHECK: .long 1067320814 @ float 1.23455596
+; CHECK: .long 0x3f9e05ee @ float 1.23455596
 ; CHECK: {{.*}} %do.end
 
 define i32 @testpadding(i32 %a) {
 entry:
   %0 = load i32, i32* @g0, align 4
   %add = add nsw i32 %0, 12
   store i32 %add, i32* @g0, align 4
   %1 = load double, double* @d0, align 8

llvm/test/CodeGen/Thumb2/mve-ctlz.ll

 ; CHECK-NEXT:    vmov s4, r1
 ; CHECK-NEXT:    vldr s5, .LCPI0_0
 ; CHECK-NEXT:    vmov.f32 s7, s5
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){
 ; CHECK-LABEL: ctlz_4i32_0_t:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vmov s4, r1
 ; CHECK-NEXT:    vldr s5, .LCPI4_0
 ; CHECK-NEXT:    vmov.f32 s7, s5
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI4_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){
 ; CHECK-LABEL: ctlz_4i32_1_t:
 ; CHECK:       @ %bb.0: @ %entry

llvm/test/CodeGen/Thumb2/mve-ctpop.ll

 ; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    add.w r0, r2, r1, lsr #24
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vmov.f32 s3, s1
 ; CHECK-NEXT:    pop {r4, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @ctpop_4i32_t(<4 x i32> %src){
 ; CHECK-LABEL: ctpop_4i32_t:
 ; CHECK:       @ %bb.0: @ %entry

llvm/test/CodeGen/Thumb2/mve-cttz.ll

 ; CHECK-NEXT:    vmov s4, r1
 ; CHECK-NEXT:    vldr s5, .LCPI0_0
 ; CHECK-NEXT:    vmov.f32 s7, s5
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_0_t(<4 x i32> %src){
 ; CHECK-LABEL: cttz_4i32_0_t:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vmov s4, r1
 ; CHECK-NEXT:    vldr s5, .LCPI4_0
 ; CHECK-NEXT:    vmov.f32 s7, s5
 ; CHECK-NEXT:    vmov q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI4_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1)
   ret <2 x i64> %0
 }
 
 define arm_aapcs_vfpcc <4 x i32> @cttz_4i32_1_t(<4 x i32> %src){
 ; CHECK-LABEL: cttz_4i32_1_t:
 ; CHECK:       @ %bb.0: @ %entry

llvm/test/CodeGen/Thumb2/mve-phireg.ll

 ; CHECK-NEXT:    vstrw.32 q7, [r0]
 ; CHECK-NEXT:    str.w r8, [sp, #356]
 ; CHECK-NEXT:  .LBB1_1: @ %for.cond
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    b .LBB1_1
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.2:
 ; CHECK-NEXT:  .LCPI1_0:
-; CHECK-NEXT:    .long 4 @ float 5.60519386E-45
+; CHECK-NEXT:    .long 0x00000004 @ float 5.60519386E-45
 ; CHECK-NEXT:  .LCPI1_1:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %f = alloca i16, align 2
   %g = alloca [3 x [8 x [4 x i16*]]], align 4
   store i16 4, i16* %f, align 2
   %0 = load i32, i32* @c, align 4
   %1 = load i32, i32* @d, align 4
   %arrayinit.element7 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 1, i32 1
   %2 = bitcast i16** %arrayinit.element7 to i32*

llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll

 ; CHECK-NEXT:    vmov.f32 s11, s10
 ; CHECK-NEXT:    vbic q1, q1, q2
 ; CHECK-NEXT:    vand q0, q0, q2
 ; CHECK-NEXT:    vorr q0, q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI9_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0
   %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %r
 }
 
 define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {

 ; CHECK-NEXT:    vmov.f32 s11, s10
 ; CHECK-NEXT:    vbic q1, q1, q2
 ; CHECK-NEXT:    vand q0, q0, q2
 ; CHECK-NEXT:    vorr q0, q0, q1
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI10_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %c = icmp ult i32 %s, %t
   %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1
   %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
   ret <2 x i64> %r
 }
 
 define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {

llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
 
 define arm_aapcs_vfpcc float @fadd_v2f32(<2 x float> %x, float %y) {
 ; CHECK-LABEL: fadd_v2f32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vadd.f32 s0, s0, s1
 ; CHECK-NEXT:    vldr s2, .LCPI0_0
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    vadd.f32 s0, s4, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 0 @ float 0
+; CHECK-NEXT:    .long 0x00000000 @ float 0
 entry:
   %z = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float %y, <2 x float> %x)
   ret float %z
 }
 
 define arm_aapcs_vfpcc float @fadd_v4f32(<4 x float> %x, float %y) {
 ; CHECK-LABEL: fadd_v4f32:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vadd.f16 s0, s0, s2
 ; CHECK-NEXT:    vldr.16 s2, [r0]
 ; CHECK-NEXT:    vadd.f16 s0, s2, s0
 ; CHECK-NEXT:    vstr.16 s0, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI3_0:
-; CHECK-NEXT:    .short 0 @ half 0
+; CHECK-NEXT:    .short 0x0000 @ half 0
 entry:
   %y = load half, half* %yy
   %z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half %y, <4 x half> %x)
   store half %z, half* %yy
   ret void
 }
 
 define arm_aapcs_vfpcc void @fadd_v8f16(<8 x half> %x, half* %yy) {

llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP
 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16,+fp64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP
 
 ; FIXME minnum nonan X, +Inf -> X   ?
 define arm_aapcs_vfpcc float @fmin_v2f32(<2 x float> %x) {
 ; CHECK-LABEL: fmin_v2f32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldr s4, .LCPI0_0
 ; CHECK-NEXT:    vminnm.f32 s0, s0, s1
 ; CHECK-NEXT:    vminnm.f32 s0, s0, s4
 ; CHECK-NEXT:    vminnm.f32 s0, s0, s4
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
-; CHECK-NEXT:    .long 2139095040 @ float +Inf
+; CHECK-NEXT:    .long 0x7f800000 @ float +Inf
 entry:
   %z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
   ret float %z
 }
 
 define arm_aapcs_vfpcc float @fmin_v4f32(<4 x float> %x) {
 ; CHECK-LABEL: fmin_v4f32:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vstr.16 s0, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI3_0:
-; CHECK-NEXT:    .short 31744 @ half +Inf
+; CHECK-NEXT:    .short 0x7c00 @ half +Inf
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
   ret half %z
 }
 
 define arm_aapcs_vfpcc half @fmin_v8f16(<8 x half> %x) {
 ; CHECK-LABEL: fmin_v8f16:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vminnm.f32 s0, s0, s1
 ; CHECK-NEXT:    vminnm.f32 s0, s0, s6
 ; CHECK-NEXT:    vminnm.f32 s0, s0, s6
 ; CHECK-NEXT:    vminnm.f32 s0, s4, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI18_0:
-; CHECK-NEXT:    .long 2139095040 @ float +Inf
+; CHECK-NEXT:    .long 0x7f800000 @ float +Inf
 entry:
   %z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
   %c = fcmp fast olt float %y, %z
   %r = select i1 %c, float %y, float %z
   ret float %r
 }
 
 define arm_aapcs_vfpcc float @fmin_v4f32_acc(<4 x float> %x, float %y) {

 ; CHECK-NEXT:    vminnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vldr.16 s2, [r0]
 ; CHECK-NEXT:    vminnm.f16 s0, s2, s0
 ; CHECK-NEXT:    vstr.16 s0, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI21_0:
-; CHECK-NEXT:    .short 31744 @ half +Inf
+; CHECK-NEXT:    .short 0x7c00 @ half +Inf
 entry:
   %y = load half, half* %yy
   %z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x)
   %c = fcmp fast olt half %y, %z
   %r = select i1 %c, half %y, half %z
   store half %r, half* %yy
   ret void
 }

 ; CHECK-NEXT:    vldr s4, .LCPI36_0
 ; CHECK-NEXT:    vmaxnm.f32 s0, s0, s1
 ; CHECK-NEXT:    vmaxnm.f32 s0, s0, s4
 ; CHECK-NEXT:    vmaxnm.f32 s0, s0, s4
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI36_0:
-; CHECK-NEXT:    .long 4286578688 @ float -Inf
+; CHECK-NEXT:    .long 0xff800000 @ float -Inf
 entry:
   %z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
   ret float %z
 }
 
 define arm_aapcs_vfpcc float @fmax_v4f32(<4 x float> %x) {
 ; CHECK-LABEL: fmax_v4f32:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vstr.16 s0, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI39_0:
-; CHECK-NEXT:    .short 64512 @ half -Inf
+; CHECK-NEXT:    .short 0xfc00 @ half -Inf
 entry:
   %z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x)
   ret half %z
 }
 
 define arm_aapcs_vfpcc half @fmax_v8f16(<8 x half> %x) {
 ; CHECK-LABEL: fmax_v8f16:
 ; CHECK:       @ %bb.0: @ %entry

 ; CHECK-NEXT:    vmaxnm.f32 s0, s0, s1
 ; CHECK-NEXT:    vmaxnm.f32 s0, s0, s6
 ; CHECK-NEXT:    vmaxnm.f32 s0, s0, s6
 ; CHECK-NEXT:    vmaxnm.f32 s0, s4, s0
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI54_0:
-; CHECK-NEXT:    .long 4286578688 @ float -Inf
+; CHECK-NEXT:    .long 0xff800000 @ float -Inf
 entry:
   %z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
   %c = fcmp fast ogt float %y, %z
   %r = select i1 %c, float %y, float %z
   ret float %r
 }
 
 define arm_aapcs_vfpcc float @fmax_v4f32_acc(<4 x float> %x, float %y) {

 ; CHECK-NEXT:    vmaxnm.f16 s0, s0, s2
 ; CHECK-NEXT:    vldr.16 s2, [r0]
 ; CHECK-NEXT:    vmaxnm.f16 s0, s2, s0
 ; CHECK-NEXT:    vstr.16 s0, [r0]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 1
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI57_0:
-; CHECK-NEXT:    .short 64512 @ half -Inf
+; CHECK-NEXT:    .short 0xfc00 @ half -Inf
 entry:
   %y = load half, half* %yy
   %z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x)
   %c = fcmp fast ogt half %y, %z
   %r = select i1 %c, half %y, half %z
   store half %r, half* %yy
   ret void
 }

llvm/test/CodeGen/WebAssembly/global.ll

 ; CHECK-NEXT: f32ud:
 ; CHECK-NEXT: .skip 4{{$}}
 ; CHECK-NEXT: .size f32ud, 4{{$}}
 @f32ud = internal global float undef
 
 ; CHECK: .type f32nil,@object
 ; CHECK: .p2align 2{{$}}
 ; CHECK-NEXT: f32nil:
-; CHECK-NEXT: .int32 0{{$}}
+; CHECK-NEXT: .int32 0x00000000{{$}}
 ; CHECK-NEXT: .size f32nil, 4{{$}}
 @f32nil = internal global float zeroinitializer
 
 ; CHECK: .type f32z,@object
 ; CHECK: .p2align 2{{$}}
 ; CHECK-NEXT: f32z:
-; CHECK-NEXT: .int32 0{{$}}
+; CHECK-NEXT: .int32 0x00000000{{$}}
 ; CHECK-NEXT: .size f32z, 4{{$}}
 @f32z = internal global float 0.0
 
 ; CHECK: .type f32nz,@object
 ; CHECK: .p2align 2{{$}}
 ; CHECK: f32nz:
-; CHECK: .int32 2147483648{{$}}
+; CHECK: .int32 0x80000000{{$}}
 ; CHECK: .size f32nz, 4{{$}}
 @f32nz = internal global float -0.0
 
 ; CHECK: .type f32two,@object
 ; CHECK: .p2align 2{{$}}
 ; CHECK-NEXT: f32two:
-; CHECK-NEXT: .int32 1073741824{{$}}
+; CHECK-NEXT: .int32 0x40000000{{$}}
 ; CHECK-NEXT: .size f32two, 4{{$}}
 @f32two = internal global float 2.0
 
 ; CHECK: .type f64ud,@object
 ; CHECK: .p2align 3{{$}}
 ; CHECK-NEXT: f64ud:
 ; CHECK-NEXT: .skip 8{{$}}
 ; CHECK-NEXT: .size f64ud, 8{{$}}
 @f64ud = internal global double undef
 
 ; CHECK: .type f64nil,@object
 ; CHECK: .p2align 3{{$}}
 ; CHECK-NEXT: f64nil:
-; CHECK-NEXT: .int64 0{{$}}
+; CHECK-NEXT: .int64 0x0000000000000000{{$}}
 ; CHECK-NEXT: .size f64nil, 8{{$}}
 @f64nil = internal global double zeroinitializer
 
 ; CHECK: .type f64z,@object
 ; CHECK: .p2align 3{{$}}
 ; CHECK-NEXT: f64z:
-; CHECK-NEXT: .int64 0{{$}}
+; CHECK-NEXT: .int64 0x0000000000000000{{$}}
 ; CHECK-NEXT: .size f64z, 8{{$}}
 @f64z = internal global double 0.0
 
 ; CHECK: .type f64nz,@object
 ; CHECK: .p2align 3{{$}}
 ; CHECK-NEXT: f64nz:
-; CHECK-NEXT: .int64 -9223372036854775808{{$}}
+; CHECK-NEXT: .int64 0x8000000000000000{{$}}
 ; CHECK-NEXT: .size f64nz, 8{{$}}
 @f64nz = internal global double -0.0
 
 ; CHECK: .type f64two,@object
 ; CHECK: .p2align 3{{$}}
 ; CHECK-NEXT: f64two:
-; CHECK-NEXT: .int64 4611686018427387904{{$}}
+; CHECK-NEXT: .int64 0x4000000000000000{{$}}
 ; CHECK-NEXT: .size f64two, 8{{$}}
 @f64two = internal global double 2.0
 
 ; Indexing into a global array produces a relocation.
 ; CHECK:      .type arr,@object
 ; CHECK:      .type ptr,@object
 ; CHECK:      ptr:
 ; CHECK-NEXT: .int32 arr+80

llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll

 ; AVX512F-64-NEXT:    retq
   %res1 = fadd <8 x double> <double 2.0, double 1.0, double 2.0, double 1.0, double 2.0, double 1.0, double 2.0, double 1.0>, %a
   %res2 = fdiv <8 x double> <double 2.0, double 1.0, double 2.0, double 1.0, double 2.0, double 1.0, double 2.0, double 1.0>, %res1
   ret <8 x double> %res2
 }
 
 
 ; AVX512:       .LCPI37
-; AVX512-NEXT:  .quad 4616189618054758400     # double 4
-; AVX512-NEXT:  .quad 4607182418800017408     # double 1
-; AVX512-NEXT:  .quad 4611686018427387904     # double 2
-; AVX512-NEXT:  .quad 4613937818241073152     # double 3
+; AVX512-NEXT:  .quad 0x4010000000000000      # double 4
+; AVX512-NEXT:  .quad 0x3ff0000000000000      # double 1
+; AVX512-NEXT:  .quad 0x4000000000000000      # double 2
+; AVX512-NEXT:  .quad 0x4008000000000000      # double 3
 ; AVX512-NOT:   .quad
 
 define <8 x double> @f8xf64_f256(<8 x double> %a) {
 ; AVX-LABEL: f8xf64_f256:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vmovapd {{.*#+}} ymm2 = [4.0E+0,1.0E+0,2.0E+0,3.0E+0]
 ; AVX-NEXT:    vaddpd %ymm2, %ymm1, %ymm1
 ; AVX-NEXT:    vaddpd %ymm2, %ymm0, %ymm0

llvm/test/CodeGen/X86/copysign-constant-magnitude.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-apple-macosx10.10.0 < %s | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
 ; The assertions are *enhanced* from update_test_checks.ll to include
 ; the constant load values because those are important.
 
 ; CHECK:        [[SIGNMASK1:L.+]]:
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 
 define double @mag_pos0_double(double %x) nounwind {
 ; CHECK-LABEL: mag_pos0_double:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call double @copysign(double 0.0, double %x)
   ret double %y
 }
 
 ; CHECK:        [[SIGNMASK2:L.+]]:
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 
 define double @mag_neg0_double(double %x) nounwind {
 ; CHECK-LABEL: mag_neg0_double:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    andps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %y = call double @copysign(double -0.0, double %x)
   ret double %y
 }
 
 ; CHECK:        [[SIGNMASK3:L.+]]:
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 ; CHECK:        [[ONE3:L.+]]:
-; CHECK-NEXT:   .quad 4607182418800017408     ## double 1
+; CHECK-NEXT:   .quad 0x3ff0000000000000     ## double 1
 
 define double @mag_pos1_double(double %x) nounwind {
 ; CHECK-LABEL: mag_pos1_double:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
 ; CHECK-NEXT:    orps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %y = call double @copysign(double 1.0, double %x)
   ret double %y
 }
 
 ; CHECK:        [[SIGNMASK4:L.+]]:
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
-; CHECK-NEXT:   .quad -9223372036854775808    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
+; CHECK-NEXT:   .quad 0x8000000000000000    ## double -0
 ; CHECK:        [[ONE4:L.+]]:
-; CHECK-NEXT:   .quad 4607182418800017408     ## double 1
-; CHECK-NEXT:   .quad 4607182418800017408     ## double 1
+; CHECK-NEXT:   .quad 0x3ff0000000000000     ## double 1
+; CHECK-NEXT:   .quad 0x3ff0000000000000     ## double 1
 
 define double @mag_neg1_double(double %x) nounwind {
 ; CHECK-LABEL: mag_neg1_double:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call double @copysign(double -1.0, double %x)
   ret double %y
 }
 
 ; CHECK:       [[SIGNMASK5:L.+]]:
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
 
 define float @mag_pos0_float(float %x) nounwind {
 ; CHECK-LABEL: mag_pos0_float:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call float @copysignf(float 0.0, float %x)
   ret float %y
 }
 
 ; CHECK:       [[SIGNMASK6:L.+]]:
-; CHECK-NEXT:  .long 2147483648              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
 
 define float @mag_neg0_float(float %x) nounwind {
 ; CHECK-LABEL: mag_neg0_float:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    andps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %y = call float @copysignf(float -0.0, float %x)
   ret float %y
 }
 
 ; CHECK:       [[SIGNMASK7:L.+]]:
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK:        [[ONE7:L.+]]:
-; CHECK-NEXT:  .long 1065353216              ## float 1
+; CHECK-NEXT:  .long 0x3f800000              ## float 1
 
 define float @mag_pos1_float(float %x) nounwind {
 ; CHECK-LABEL: mag_pos1_float:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    orps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %y = call float @copysignf(float 1.0, float %x)
   ret float %y
 }
 
 ; CHECK:       [[SIGNMASK8:L.+]]:
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
-; CHECK-NEXT:  .long 2147483648              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
+; CHECK-NEXT:  .long 0x80000000              ## float -0
 ; CHECK:        [[ONE8:L.+]]:
-; CHECK-NEXT:  .long 1065353216              ## float 1
-; CHECK-NEXT:  .long 1065353216              ## float 1
-; CHECK-NEXT:  .long 1065353216              ## float 1
-; CHECK-NEXT:  .long 1065353216              ## float 1
+; CHECK-NEXT:  .long 0x3f800000              ## float 1
+; CHECK-NEXT:  .long 0x3f800000              ## float 1
+; CHECK-NEXT:  .long 0x3f800000              ## float 1
+; CHECK-NEXT:  .long 0x3f800000              ## float 1
 
 define float @mag_neg1_float(float %x) nounwind {
 ; CHECK-LABEL: mag_neg1_float:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    orps {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
   %y = call float @copysignf(float -1.0, float %x)
   ret float %y
 }
 
 declare double @copysign(double, double) nounwind readnone
 declare float @copysignf(float, float) nounwind readnone
 

llvm/test/CodeGen/X86/float-asmprint.ll

 ; RUN: llc -mtriple=x86_64-none-linux < %s | FileCheck %s
 
 ; Check that all current floating-point types are correctly emitted to assembly
 ; on a little-endian target.
 
 @var128 = global fp128 0xL00000000000000008000000000000000, align 16
 @varppc128 = global ppc_fp128 0xM80000000000000000000000000000000, align 16
 @var80 = global x86_fp80 0xK80000000000000000000, align 16
 @var64 = global double -0.0, align 8
 @var32 = global float -0.0, align 4
 @var16 = global half -0.0, align 2
 @var4f32 = global <4 x float> <float -0.0, float 0.0, float 1.0, float 2.0>
 @var4f16 = global <4 x half> <half -0.0, half 0.0, half 1.0, half 2.0>
 
 ; CHECK: var128:
-; CHECK-NEXT: .quad 0                         # fp128 -0
-; CHECK-NEXT: .quad -9223372036854775808
+; CHECK-NEXT: .quad 0x0000000000000000      # fp128 -0
+; CHECK-NEXT: .quad 0x8000000000000000
 ; CHECK-NEXT: .size
 
 ; CHECK: varppc128:
 ; For ppc_fp128, the high double always comes first.
-; CHECK-NEXT: .quad -9223372036854775808      # ppc_fp128 -0
-; CHECK-NEXT: .quad 0
+; CHECK-NEXT: .quad 0x8000000000000000      # ppc_fp128 -0
+; CHECK-NEXT: .quad 0x0000000000000000
 ; CHECK-NEXT: .size
 
 ; CHECK: var80:
-; CHECK-NEXT: .quad 0                         # x86_fp80 -0
-; CHECK-NEXT: .short 32768
+; CHECK-NEXT: .quad  0x0000000000000000     # x86_fp80 -0
+; CHECK-NEXT: .short 0x8000
 ; CHECK-NEXT: .zero 6
 ; CHECK-NEXT: .size
 
 ; CHECK: var64:
-; CHECK-NEXT: .quad -9223372036854775808      # double -0
+; CHECK-NEXT: .quad 0x8000000000000000      # double -0
 ; CHECK-NEXT: .size
 
 ; CHECK: var32:
-; CHECK-NEXT: .long 2147483648                # float -0
+; CHECK-NEXT: .long 0x80000000                # float -0
 ; CHECK-NEXT: .size
 
 ; CHECK: var16:
-; CHECK-NEXT: .short 32768                    # half -0
+; CHECK-NEXT: .short 0x8000                   # half -0
 ; CHECK-NEXT: .size
 
 ; CHECK: var4f32:
-; CHECK-NEXT: .long 2147483648               # float -0
-; CHECK-NEXT: .long 0                        # float 0
-; CHECK-NEXT: .long 1065353216               # float 1
-; CHECK-NEXT: .long 1073741824               # float 2
+; CHECK-NEXT: .long 0x80000000               # float -0
+; CHECK-NEXT: .long 0x00000000               # float 0
+; CHECK-NEXT: .long 0x3f800000               # float 1
+; CHECK-NEXT: .long 0x40000000               # float 2
 ; CHECK-NEXT: .size
 
 ; CHECK: var4f16:
-; CHECK-NEXT: .short 32768                    # half -0
-; CHECK-NEXT: .short 0                        # half 0
-; CHECK-NEXT: .short 15360                    # half 1
-; CHECK-NEXT: .short 16384                    # half 2
+; CHECK-NEXT: .short 0x8000                   # half -0
+; CHECK-NEXT: .short 0x0000                   # half 0
+; CHECK-NEXT: .short 0x3c00                   # half 1
+; CHECK-NEXT: .short 0x4000                   # half 2
 ; CHECK-NEXT: .size

llvm/test/CodeGen/X86/fp-immediate-shorten.ll

 ;; Test that this FP immediate is stored in the constant pool as a float.
 
 ; RUN: llc < %s -mtriple=i686-- -mattr=-sse2,-sse3 | FileCheck %s
 
-; CHECK: {{.long.1123418112}}
+; CHECK: {{.long.0x42f60000}}
 
 define double @D() {
         ret double 1.230000e+02
 }
 

llvm/test/CodeGen/X86/fp128-load.ll

 ; CHECK-LABEL: TestLoadExtend:
 ; CHECK:       movslq  %edi, %rax
 ; CHECK-NEXT:  movss   TestLoadExtend.data(,%rax,4), %xmm0
 ; CHECK-NEXT:  callq   __extendsftf2
 ; CHECK:       retq
 }
 
 ; CHECK-LABEL:  my_fp128:
-; CHECK-NEXT:  .quad   0
-; CHECK-NEXT:  .quad   4611404543450677248
+; CHECK-NEXT:  .quad   0x0
+; CHECK-NEXT:  .quad   0x3fff000000000000
 ; CHECK-NEXT:  .size   my_fp128, 16

llvm/test/CodeGen/X86/pr13577.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-darwin | FileCheck %s
 
 ; CHECK-LABEL: LCPI0_0:
-; CHECK-NEXT: .long 4286578688
+; CHECK-NEXT: .long 0xff800000
 ; CHECK-LABEL: LCPI0_1:
-; CHECK-NEXT: .long 2139095040
+; CHECK-NEXT: .long 0x7f800000
 
 define x86_fp80 @foo(x86_fp80 %a) {
 ; CHECK-LABEL: foo:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    fstpt -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    testb $-128, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    flds {{.*}}(%rip)

llvm/test/CodeGen/X86/pr40730.ll

 ; CHECK-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[0,0,3,2]
 ; CHECK-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5],ymm0[6,7]
 ; CHECK-NEXT:    retq
   %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 13, i32 12, i32 13, i32 3, i32 15, i32 1, i32 4>
   ret <8 x i32> %shuffle
 }
 
 ; CHECK:      .LCPI1_0:
-; CHECK-NEXT: .quad   60129542157
-; CHECK-NEXT: .quad   60129542157
-; CHECK-NEXT: .quad   68719476736
-; CHECK-NEXT: .quad   60129542157
+; CHECK-NEXT: .quad   0x0000000e0000000d
+; CHECK-NEXT: .quad   0x0000000e0000000d
+; CHECK-NEXT: .quad   0x0000001000000000
+; CHECK-NEXT: .quad   0x0000000e0000000d
 
 define <8 x i32> @shuffle_v8i32_0dcd3f14_constant(<8 x i32> %a0)  {
 ; CHECK-LABEL: shuffle_v8i32_0dcd3f14_constant:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; CHECK-NEXT:    vblendps {{.*#+}} xmm1 = xmm1[0],xmm0[1,2,3]
 ; CHECK-NEXT:    vpermilps {{.*#+}} xmm1 = xmm1[3,1,1,0]
 ; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; CHECK-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],mem[1,2,3],ymm0[4],mem[5],ymm0[6,7]
 ; CHECK-NEXT:    retq
   %res = shufflevector <8 x i32> %a0, <8 x i32> <i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>, <8 x i32> <i32 0, i32 13, i32 12, i32 13, i32 3, i32 15, i32 1, i32 4>
   ret <8 x i32> %res
 }

llvm/test/CodeGen/X86/vec-copysign.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.10.0 -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
 
 ; Assertions have been enhanced from utils/update_llc_test_checks.py to show the constant pool values.
 ; Use a macosx triple to make sure the format of those constant strings is exact.
 
 ; CHECK:       [[SIGNMASK1:L.+]]:
-; CHECK-NEXT:  .long 2147483648
-; CHECK-NEXT:  .long 2147483648
-; CHECK-NEXT:  .long 2147483648
-; CHECK-NEXT:  .long 2147483648
+; CHECK-NEXT:  .long 0x80000000
+; CHECK-NEXT:  .long 0x80000000
+; CHECK-NEXT:  .long 0x80000000
+; CHECK-NEXT:  .long 0x80000000
 
 ; CHECK:       [[MAGMASK1:L.+]]:
-; CHECK-NEXT:  .long 2147483647
-; CHECK-NEXT:  .long 2147483647
-; CHECK-NEXT:  .long 2147483647
-; CHECK-NEXT:  .long 2147483647
+; CHECK-NEXT:  .long 0x7fffffff
+; CHECK-NEXT:  .long 0x7fffffff
+; CHECK-NEXT:  .long 0x7fffffff
+; CHECK-NEXT:  .long 0x7fffffff
 
 define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind {
 ; SSE2-LABEL: v4f32:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    andps [[SIGNMASK1]](%rip), %xmm1
 ; SSE2-NEXT:    andps [[MAGMASK1]](%rip), %xmm0
 ; SSE2-NEXT:    orps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: v4f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vandps [[SIGNMASK1]](%rip), %xmm1, %xmm1
 ; AVX-NEXT:    vandps [[MAGMASK1]](%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
   %tmp = tail call <4 x float> @llvm.copysign.v4f32( <4 x float> %a, <4 x float> %b )
   ret <4 x float> %tmp
 }
 
 ; SSE2:       [[MAGMASK2:L.+]]:
-; SSE2-NEXT:  .long 2147483647
-; SSE2-NEXT:  .long 2147483647
-; SSE2-NEXT:  .long 2147483647
-; SSE2-NEXT:  .long 2147483647
+; SSE2-NEXT:  .long 0x7fffffff
+; SSE2-NEXT:  .long 0x7fffffff
+; SSE2-NEXT:  .long 0x7fffffff
+; SSE2-NEXT:  .long 0x7fffffff
 
 ; AVX:       [[SIGNMASK2:L.+]]:
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
-; AVX-NEXT:  .long 2147483648
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
+; AVX-NEXT:  .long 0x80000000
 
 ; AVX:       [[MAGMASK2:L.+]]:
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
-; AVX-NEXT:  .long 2147483647
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
+; AVX-NEXT:  .long 0x7fffffff
 
 define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind {
 ; SSE2-LABEL: v8f32:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    movaps [[MAGMASK2]](%rip), %xmm4
 ; SSE2-NEXT:    movaps %xmm4, %xmm5
 ; SSE2-NEXT:    andnps %xmm2, %xmm5
 ; SSE2-NEXT:    andps %xmm4, %xmm0

 ; AVX-NEXT:    vorps %ymm1, %ymm0, %ymm0
 ; AVX-NEXT:    retq
 ;
   %tmp = tail call <8 x float> @llvm.copysign.v8f32( <8 x float> %a, <8 x float> %b )
   ret <8 x float> %tmp
 }
 
 ; CHECK:        [[SIGNMASK3:L.+]]:
-; CHECK-NEXT:   .quad -9223372036854775808
-; CHECK-NEXT:   .quad -9223372036854775808
+; CHECK-NEXT:   .quad 0x8000000000000000
+; CHECK-NEXT:   .quad 0x8000000000000000
 
 ; CHECK:        [[MAGMASK3:L.+]]:
-; CHECK-NEXT:   .quad 9223372036854775807
-; CHECK-NEXT:   .quad 9223372036854775807
+; CHECK-NEXT:   .quad 0x7fffffffffffffff
+; CHECK-NEXT:   .quad 0x7fffffffffffffff
 
 define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
 ; SSE2-LABEL: v2f64:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    andps [[SIGNMASK3]](%rip), %xmm1
 ; SSE2-NEXT:    andps [[MAGMASK3]](%rip), %xmm0
 ; SSE2-NEXT:    orps %xmm1, %xmm0
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: v2f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vandps [[SIGNMASK3]](%rip), %xmm1, %xmm1
 ; AVX-NEXT:    vandps [[MAGMASK3]](%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vorps %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    retq
 ;
   %tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
   ret <2 x double> %tmp
 }
 
 ; SSE2:        [[MAGMASK4:L.+]]:
-; SSE2-NEXT:   .quad 9223372036854775807
-; SSE2-NEXT:   .quad 9223372036854775807
+; SSE2-NEXT:   .quad 0x7fffffffffffffff
+; SSE2-NEXT:   .quad 0x7fffffffffffffff
 
 ; AVX:        [[SIGNMASK4:L.+]]:
-; AVX-NEXT:   .quad -9223372036854775808
-; AVX-NEXT:   .quad -9223372036854775808
-; AVX-NEXT:   .quad -9223372036854775808
-; AVX-NEXT:   .quad -9223372036854775808
+; AVX-NEXT:   .quad 0x8000000000000000
+; AVX-NEXT:   .quad 0x8000000000000000
+; AVX-NEXT:   .quad 0x8000000000000000
+; AVX-NEXT:   .quad 0x8000000000000000
 
 ; AVX:        [[MAGMASK4:L.+]]:
-; AVX-NEXT:   .quad 9223372036854775807
-; AVX-NEXT:   .quad 9223372036854775807
-; AVX-NEXT:   .quad 9223372036854775807
-; AVX-NEXT:   .quad 9223372036854775807
+; AVX-NEXT:   .quad 0x7fffffffffffffff
+; AVX-NEXT:   .quad 0x7fffffffffffffff
+; AVX-NEXT:   .quad 0x7fffffffffffffff
+; AVX-NEXT:   .quad 0x7fffffffffffffff
 
 define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind {
 ; SSE2-LABEL: v4f64:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    movaps [[MAGMASK4]](%rip), %xmm4
 ; SSE2-NEXT:    movaps %xmm4, %xmm5
 ; SSE2-NEXT:    andnps %xmm2, %xmm5
 ; SSE2-NEXT:    andps %xmm4, %xmm0

llvm/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll

 
 ; CST: [[HIGHCSTADDR:.LCPI[0-9_]+]]:
 ; CST-NEXT: .long 1392508928 # 0x53000000
 ; CST-NEXT: .long 1392508928 # 0x53000000
 ; CST-NEXT: .long 1392508928 # 0x53000000
 ; CST-NEXT: .long 1392508928 # 0x53000000
 
 ; CST: [[MAGICCSTADDR:.LCPI[0-9_]+]]:
-; CST-NEXT: .long 1392509056 # float 5.49764202E+11
-; CST-NEXT: .long 1392509056 # float 5.49764202E+11
-; CST-NEXT: .long 1392509056 # float 5.49764202E+11
-; CST-NEXT: .long 1392509056 # float 5.49764202E+11
+; CST-NEXT: .long 0x53000080 # float 5.49764202E+11
+; CST-NEXT: .long 0x53000080 # float 5.49764202E+11
+; CST-NEXT: .long 0x53000080 # float 5.49764202E+11
+; CST-NEXT: .long 0x53000080 # float 5.49764202E+11
 
 ; AVX2: [[LOWCSTADDR:.LCPI[0-9_]+]]:
 ; AVX2-NEXT: .long 1258291200 # 0x4b000000
 
 ; AVX2: [[HIGHCSTADDR:.LCPI[0-9_]+]]:
 ; AVX2-NEXT: .long 1392508928 # 0x53000000
 
 ; AVX2: [[MAGICCSTADDR:.LCPI[0-9_]+]]:
-; AVX2-NEXT: .long 1392509056 # float 5.49764202E+11
+; AVX2-NEXT: .long 0x53000080 # float 5.49764202E+11
 
 define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) {
 ; SSE2-LABEL: test_uitofp_v4i32_to_v4f32:
 ; SSE2: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]]
 ; SSE2-NEXT: pand %xmm0, [[MASK]]
 ; After this instruction, MASK will have the value of the low parts
 ; of the vector.
 ; SSE2-NEXT: por [[LOWCSTADDR]](%rip), [[MASK]]

 ; Match the AVX2 constants used in the next function
 ; AVX2: [[LOWCSTADDR:.LCPI[0-9_]+]]:
 ; AVX2-NEXT: .long 1258291200 # 0x4b000000
 
 ; AVX2: [[HIGHCSTADDR:.LCPI[0-9_]+]]:
 ; AVX2-NEXT: .long 1392508928 # 0x53000000
 
 ; AVX2: [[MAGICCSTADDR:.LCPI[0-9_]+]]:
-; AVX2-NEXT: .long 1392509056 # float 5.49764202E+11
+; AVX2-NEXT: .long 0x53000080 # float 5.49764202E+11
 
 define <8 x float> @test_uitofp_v8i32_to_v8f32(<8 x i32> %arg) {
 ; Legalization will break the thing is 2 x <4 x i32> on anthing prior AVX.
 ; The constant used for in the vector instruction are shared between the
 ; two sequences of instructions.
 ;
 ; SSE2-LABEL: test_uitofp_v8i32_to_v8f32:
 ; SSE2: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535]

llvm/test/CodeGen/X86/vec_uint_to_fp.ll

 
 ; CST: [[HIGHCSTADDR:LCPI0_[0-9]+]]:
 ; CST-NEXT: .long 1392508928              ## 0x53000000
 ; CST-NEXT: .long 1392508928              ## 0x53000000
 ; CST-NEXT: .long 1392508928              ## 0x53000000
 ; CST-NEXT: .long 1392508928              ## 0x53000000
 
 ; CST: [[MAGICCSTADDR:LCPI0_[0-9]+]]:
-; CST-NEXT: .long 1392509056              ## float 5.49764202E+11
-; CST-NEXT: .long 1392509056              ## float 5.49764202E+11
-; CST-NEXT: .long 1392509056              ## float 5.49764202E+11
-; CST-NEXT: .long 1392509056              ## float 5.49764202E+11
+; CST-NEXT: .long 0x53000080              ## float 5.49764202E+11
+; CST-NEXT: .long 0x53000080              ## float 5.49764202E+11
+; CST-NEXT: .long 0x53000080              ## float 5.49764202E+11
+; CST-NEXT: .long 0x53000080              ## float 5.49764202E+11
 
 ; AVX2: [[LOWCSTADDR:LCPI0_[0-9]+]]:
 ; AVX2-NEXT: .long  1258291200              ## 0x4b000000
 
 ; AVX2: [[HIGHCSTADDR:LCPI0_[0-9]+]]:
 ; AVX2-NEXT: .long  1392508928              ## 0x53000000
 
 ; AVX2: [[MAGICCSTADDR:LCPI0_[0-9]+]]:
-; AVX2-NEXT: .long  1392509056              ## float 5.49764202E+11
+; AVX2-NEXT: .long  0x53000080              ## float 5.49764202E+11
 
 define <4 x float> @test1(<4 x i32> %A) nounwind {
 ; CHECK-LABEL: test1:
 ;
 ; SSE: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]]
 ; SSE-NEXT: pand %xmm0, [[MASK]]
 ; After this instruction, MASK will have the value of the low parts
 ; of the vector.

 ; Match the AVX2 constants used in the next function
 ; AVX2: [[LOWCSTADDR:LCPI1_[0-9]+]]:
 ; AVX2-NEXT: .long  1258291200              ## 0x4b000000
 
 ; AVX2: [[HIGHCSTADDR:LCPI1_[0-9]+]]:
 ; AVX2-NEXT: .long  1392508928              ## 0x53000000
 
 ; AVX2: [[MAGICCSTADDR:LCPI1_[0-9]+]]:
-; AVX2-NEXT: .long  1392509056              ## float 5.49764202E+11
+; AVX2-NEXT: .long  0x53000080              ## float 5.49764202E+11
 
 define <8 x float> @test2(<8 x i32> %A) nounwind {
 ; CHECK-LABEL: test2:
 ; Legalization will break the thing is 2 x <4 x i32> on anthing prior AVX.
 ; The constant used for in the vector instruction are shared between the
 ; two sequences of instructions.
 ;
 ; SSE: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535]

llvm/test/CodeGen/X86/win_cst_pool.ll

 ; Three variants of "MSVC" environments.
 ; RUN: llc < %s -mattr=sse2 -mattr=avx | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=sse2 -mattr=avx | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-windows-msvc -mattr=sse2 -mattr=avx | FileCheck %s
 ; GNU environment.
 ; RUN: llc < %s -mtriple=x86_64-win32-gnu -mattr=sse2 -mattr=avx | FileCheck -check-prefix=MINGW %s
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-pc-win32"
 
 define double @double() {
   ret double 0x0000000000800000
 }
 ; CHECK:              .globl  __real@0000000000800000
 ; CHECK-NEXT:         .section        .rdata,"dr",discard,__real@0000000000800000
 ; CHECK-NEXT:         .p2align  3
 ; CHECK-NEXT: __real@0000000000800000:
-; CHECK-NEXT:         .quad   8388608
+; CHECK-NEXT:         .quad   0x0000000000800000
 ; CHECK:      double:
 ; CHECK:               movsd   __real@0000000000800000(%rip), %xmm0
 ; CHECK-NEXT:          ret
 
 ; MINGW:              .section        .rdata,"dr"
 ; MINGW-NEXT:         .p2align  3
 ; MINGW-NEXT: [[LABEL:\.LC.*]]:
-; MINGW-NEXT:         .quad   8388608
+; MINGW-NEXT:         .quad   0x0000000000800000
 ; MINGW:      double:
 ; MINGW:               movsd   [[LABEL]](%rip), %xmm0
 ; MINGW-NEXT:          ret
 
 define <4 x i32> @vec1() {
   ret <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 }
 ; CHECK:              .globl  __xmm@00000000000000010000000200000003

 
 define <4 x float> @undef1() {
   ret <4 x float> <float 1.0, float 1.0, float undef, float undef>
 
 ; CHECK:             .globl  __xmm@00000000000000003f8000003f800000
 ; CHECK-NEXT:        .section        .rdata,"dr",discard,__xmm@00000000000000003f8000003f800000
 ; CHECK-NEXT:        .p2align  4
 ; CHECK-NEXT: __xmm@00000000000000003f8000003f800000:
-; CHECK-NEXT:        .long   1065353216              # float 1
-; CHECK-NEXT:        .long   1065353216              # float 1
+; CHECK-NEXT:        .long   0x3f800000              # float 1
+; CHECK-NEXT:        .long   0x3f800000              # float 1
 ; CHECK-NEXT:        .zero   4
 ; CHECK-NEXT:        .zero   4
 ; CHECK:      undef1:
 ; CHECK:               movaps  __xmm@00000000000000003f8000003f800000(%rip), %xmm0
 ; CHECK-NEXT:          ret
 }
 
 define float @pr23966(i32 %a) {
   %tobool = icmp ne i32 %a, 0
   %sel = select i1 %tobool, float -1.000000e+00, float 1.000000e+00
   ret float %sel
 }
 
 ; CHECK:              .globl  __real@bf8000003f800000
 ; CHECK-NEXT:         .section        .rdata,"dr",discard,__real@bf8000003f800000
 ; CHECK-NEXT:         .p2align  3
 ; CHECK-NEXT: __real@bf8000003f800000:
-; CHECK-NEXT:         .long   1065353216
-; CHECK-NEXT:         .long   3212836864
+; CHECK-NEXT:         .long   0x3f800000
+; CHECK-NEXT:         .long   0xbf800000
 
 define <4 x i64> @ymm() {
 entry:
   ret <4 x i64> <i64 8589934593, i64 17179869187, i64 8589934593, i64 17179869187>
 }
 
 ; CHECK:  .globl  __ymm@0000000400000003000000020000000100000004000000030000000200000001
 ; CHECK:  .section  .rdata,"dr",discard,__ymm@0000000400000003000000020000000100000004000000030000000200000001
 ; CHECK:  .p2align  5
 ; CHECK: __ymm@0000000400000003000000020000000100000004000000030000000200000001:
 ; CHECK:  .quad 8589934593              # 0x200000001
 ; CHECK:  .quad 17179869187             # 0x400000003
 ; CHECK:  .quad 8589934593              # 0x200000001
 ; CHECK:  .quad 17179869187

llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll

; CHECK-NEXT:    retq
   %result = sitofp <4 x i32> %ext to <4 x double>
   store <4 x double> %result, <4 x double>* %p
   ret void
 }
 
 ; Also test the general purpose constant folding of int->fp.
 define void @foo2(<4 x float>* noalias %result) nounwind {
 ; CHECK-LABEL: LCPI2_0:
-; CHECK-NEXT: .long 1082130432              ## float 4
-; CHECK-NEXT: .long 1084227584              ## float 5
-; CHECK-NEXT: .long 1086324736              ## float 6
-; CHECK-NEXT: .long 1088421888              ## float 7
+; CHECK-NEXT: .long 0x40800000              ## float 4
+; CHECK-NEXT: .long 0x40a00000              ## float 5
+; CHECK-NEXT: .long 0x40c00000              ## float 6
+; CHECK-NEXT: .long 0x40e00000              ## float 7
 ; CHECK-LABEL: foo2:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0]
 ; CHECK-NEXT:    movaps %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
   %val = uitofp <4 x i32> <i32 4, i32 5, i32 6, i32 7> to <4 x float>
   store <4 x float> %val, <4 x float>* %result
   ret void
; CHECK-NEXT:    retq
   %and = and <4 x i32> %ext, <i32 255, i32 256, i32 257, i32 258>
   %result = sitofp <4 x i32> %and to <4 x float>
   ret <4 x float> %result
 }
 
 ; Test the general purpose constant folding of uint->fp.
 define void @foo4(<4 x float>* noalias %result) nounwind {
 ; CHECK-LABEL: LCPI4_0:
-; CHECK-NEXT: .long 1065353216              ## float 1
-; CHECK-NEXT: .long 1123942400              ## float 127
-; CHECK-NEXT: .long 1124073472              ## float 128
-; CHECK-NEXT: .long 1132396544              ## float 255
+; CHECK-NEXT: .long 0x3f800000              ## float 1
+; CHECK-NEXT: .long 0x42fe0000              ## float 127
+; CHECK-NEXT: .long 0x43000000              ## float 128
+; CHECK-NEXT: .long 0x437f0000              ## float 255
 ; CHECK-LABEL: foo4:
 ; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [1.0E+0,1.27E+2,1.28E+2,2.55E+2]
 ; CHECK-NEXT:    movaps %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
   %val = uitofp <4 x i8> <i8 1, i8 127, i8 -128, i8 -1> to <4 x float>
   store <4 x float> %val, <4 x float>* %result
   ret void
 }