[FileCheck] Catch missspelled directives.

[kosarev]

A work in progress. Contains changes that we likely want to see addressed separately.

[jhenderson]

Code change looks good to me. Are the TODO cases where the test fails if changing them?

llvm/test/FileCheck/missspelled-directive.txt

19

What about P4-COUNT_2? Is that case not really related?

[kosarev]

In D125604#3514983, @jhenderson wrote:

Are the TODO cases where the test fails if changing them?

Yes, this and where the fix is not perfectly obvious.

llvm/test/FileCheck/missspelled-directive.txt

19

Yeah, that's intentionally left for later. At the moment I don't even know how severe the problem with COUNT_* is, need to try and see.

[thopre]

llvm/lib/FileCheck/FileCheck.cpp

1774–1781

Instead of introducing a new wrapper, why don't you change all the return to call a constructor method (e.g. make_check_type()) that does what this wrapper do? Then there would not be any FindCheckType that take a Misspelled parameter.

I'm also not sure about Misspelled being a check kind. It feels conceptually wrong but on the other hand I guess it makes the implementation simpler.

[kosarev]

llvm/lib/FileCheck/FileCheck.cpp

1774–1781

Tried that. Replacing the returned pair with a new CheckLine kind of object implementing the misspelled-related logic seems to add a lot of extra clutter such as the definition of the new structure itself, but especially all the repetitive mentions of Misspelled on every return. Feels like having it as a reference parameter works better, as we only need to alter the flag occasionally.

Regarding CheckMisspelled, now that we have CheckBadNot and CheckBadCount, this looks the usual way of propagating the information about our spelling-related concerns. Might be not the best design and may be worth looking into at some point, but at least doesn' seem to be specific to this patch?

[kosarev]

Added MLIR fixes.

[thopre]

llvm/lib/FileCheck/FileCheck.cpp

1774–1781

I was thinking something along the line of:

return getRealCheckType(CHECK::CheckBadCount, Rest, Misspelled); with:

static std::pair<Check::FileCheckType, StringRef>
getRealCheckType(Check::FileCheckType CheckType, StringRef Rest, bool Misspelled) {
  if (CheckType != Check::CheckNone && Misspelled)
    return {Check::CheckMisspelled, Rest};
  return {CheckType, Rest};
}

Fair enough for CheckMisspelled, there is indeeed precedent.

[kosarev]

llvm/lib/FileCheck/FileCheck.cpp

1774–1781

That unfortunately wouldn't eliminate the repetitive return getRealCheckType(..., Misspelled) bits, thus adding a significant amount of clutter -- all for the sake of a single assignment where we raise the flag, while also making the code more fragile as the compiler wouldn't then be able to catch returns without calling getRealCheckType(). And if that's not enough, then the name of the function sounds like we introduce one of the most irritating kinds of concepts -- the 'real' ones. :-)

[thopre]

llvm/lib/FileCheck/FileCheck.cpp

1774–1781

Fair enough. LGTM for the FileCheck part then. Have you sent a message to discourse to ask test authors for help on the TODO?

[kosarev]

llvm/lib/FileCheck/FileCheck.cpp

1774–1781

https://discourse.llvm.org/t/help-wanted-with-fixing-misspelled-filecheck-directives/62593

Thanks for the idea!

[kosarev]

Add Polly fixes.

[RKSimon]

Thanks @kosarev - CodeGen\X86 should be clean now!

[RKSimon]

llvm/test/DebugInfo/X86/debug-info-template-parameter.ll

36

Should be fixed by rGf718664866ab

[kosarev]

Tagging more people in hope to add visibility.

clang/test/CodeGen/cmse-clear-return.c

235

@momchil.velikov @chill

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

682–689

@az

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

3–5

@alex-t

llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll

13–14

@keith.walker.arm

llvm/test/CodeGen/WebAssembly/libcalls.ll

52–54

@dschuff

llvm/test/CodeGen/X86/GlobalISel/select-ext.mir

69–73

@aivchenk @plotfi @zer0

llvm/test/DebugInfo/X86/debug-info-template-parameter.ll

33–36

@awanpand

mlir/test/Conversion/MemRefToSPIRV/alloc.mlir

44

@antiagainst @levivic @zlei

[dmgreen]

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

682–689

These lines should be removed. The were accidentally left in as the file was update_llc_test_check'd

llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll

13–14

I think ; CHECK-NEXT: .long 4294965696 should be OK. That looks like it would match up with the code.

[RKSimon]

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

682–689

This was fixed in rG1584b2c74e4c804a2c85d760a1a2c10b33465f2e

[kosarev]

Added Flang fixes and rebased.

Thanks Simon for the quick turnaround!

[MaskRay]

LGTM. Thanks for pinging the relevant folks on individual tests. You can push the fixes yourself before landing this patch.

[kosarev]

Rebased on top of fixes for non-trivial cases. Going to submit this
tomorrow, if no objections.

[kosarev]

Committing this revealed some more failures, fixed in rG8894c05b0d351f998b1836542ba791247394bd12.

clang/test/CodeGen/cmse-clear-return.c

 } T14;
 
 T14 t14;
 __attribute__((cmse_nonsecure_entry)) T14 f14(void) { return t14; }
 // CHECK: define {{.*}} @f14()
 // CHECK: [[R:%.*]] = load
 // CHECK-LE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
 // CHECK-BE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK_NEXT: ret i32 [[AND]]
+// TODO-NEXT: ret i32 [[AND]]
 
 // LE: 1111..11 1111..11 11111111 11111111 0xfffff3f3/-3085
 // BE: 11..1111 11..1111 11111111 11111111 0xcfcfffff/-808452097
 typedef struct T17 {
   struct T170 {
     char a : 2;
     char   : 2, b : 4;
   } a[2];

clang/test/CodeGenCXX/attr-mustprogress.cpp

 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    br label %for.cond
 // CHECK:       for.cond:
 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* @b, align 4
 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], [[TMP1]]
 // CHECK-NEXT:    br i1 [[CMP]], label %for.body, label %for.end
 // CHECK:       for.body:
-// CXX98_NOT:     br {{.*}} !llvm.loop
+// CXX98-NOT:     br {{.*}} !llvm.loop
 // CXX11-NEXT:    br label %for.cond, !llvm.loop [[LOOP6:!.*]]
 // FINITE-NEXT:   br label %for.cond, !llvm.loop [[LOOP6:!.*]]
 // CHECK:       for.end:
 // CHECK-NEXT:    br label %for.cond1
 // CHECK:       for.cond1:
 // CHECK-NEXT:    br i1 true, label %for.body2, label %for.end3
 // CHECK:       for.body2:
 // CXX98-NOT:     br {{.*}}, !llvm.loop

clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp

 struct Container {
   ImplicitCopy b[2];
   ThrowCopy c;
 };
 
 int main () {
   try {
     Container c1;
-    // CHECK_LABEL: main
+    // CHECK-LABEL: main
     // CHECK-NOT: call void @_ZN9ThrowCopyC1ERKS_
     // CHECK: invoke void @_ZN9ThrowCopyC1ERKS_
     // CHECK98: invoke void @_ZN12ImplicitCopyD1Ev
     // CHECK11: call void @_ZN12ImplicitCopyD1Ev
     Container c2(c1);
   }
   catch (...) {
     return 1;
   }
 
   return 0;
 }
 

clang/test/CodeGenCXX/inheriting-constructor.cpp

namespace noninline_virt {
   // MSABI: br
   // MSABI: call {{.*}} @"??0Z@@Q{{AE|EAA}}@XZ"(
   // MSABI: call {{.*}} @"??0Z@@Q{{AE|EAA}}@XZ"(
 
   struct C : B { using B::B; };
   C c(1, 2, &c);
   // Complete object ctor forwards to A ctor, then calls B's base inheriting
   // constructor, which takes no arguments other than the this pointer and VTT.
-  // ITANIUM_LABEL: define linkonce_odr void @_ZN14noninline_virt1CCI1NS_1AEEiO1QPvU17pass_object_size0(
+  // ITANIUM-LABEL: define linkonce_odr void @_ZN14noninline_virt1CCI1NS_1AEEiO1QPvU17pass_object_size0(
   // ITANIUM: call void @_ZN14noninline_virt1AC2EiO1QPvU17pass_object_size0({{.*}} %{{.*}}, i32 %{{.*}}, %{{.*}}* {{.*}}, i8* %{{.*}}, i{{32|64}} %{{.*}})
   // ITANIUM: call void @_ZN14noninline_virt1BCI2NS_1AEEiO1QPvU17pass_object_size0(%{{.*}}* {{[^,]*}} %{{.*}}, i8** getelementptr inbounds ([2 x i8*], [2 x i8*]* @_ZTTN14noninline_virt1CE, i64 0, i64 1))
   // ITANIUM: store {{.*}} @_ZTVN14noninline_virt1CE
 
   // C constructor forwards to B constructor and A constructor. We pass the args
   // to both. FIXME: Can we pass undef here instead, for the base object
   // constructor call?
   // MSABI-LABEL: define internal {{.*}} @"??0C@noninline_virt@@Q{{AE|EAA}}@H$$Q{{E?}}AUQ@@P{{E?}}AXW4__pass_object_size0@__clang@@@Z"(%{{.*}}, i32{{.*}}, %{{.*}}, i8*{{.*}}, i{{32|64}}{{.*}}, i32 %{{.*}})

clang/test/CodeGenObjC/non-runtime-protocol.m

 // NONFRAGILE-NOT: OBJC_CLASS_NAME{{.*}}NonRuntimeProtocol
 // NONFRAGILE-NOT: _OBJC_$_PROTOCOL_INSTANCE_METHODS_NonRuntimeProtocol
 // NONFRAGILE-NOT: _OBJC_$_PROTOCOL_CLASS_METHODS_NonRuntimeProtocol
 // NONFRAGILE-NOT: _OBJC_PROTOCOL_$_NonRuntimeProtocol
 // NONFRAGILE-NOT: _OBJC_LABEL_PROTOCOL_$_NonRuntimeProtocol
 // NONFRAGILE-NOT: _OBJC_CLASS_PROTOCOLS_$_NonRuntimeImplementer
 // FRAGILE-NOT: OBJC_CLASS_NAME_.{{.*}}"Runtime\00"
 // FRAGILE-NOT: OBJC_PROTOCOL_NonRuntime
-// FRAGILE_NOT: OBJC_PROTOCOLS_NonRuntimeImplementer
+// FRAGILE-NOT: OBJC_PROTOCOLS_NonRuntimeImplementer
 // GNU-NOT: private unnamed_addr constant {{.*}} c"NonRuntimeProtocol\00"
 // GNU-NOT: @.objc_protocol {{.*}}
 // GNU2-NOT: private unnamed_addr constant {{.*}} c"NonRuntimeProtocol\00"
 // GNU2-NOT: @.objc_protocol {{.*}}
 __attribute__((objc_non_runtime_protocol))
 @protocol NonRuntimeProtocol
 - (void)doThing;
 + (void)doClassThing;

clang/test/OpenMP/master_taskloop_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
 // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2

clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
 // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2

clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
 // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2

clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
 // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2

clang/test/OpenMP/task_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal noundef i32 [[DESTRUCTORS]](i32 noundef %0, [[KMP_TASK_MAIN_TY]]* noalias noundef %1)
 // CHECK: [[PRIVATES:%.+]] = getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* [[RES_KMP_TASK:%.+]], i{{[0-9]+}} 0, i{{[0-9]+}} 1
 // CHECK: [[PRIVATE_S_ARR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 0
 // CHECK: [[PRIVATE_VAR_REF:%.+]] = getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* [[PRIVATES]], i{{.+}} 0, i{{.+}} 1
 // CHECK: call void [[S_DOUBLE_TY_DESTR]]([[S_DOUBLE_TY]]* {{[^,]*}} [[PRIVATE_VAR_REF]])

clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp

 // CHECK-DAG: define internal void @[[CCOMB]](i8* noundef %0, i8* noundef %1)
 // CHECK-DAG: phi %struct.S* [
 // CHECK-DAG: phi %struct.S* [
 // CHECK-DAG: call {{.+}}(%struct.S* {{.+}}, %struct.S* {{.+}}, %struct.S* {{.+}})
 // CHECK-DAG: call {{.+}}(%struct.S* {{.+}}, %struct.S* {{.+}})
 // CHECK-DAG: call {{.+}}(%struct.S* {{.+}})
 // CHECK-DAG: br i1 %
 // CHECK-DAG: ret void
-// CHECK_DAG: }
+// CHECK-DAG: }
 
 // CHECK-DAG: define internal void @[[VLAINIT]](i8* noalias noundef %{{.+}}, i8* noalias noundef %{{.+}})
 // CHECK-DAG: call i32 @__kmpc_global_thread_num(%struct.ident_t* {{[^,]+}})
 // CHECK-DAG: call i8* @__kmpc_threadprivate_cached(%struct.ident_t*
 // CHECK-DAG: phi i16* [
 // CHECK-DAG: store i16 0, i16* %
 // CHECK-DAG: br i1 %
 // CHECK-DAG: ret void
 // CHECK-DAG: }
 
 // CHECK-DAG: define internal void @[[VLACOMB]](i8* noundef %0, i8* noundef %1)
 // CHECK-DAG: call i32 @__kmpc_global_thread_num(%struct.ident_t* {{[^,]+}})
 // CHECK-DAG: call i8* @__kmpc_threadprivate_cached(%struct.ident_t*
 // CHECK-DAG: phi i16* [
 // CHECK-DAG: phi i16* [
 // CHECK-DAG: sext i16 %{{.+}} to i32
 // CHECK-DAG: add nsw i32 %
 // CHECK-DAG: trunc i32 %{{.+}} to i16
 // CHECK-DAG: store i16 %
-// CHECK_DAG: br i1 %
+// CHECK-DAG: br i1 %
 // CHECK-DAG: ret void
 // CHECK-DAG: }
 #endif
 
 // DEBUG-LABEL: distinct !DICompileUnit
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[AINIT]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[ACOMB]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[BINIT]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[BCOMB]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[ARGCINIT]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[ARGCCOMB]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[CINIT]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[CFINI]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[CCOMB]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[VLAINIT]]",
 // DEBUG-DAG: distinct !DISubprogram(linkageName: "[[VLACOMB]]",

clang/test/OpenMP/taskloop_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
 // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2

clang/test/OpenMP/taskloop_simd_private_codegen.cpp

 // CHECK: [[PRIV_VEC:%.+]] = load [2 x i32]*, [2 x i32]** [[PRIV_VEC_ADDR]],
 // CHECK: [[PRIV_SIVAR:%.+]] = load i32*, i32** [[PRIV_SIVAR_ADDR]],
 
 // Privates actually are used.
 // CHECK-DAG: [[PRIV_VAR]]
 // CHECK-DAG: [[PRIV_T_VAR]]
 // CHECK-DAG: [[PRIV_S_ARR]]
 // CHECK-DAG: [[PRIV_VEC]]
-// CHECK_DAG: [[PRIV_SIVAR]]
+// CHECK-DAG: [[PRIV_SIVAR]]
 
 // CHECK: ret
 
 // CHECK: define internal void [[MAIN_DUP]]([[KMP_TASK_MAIN_TY]]* noundef %0, [[KMP_TASK_MAIN_TY]]* noundef %1, i32 noundef %2)
 // CHECK: getelementptr inbounds [[KMP_TASK_MAIN_TY]], [[KMP_TASK_MAIN_TY]]* %{{.+}}, i32 0, i32 1
 // CHECK: getelementptr inbounds [[PRIVATES_MAIN_TY]], [[PRIVATES_MAIN_TY]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [2 x [[S_DOUBLE_TY]]], [2 x [[S_DOUBLE_TY]]]* %{{.+}}, i32 0, i32 0
 // CHECK: getelementptr inbounds [[S_DOUBLE_TY]], [[S_DOUBLE_TY]]* %{{.+}}, i64 2

llvm/include/llvm/FileCheck/FileCheck.h

struct FileCheckRequest {
   bool Verbose = false;
   bool VerboseVerbose = false;
 };
 
 namespace Check {
 
 enum FileCheckKind {
   CheckNone = 0,
+  CheckMisspelled,
   CheckPlain,
   CheckNext,
   CheckSame,
   CheckNot,
   CheckDAG,
   CheckLabel,
   CheckEmpty,
   CheckComment,

llvm/lib/FileCheck/FileCheck.cpp

std::string Check::FileCheckType::getDescription(StringRef Prefix) const {
   // Append directive modifiers.
   auto WithModifiers = [this, Prefix](StringRef Str) -> std::string {
     return (Prefix + Str + getModifiersDescription()).str();
   };
 
   switch (Kind) {
   case Check::CheckNone:
     return "invalid";
+  case Check::CheckMisspelled:
+    return "misspelled";
   case Check::CheckPlain:
     if (Count > 1)
       return WithModifiers("-COUNT");
     return WithModifiers("");
   case Check::CheckNext:
     return WithModifiers("-NEXT");
   case Check::CheckSame:
     return WithModifiers("-SAME");
case Check::CheckBadNot:
     return "bad NOT";
   case Check::CheckBadCount:
     return "bad COUNT";
   }
   llvm_unreachable("unknown FileCheckType");
 }
 
 static std::pair<Check::FileCheckType, StringRef>
-FindCheckType(const FileCheckRequest &Req, StringRef Buffer, StringRef Prefix) {
+FindCheckType(const FileCheckRequest &Req, StringRef Buffer, StringRef Prefix,
+              bool &Misspelled) {
   if (Buffer.size() <= Prefix.size())
     return {Check::CheckNone, StringRef()};
 
   StringRef Rest = Buffer.drop_front(Prefix.size());
   // Check for comment.
   if (llvm::is_contained(Req.CommentPrefixes, Prefix)) {
     if (Rest.consume_front(":"))
       return {Check::CheckComment, Rest};
FindCheckType(const FileCheckRequest &Req, StringRef Buffer, StringRef Prefix,
   };
 
   // Verify that the prefix is followed by directive modifiers or a colon.
   if (Rest.consume_front(":"))
     return {Check::CheckPlain, Rest};
   if (Rest.front() == '{')
     return ConsumeModifiers(Check::CheckPlain);
 
-  if (!Rest.consume_front("-"))
+  if (Rest.consume_front("_"))
+    Misspelled = true;
+  else if (!Rest.consume_front("-"))
     return {Check::CheckNone, StringRef()};
 
   if (Rest.consume_front("COUNT-")) {
     int64_t Count;
     if (Rest.consumeInteger(10, Count))
       // Error happened in parsing integer.
       return {Check::CheckBadCount, Rest};
     if (Count <= 0 || Count > INT32_MAX)
if (Rest.consume_front("LABEL"))
     return ConsumeModifiers(Check::CheckLabel);
 
   if (Rest.consume_front("EMPTY"))
     return ConsumeModifiers(Check::CheckEmpty);
 
   return {Check::CheckNone, Rest};
 }
 
+static std::pair<Check::FileCheckType, StringRef>
+FindCheckType(const FileCheckRequest &Req, StringRef Buffer, StringRef Prefix) {
+  bool Misspelled = false;
+  auto Res = FindCheckType(Req, Buffer, Prefix, Misspelled);
+  if (Res.first != Check::CheckNone && Misspelled)
+    return {Check::CheckMisspelled, Res.second};
+  return Res;
+}
+
 // From the given position, find the next character after the word.
 static size_t SkipWord(StringRef Str, size_t Loc) {
   while (Loc < Str.size() && IsPartOfWord(Str[Loc]))
     ++Loc;
   return Loc;
 }
 
 /// Searches the buffer for the first prefix in the prefix regular expression.
while (true) {
     // Location to use for error messages.
     const char *UsedPrefixStart = UsedPrefix.data();
 
     // Skip the buffer to the end of parsed suffix (or just prefix, if no good
     // suffix was processed).
     Buffer = AfterSuffix.empty() ? Buffer.drop_front(UsedPrefix.size())
                                  : AfterSuffix;
 
+    // Complain about misspelled directives.
+    if (CheckTy == Check::CheckMisspelled) {
+      StringRef UsedDirective(UsedPrefix.data(),
+                              AfterSuffix.data() - UsedPrefix.data());
+      SM.PrintMessage(SMLoc::getFromPointer(UsedDirective.data()),
+                      SourceMgr::DK_Error,
+                      "misspelled directive '" + UsedDirective + "'");
+      return true;
+    }
+
     // Complain about useful-looking but unsupported suffixes.
     if (CheckTy == Check::CheckBadNot) {
       SM.PrintMessage(SMLoc::getFromPointer(Buffer.data()), SourceMgr::DK_Error,
                       "unsupported -NOT combo on prefix '" + UsedPrefix + "'");
       return true;
     }
 
     // Complain about invalid count specification.

llvm/test/Analysis/MemorySSA/phi-translation.ll

; LIMIT-NEXT: load i8, i8* %p1
   load i8, i8* %p1
   br label %while.cond
 }
 
 ; CHECK-LABEL: define i32 @use_not_optimized_due_to_backedge
 define i32 @use_not_optimized_due_to_backedge(i32* nocapture %m_i_strides, i32* nocapture readonly %eval_left_dims) {
 entry:
 ; CHECK: 1 = MemoryDef(liveOnEntry)
-; CHECK_NEXT: store i32 1, i32* %m_i_strides, align 4
+; CHECK-NEXT: store i32 1, i32* %m_i_strides, align 4
   store i32 1, i32* %m_i_strides, align 4
   br label %for.body
 
 for.cond.cleanup:                                 ; preds = %for.inc
   ret i32 %m_i_size.1
 
 for.body:                                         ; preds = %entry, %for.inc
 ; CHECK: 4 = MemoryPhi({entry,1},{for.inc,3})

llvm/test/Analysis/RegionInfo/infinite_loop_4.ll

 "3":
   br label %"4"
 "4":
   ret void
 }
 ; CHECK-NOT: =>
 ; CHECK: [0] 0 => <Function Return>
 ; CHECK-NEXT: [1] 2 => 10
-; CHECK_NEXT: [2] 5 => 6
+; CHECK-NEXT: [2] 5 => 6
 ; STAT: 3 region - The # of regions
 ; STAT: 1 region - The # of simple regions
 
 ; BBIT: 0, 7, 1, 2, 5, 11, 6, 10, 8, 9, 13, 14, 12, 3, 4,
 ; BBIT: 2, 5, 11, 6, 12,
 ; BBIT: 5, 11, 12,
 ; RNIT: 0, 7, 1, 2 => 10, 10, 8, 9, 13, 14, 3, 4,
 ; RNIT: 2, 5 => 6, 6,
 ; RNIT: 5, 11, 12,

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

 ; CHECK-FP16-NEXT:    fcvtzs v0.8h, v0.8h
 ; CHECK-FP16-NEXT:    xtn v0.8b, v0.8h
 ; CHECK-FP16-NEXT:    ret
   %1 = fptosi<8 x half> %a to <8 x i8>
   ret <8 x i8> %1
 }
 
 define <8 x i16> @fptosi_i16(<8 x half> %a) #0 {
-; CHECK-CVT_DAG:   fcvtl   [[LO:v[0-9]+\.4s]], v0.4h
-; CHECK-CVT_DAG:   fcvtl2  [[HI:v[0-9]+\.4s]], v0.8h
-; CHECK-CVT_DAG:   fcvtzs  [[LOF32:v[0-9]+\.4s]], [[LO]]
-; CHECK-CVT_DAG:   xtn     [[I16:v[0-9]+]].4h, [[LOF32]]
-; CHECK-CVT_DAG:   fcvtzs  [[HIF32:v[0-9]+\.4s]], [[HI]]
-; CHECK-CVT_DAG:   xtn2    [[I16]].8h, [[HIF32]]
-; CHECK-COMMON_NEXT:      ret
+; TODO-CVT-DAG:   fcvtl   [[LO:v[0-9]+\.4s]], v0.4h
+; TODO-CVT-DAG:   fcvtl2  [[HI:v[0-9]+\.4s]], v0.8h
+; TODO-CVT-DAG:   fcvtzs  [[LOF32:v[0-9]+\.4s]], [[LO]]
+; TODO-CVT-DAG:   xtn     [[I16:v[0-9]+]].4h, [[LOF32]]
+; TODO-CVT-DAG:   fcvtzs  [[HIF32:v[0-9]+\.4s]], [[HI]]
+; TODO-CVT-DAG:   xtn2    [[I16]].8h, [[HIF32]]
+; TODO-NEXT:      ret
 ; CHECK-CVT-LABEL: fptosi_i16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    fcvtl2 v1.4s, v0.8h
 ; CHECK-CVT-NEXT:    fcvtl v0.4s, v0.4h
 ; CHECK-CVT-NEXT:    fcvtzs v1.4s, v1.4s
 ; CHECK-CVT-NEXT:    fcvtzs v0.4s, v0.4s
 ; CHECK-CVT-NEXT:    uzp1 v0.8h, v0.8h, v1.8h
 ; CHECK-CVT-NEXT:    ret
 ;

llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll

 ;     res[i] = vmull_p64((poly64_t)vget_low_p64(vreinterpretq_p64_u64(ci)),
 ;                        (poly64_t)vget_low_p64(vreinterpretq_p64_u64(h)));
 ;     res[i+1] = vmull_high_p64(vreinterpretq_p64_u64(ci),
 ;                               vreinterpretq_p64_u64(h));
 ;   }
 ; }
 
 
-;CHECK_LABEL: func:
+;CHECK-LABEL: _Z4funcP2SSjPKhPo
 ;CHECK: pmull2
 
 %struct.SS = type { <2 x i64>, <2 x i64> }
 
 ; Function Attrs: nofree noinline nounwind
 define dso_local void @_Z4funcP2SSjPKhPo(%struct.SS* nocapture readonly %g, i32 %count, i8* nocapture readonly %buf, i128* nocapture %res) local_unnamed_addr #0 {
 entry:
   %h2 = getelementptr inbounds %struct.SS, %struct.SS* %g, i64 0, i32 1

llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
-; GCN_LABEL: @bfe_uniform
+; GCN-LABEL: @bfe_uniform
 ; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x40010
 define amdgpu_kernel void @bfe_uniform(i32 %val, i32 addrspace(1)* %out) {
   %hibits = lshr i32 %val, 16
   %masked = and i32 %hibits, 15
   store i32 %masked, i32 addrspace(1)* %out
   ret void
 }
 
-; GCN_LABEL: @bfe_divergent
+; GCN-LABEL: @bfe_divergent
 ; GCN: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, 16, 4
 define amdgpu_kernel void @bfe_divergent(i32 %val, i32 addrspace(1)* %out) {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %divergent = add i32 %val, %tid
   %hibits = lshr i32 %divergent, 16
   %masked = and i32 %hibits, 15
   store i32 %masked, i32 addrspace(1)* %out
   ret void
 }
 
 
 declare i32 @llvm.amdgcn.workitem.id.x()
 

llvm/test/CodeGen/AMDGPU/hoist-cond.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs -disable-block-placement < %s | FileCheck %s
 
 ; Check that invariant compare is hoisted out of the loop.
 ; At the same time condition shall not be serialized into a VGPR and deserialized later
 ; using another v_cmp + v_cndmask, but used directly in s_and_saveexec_b64.
 
 ; CHECK: v_cmp_{{..}}_u32_e{{32|64}} [[COND:s\[[0-9]+:[0-9]+\]|vcc]]
 ; CHECK: BB0_1:
 ; CHECK-NOT: v_cmp
-; CHECK_NOT: v_cndmask
+; CHECK-NOT: v_cndmask
 ; CHECK: s_and_saveexec_b64 s[{{[0-9]+:[0-9]+}}], [[COND]]
 ; CHECK: ; %bb.2:
 
 define amdgpu_kernel void @hoist_cond(float addrspace(1)* nocapture %arg, float addrspace(1)* noalias nocapture readonly %arg1, i32 %arg3, i32 %arg4) {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
   %tmp5 = icmp ult i32 %tmp, %arg3
   br label %bb1

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll

define amdgpu_ps float @test2() #0 {
   %r = extractelement <4 x float> %t, i32 0
   ret float %r
 }
 
 ; CHECK-LABEL: {{^}}test3:
 ; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
 ; CHECK-DAG: s_wqm_b64 exec, exec
 ; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1
-; CHECK_DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]]
+; CHECK-DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]]
 ; CHECK: ; %dead
 define amdgpu_ps float @test3(i32 %in) #0 {
 entry:
   %live = call i1 @llvm.amdgcn.ps.live()
   br i1 %live, label %end, label %dead
 
 dead:
   %tc.dead = mul i32 %in, 2

llvm/test/CodeGen/AMDGPU/mode-register.mir

body: |
 
   bb.6:
     S_ENDPGM 0
 ...
 ---
 # check that mode is propagated back to start of loop and through a block that
 # neither sets or uses the mode.
 # CHECK-LABEL: name: loop_indirect
-# CHECK_NOT: S_SETREG_IMM32_B32
+# CHECK-NOT: S_SETREG_IMM32_B32
 # CHECK-LABEL: bb.3:
 # CHECK: S_SETREG_IMM32_B32 3, 2177
 # CHECK: V_INTERP_P1LL_F16
 # CHECK-NOT: S_SETREG_IMM32_B32
 
 name: loop_indirect
 
 body: |

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

 # RUN: llc  -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
 ---
-# GCN_LABEL: phi_moveimm_input
+# GCN-LABEL: phi_moveimm_input
 # GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
-# GCN:     %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
+# TODO:     %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 
 name:            phi_moveimm_input
 tracksRegLiveness: true
 body:             |
   bb.0:
     successors: %bb.1
     liveins: $sgpr0, $sgpr1
 
body:             |
 
   bb.3:
     successors: %bb.2
     %1:sreg_32 = COPY %0
     S_BRANCH %bb.2
 ...
 
 ---
-# GCN_LABEL: phi_moveimm_subreg_input
-# GCN-NOT: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
-# GCN: %{{[0-9]+}}:vreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
+# GCN-LABEL: phi_moveimm_subreg_input
+# TODO-NOT: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
+# TODO: %{{[0-9]+}}:vreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 name:            phi_moveimm_subreg_input
 tracksRegLiveness: true
 body:             |
   bb.0:
     successors: %bb.1
     liveins: $sgpr0, $sgpr1
 
     %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
body:             |
   bb.3:
     successors: %bb.2
     undef %1.sub0:sreg_64 = COPY %0
     S_BRANCH %bb.2
 ...
 
 
 ---
-# GCN_LABEL: phi_moveimm_bad_opcode_input
-# GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
+# GCN-LABEL: phi_moveimm_bad_opcode_input
+# TODO-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 # GCN: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
 name:            phi_moveimm_bad_opcode_input
 tracksRegLiveness: true
 body:             |
   bb.0:
     successors: %bb.1
     liveins: $sgpr0, $sgpr1, $vgpr0
     %6:vgpr_32 = COPY $vgpr0

llvm/test/CodeGen/AMDGPU/smrd.ll

main_body:
   call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true) #0
   ret void
 }
 
 ; GCN-LABEL: {{^}}smrd_imm_merge_m0:
 ;
 ; GCN: s_buffer_load_dwordx2
 ; SICIVI: s_mov_b32 m0
-; SICIVI_DAG: v_interp_p1_f32
-; SICIVI_DAG: v_interp_p1_f32
-; SICIVI_DAG: v_interp_p1_f32
-; SICIVI_DAG: v_interp_p2_f32
-; SICIVI_DAG: v_interp_p2_f32
-; SICIVI_DAG: v_interp_p2_f32
+; SICIVI-DAG: v_interp_p1_f32
+; SICIVI-DAG: v_interp_p1_f32
+; SICIVI-DAG: v_interp_p1_f32
+; SICIVI-DAG: v_interp_p2_f32
+; SICIVI-DAG: v_interp_p2_f32
+; SICIVI-DAG: v_interp_p2_f32
 ;
 ; extractelement does not result in movrels anymore for vectors gitting 8 dwords
 ; SICIVI-NOT: s_mov_b32 m0
 ; SICIVI-NOT: v_movrels_b32_e32
 ; v_cndmask_b32_e32
 ; v_cndmask_b32_e32
 ;
 ; Merging is still thwarted on GFX9 due to s_set_gpr_idx

llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll

 ; RUN: llc -verify-machineinstrs -mtriple=armebv8-linux-gnueabi -O0 %s -o - | FileCheck %s
 
 @x = global i64 10, align 8
 @y = global i64 20, align 8
 @z = global i64 20, align 8
 
-; CHECK_LABEL:  main:
+; CHECK-LABEL:  main:
 ; CHECK:  ldr [[R2:r[0-9]+]], [[[R1:r[0-9]+]]]
 ; CHECK-NEXT: ldr [[R1]], [[[R1]], #4]
 ; CHECK:  mov [[R4:r[0-9]+]], [[R1]]
 ; CHECK:  ldr [[R5:r[0-9]+]], [[[R1]]]
 ; CHECK-NEXT: ldr [[R6:r[0-9]+]], [[[R1]], #4]
 ; CHECK:  mov [[R7:r[0-9]+]], [[R6]]
 
 define arm_aapcs_vfpcc i32 @main() #0 {

llvm/test/CodeGen/AVR/atomics/fence.ll

 ; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
 
 ; Checks that atomic fences are simply removed from IR.
 ; AVR is always singlethreaded so fences do nothing.
 
-; CHECK_LABEL: atomic_fence8
+; CHECK-LABEL: atomic_fence8
 ; CHECK:      ; %bb.0:
 ; CHECK-NEXT:   ret
 define void @atomic_fence8() {
   fence acquire
   ret void
 }
 

llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll

 ; CHECK:             .ascii  ".text"                 # string offset=29
 ; CHECK:             .ascii  "0:0"                   # string offset=72
 ; CHECK:             .ascii  "0:0:0"                 # string offset=76
 ; CHECK:             .ascii  "0:0:0:0"               # string offset=82
 
 ; CHECK:             .long   16                      # FieldReloc
 ; CHECK-NEXT:        .long   29                      # Field reloc section string offset=29
 ; CHECK-NEXT:        .long   3
-; CHECK_NEXT:        .long   .Ltmp{{[0-9]+}}
-; CHECK_NEXT:        .long   2
-; CHECK_NEXT:        .long   72
-; CHECK_NEXT:        .long   0
-; CHECK_NEXT:        .long   .Ltmp{{[0-9]+}}
-; CHECK_NEXT:        .long   2
-; CHECK_NEXT:        .long   76
-; CHECK_NEXT:        .long   0
-; CHECK_NEXT:        .long   .Ltmp{{[0-9]+}}
-; CHECK_NEXT:        .long   2
-; CHECK_NEXT:        .long   82
-; CHECK_NEXT:        .long   0
+; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   72
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   76
+; CHECK-NEXT:        .long   0
+; CHECK-NEXT:        .long   .Ltmp{{[0-9]+}}
+; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   82
+; CHECK-NEXT:        .long   0
 
 ; Function Attrs: nounwind readnone
 declare %struct.s1* @llvm.preserve.struct.access.index.p0s_struct.s1s.p0s_struct.r1s(%struct.r1*, i32, i32) #1
 
 ; Function Attrs: nounwind readnone
 declare %struct.t1* @llvm.preserve.struct.access.index.p0s_struct.t1s.p0s_struct.s1s(%struct.s1*, i32, i32) #1
 
 ; Function Attrs: nounwind readnone

llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir

 # RUN: not llc -march=amdgcn -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
 
 ---
 name: extra_imm_operand
 body: |
   bb.0:
     ; CHECK: [[@LINE+3]]:18: too many operands for instruction
     ; CHECK-NEXT: S_ENDPGM 0, 0
-    ; CHECK_NEXT:               ^
+    ; CHECK-NEXT:               ^
     S_ENDPGM 0, 0
 
 ...

llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir

 # RUN: not llc -march=amdgcn -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
 
 ---
 name: extra_reg_operand
 body: |
   bb.0:
     ; CHECK: [[@LINE+3]]:29: too many operands for instruction
-    ; S_ENDPGM 0, undef $vgpr0
-    ; CHECK_NEXT:               ^
+    ; CHECK: S_ENDPGM 0, undef $vgpr0
+    ; CHECK-NEXT:               ^
     S_ENDPGM 0, undef $vgpr0
 
 ...

llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll

 ; RUN: llc < %s -mtriple=thumbv8m.base-arm-none-eabi | FileCheck %s
 
 define void @fn() {
 entry:
 ; CHECK-LABEL: fn:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r5, r6, lr}
 ; CHECK-NEXT:    push {r4, r5, r6, lr}
 ; CHECK-NEXT:    ldr r6, .LCPI0_0
 ; CHECK-NEXT:    .pad #1600
 ; CHECK-NEXT:    add sp, r6
 ; CHECK: .LCPI0_0:
-; CHECK_NEXT:    long   4294963196
+; TODO-NEXT:     long   4294963196
+
   %a = alloca [400 x i32], align 4
   %arraydecay = getelementptr inbounds [400 x i32], [400 x i32]* %a, i32 0, i32 0
   call void @bar(i32* %arraydecay)
   ret void
 }
 
 define void @execute_only_fn() #0 {
 entry:

llvm/test/CodeGen/WebAssembly/libcalls.ll

define fp128 @fp128libcalls(fp128 %x, fp128 %y, i32 %z) {
   ; CHECK: call nearbyintl
   %i = call fp128 @llvm.nearbyint.f128(fp128 %h)
   ret fp128 %i
 }
 
 ; CHECK-LABEL: i128libcalls:
 define i128 @i128libcalls(i128 %x, i128 %y) {
   ; Basic ops should be expanded
-  ; CHECK_NOT: call
+  ; CHECK: .local
+  ; CHECK-NOT: call
   %a = add i128 %x, %y
   ; CHECK: call __multi3
   %b = mul i128 %a, %y
   ; CHECK: call __umodti3
   %c = urem i128 %b, %y
   ret i128 %c
 }
 
 ; CHECK-LABEL: f64libcalls:

llvm/test/CodeGen/X86/GlobalISel/select-ext.mir

 # X64-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
 # X64-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
 # X32:          %0:gr32_abcd = COPY $edi
 # X64:          %0:gr32 = COPY $edi
-# ALL_NEXT:     %1:gr8 = COPY %0.sub_8bit
-# ALL_NEXT:     %2:gr8 = AND8ri %1, 1, implicit-def $eflags
-# ALL_NEXT:     $al = COPY %2
-# ALL_NEXT:     RET 0, implicit $al
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT:     %2:gr8 = AND8ri %1, 1, implicit-def $eflags
+# ALL-NEXT:     $al = COPY %2
+# ALL-NEXT:     RET 0, implicit $al
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     %0(s32) = COPY $edi
     %1(s1) = G_TRUNC %0(s32)
     %2(s8) = G_ZEXT %1(s1)
     $al = COPY %2(s8)
     RET 0, implicit $al

 # X64-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
 # X64-NEXT:   - { id: 3, class: gr16, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
 # X32:          %0:gr32_abcd = COPY $edi
 # X64:          %0:gr32 = COPY $edi
-# ALL_NEXT:     %1:gr8 = COPY %0.sub_8bit
-# ALL_NEXT:     %3:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
-# ALL_NEXT:     %2:gr16 = AND16ri8 %3, 1, implicit-def $eflags
-# ALL_NEXT:     $ax = COPY %2
-# ALL_NEXT:     RET 0, implicit $ax
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# TODO-NEXT:     %3:gr16 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
+# TODO-NEXT:     %2:gr16 = AND16ri8 %3, 1, implicit-def $eflags
+# TODO-NEXT:     $ax = COPY %2
+# TODO-NEXT:     RET 0, implicit $ax
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     %0(s32) = COPY $edi
     %1(s1) = G_TRUNC %0(s32)
     %2(s16) = G_ZEXT %1(s1)
     $ax = COPY %2(s16)

 # X64-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
 # X64-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # X32:          %0:gr32_abcd = COPY $edi
 # X64:          %0:gr32 = COPY $edi
-# ALL_NEXT:     %1:gr8 = COPY %0.sub_8bit
-# ALL_NEXT:     %3:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
-# ALL_NEXT:     %2:gr32 = AND32ri8 %3, 1, implicit-def $eflags
-# ALL_NEXT:     $eax = COPY %2
-# ALL_NEXT:     RET 0, implicit $eax
+# ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
+# TODO-NEXT:     %3:gr32 = SUBREG_TO_REG 0, %1, %subreg.sub_8bit
+# TODO-NEXT:     %2:gr32 = AND32ri8 %3, 1, implicit-def $eflags
+# TODO-NEXT:     $eax = COPY %2
+# TODO-NEXT:     RET 0, implicit $eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi
 
     %0(s32) = COPY $edi
     %1(s1) = G_TRUNC %0(s32)
     %2(s32) = G_ZEXT %1(s1)
     $eax = COPY %2(s32)

llvm/test/CodeGen/X86/coalesce-dead-lanes.mir

 # RUN: llc -run-pass simple-register-coalescing -O0 -mtriple x86_64-pc-linux-gnu -o - %s | FileCheck %s
 
 ---
 name:            foo
 tracksRegLiveness: true
 body:             |
   bb.0:
     undef %18.sub_8bit_hi:gr16_abcd = COPY undef $al
     %1:gr16_abcd = COPY killed %18
     dead %8:gr8 = COPY undef %1.sub_8bit_hi
     $al = COPY undef %8
 ...
 
 # This used to hit an assertion:
 #   lib/CodeGen/RegisterCoalescer.cpp:1110: RegisterCoalescer::reMaterializeTrivialDef(...): Assertion `ValNo && "CopyMI input register not live"' failed.
 #
-# CHECK_LABEL: name:            foo
+# CHECK-LABEL: name:            foo
 # CHECK:       bb.0:
 # CHECK-NEXT:    $al = COPY undef %2:gr8

llvm/test/CodeGen/X86/copy-propagation.ll

 ; required, which would have hidden the bug.
 ; CHECK: vmovapd  %xmm0, [[TMP:%xmm[0-9]+]]
 ; CHECK-NOT: vxorps  %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT: vcvtsi2sd      %rsi, %xmm0, %xmm6
 ; CHECK: movl $339772768, %e[[INDIRECT_CALL2:[a-z]+]]
 ; CHECK-NOT: vmovapd %xmm7, %xmm0
 ; CHECK-NEXT: vmovapd %xmm6, %xmm1
 ; Set TMP in the first argument of the second call.
-; CHECK_NEXT: callq *%r[[INDIRECT_CALL2]]
+; CHECK-NEXT: callq *%r[[INDIRECT_CALL2]]
 ; CHECK: retq
 define double @foo(i64 %arg) {
 top:
   %tmp = call double inttoptr (i64 339752784 to double (double, double)*)(double 1.000000e+00, double 0.000000e+00)
   tail call void asm sideeffect "", "x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(double %tmp)
   %tmp1 = sitofp i64 %arg to double
   call void inttoptr (i64 339772768 to void (double, double)*)(double %tmp, double %tmp1)
   %tmp3 = fadd double %tmp1, %tmp
   ret double %tmp3
 }

llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll

 ; X64FAST:   callq __llvm_lvi_thunk_r11
 ; X64FAST:   movq nonlazybind_callee@GOTPCREL(%rip), %r11
 ; X64FAST:   jmp __llvm_lvi_thunk_r11 # TAILCALL
 
 
 ; Check that a switch gets lowered using a jump table
 define void @switch_jumptable(i32* %ptr, i64* %sink) #0 {
 ; X64-LABEL: switch_jumptable:
-; X64_NOT:      jmpq *
+; X64-NOT:      jmpq *
 entry:
   br label %header
 
 header:
   %i = load volatile i32, i32* %ptr
   switch i32 %i, label %bb0 [
     i32 1, label %bb1
     i32 2, label %bb2

llvm/test/CodeGen/X86/statepoint-vreg-details.ll

entry:
   %rel0 = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(token %token, i32 0, i32 0)
   %rel1 = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(token %token, i32 1, i32 1)
   %res = select i1 %cmp, i8 addrspace(1)* %rel0, i8 addrspace(1)* %rel1
   ret i8 addrspace(1)* %res
 }
 
 ; Check that ISEL of gc.relocate used in other BB does not generate extra COPY instruction.
 define i1 @test_cross_bb_reloc(i32 addrspace(1)* %a, i1 %external_cond) gc "statepoint-example" {
-; CHECK-VREG_LABEL: test_cross_bb_reloc:
+; CHECK-VREG-LABEL: test_cross_bb_reloc
 ; CHECK-VREG:    bb.0.entry:
 ; CHECK-VREG:      [[VREG:%[^ ]+]]:gr64 = STATEPOINT 0, 0, 0, @return_i1, 2, 0, 2, 0, 2, 0, 2, 1, %2(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def $al
 ; CHECK-VREG-NOT:  COPY [[VREG]]
 ; CHECK-VREG:    bb.1.left:
 ; CHECK-VREG:      $rdi = COPY [[VREG]]
 ; CHECK-VREG:      CALL64pcrel32 @consume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
 ; CHECK-VREG:      $al = COPY %1
 ; CHECK-VREG:      RET 0, $al

llvm/test/DebugInfo/NVPTX/debug-info.ll

 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/include{{/|\\\\}}mathcalls.h"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/lib/gcc/4.8/../../../../include/c++/4.8{{/|\\\\}}cmath"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/include{{/|\\\\}}stdlib.h"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/lib/gcc/4.8/../../../../include/c++/4.8{{/|\\\\}}cstdlib"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/include{{/|\\\\}}stdlib-float.h"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/include{{/|\\\\}}stdlib-bsearch.h"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}clang/include{{/|\\\\}}stddef.h"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/local/cuda/include{{/|\\\\}}math_functions.hpp"
-; CHECK_DAG: .file {{[0-9]+}} "{{.*}}clang/include{{/|\\\\}}__clang_cuda_cmath.h"
+; CHECK-DAG: .file {{[0-9]+}} "{{.*}}clang/include{{/|\\\\}}__clang_cuda_cmath.h"
 ; CHECK-DAG: .file {{[0-9]+}} "{{.*}}/usr/local/cuda/include{{/|\\\\}}device_functions.hpp"
 ; CHECK-DAG: .file [[DEBUG_INFO_CU]] "{{.*}}debug-info.cu"
 ; CHECK-DAG: .file [[BUILTUIN_VARS_H]] "{{.*}}clang/include{{/|\\\\}}__clang_cuda_builtin_vars.h"
 
 ; CHECK:  .section  .debug_abbrev
 ; CHECK-NEXT: {
 ; CHECK-NEXT:.b8 1                                   // Abbreviation Code
 ; CHECK-NEXT:.b8 17                                  // DW_TAG_compile_unit

llvm/test/DebugInfo/X86/debug-info-template-parameter.ll

 ; CHECK-NOT: DW_AT_default_value
 ; CHECK: DW_AT_type {{.*}} "int"
 ; CHECK-NEXT: DW_AT_name {{.*}} "i"
 ; CHECK-NOT: DW_AT_default_value
 
 ; CHECK: DW_AT_name {{.*}} "foo<char, 3>"
 ; CHECK: DW_AT_type {{.*}} "char"
 ; CHECK-NEXT: DW_AT_name {{.*}} "T"
-; CHECK_NEXT: DW_AT_default_value {{.*}} true
+; TODO-NEXT: DW_AT_default_value {{.*}} true
 ; CHECK: DW_AT_type {{.*}} "int"
 ; CHECK-NEXT: DW_AT_name {{.*}} "i"
-; CHECK_NEXT: DW_AT_default_value {{.*}} true
+; TODO-NEXT: DW_AT_default_value {{.*}} true
 
 ; ModuleID = '/dir/test.cpp'
 source_filename = "test.cpp"
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 %class.foo = type { i8 }
 %class.foo.0 = type { i8 }

llvm/test/FileCheck/missspelled-directive.txt

+RUN: not FileCheck --check-prefix=P1 %s 2>&1 | FileCheck --check-prefix=CHECK1 %s
+RUN: not FileCheck --check-prefix=P2 %s 2>&1 | FileCheck --check-prefix=CHECK2 %s
+RUN: not FileCheck --check-prefix=P3 %s 2>&1 | FileCheck --check-prefix=CHECK3 %s
+RUN: not FileCheck --check-prefix=P4 %s 2>&1 | FileCheck --check-prefix=CHECK4 %s
+RUN: not FileCheck --check-prefix=P5 %s 2>&1 | FileCheck --check-prefix=CHECK5 %s
+RUN: not FileCheck --check-prefix=P6 %s 2>&1 | FileCheck --check-prefix=CHECK6 %s
+RUN: not FileCheck --check-prefix=P7 %s 2>&1 | FileCheck --check-prefix=CHECK7 %s
+
+P1_LABEL: foo
+CHECK1: error: misspelled directive 'P1_LABEL:'
+
+P2_NEXT: foo
+CHECK2: error: misspelled directive 'P2_NEXT:'
+
+P3_NOT: foo
+CHECK3: error: misspelled directive 'P3_NOT:'
+
+P4_COUNT-2: foo
+CHECK4: error: misspelled directive 'P4_COUNT-2:'
+
+P5_SAME: foo
+CHECK5: error: misspelled directive 'P5_SAME:'
+
+P6_EMPTY: foo
+CHECK6: error: misspelled directive 'P6_EMPTY:'
+
+P7_DAG: foo
+CHECK7: error: misspelled directive 'P7_DAG:'

llvm/test/MC/AMDGPU/data.s

.text
   .long         0xabadc0d1, 0xabadc0d2, 0xabadc0d3, 0xabadc0d4
   .byte         0x0a, 0x0b
   .byte         0x0c
 
 // CHECK: .text
 // CHECK: v_mov_b32
 // CHECK: v_mov_b32
 // CHECK: .long 0xabadc0de
-// CHECK_SAME: : ABADC0DE
+// CHECK-SAME: : ABADC0DE
 // CHECK: s_endpgm
 // CHECK: .long 0xabadc0d1
 // CHECK: .long 0xabadc0d2
 // CHECK: .long 0xabadc0d3
 // CHECK: .long 0xabadc0d4
 // CHECK: .byte 0x0a, 0x0b, 0x0c
 // CHECK-SAME: : 0A 0B 0C
 // CHECK-NOT: .long

llvm/test/MC/AsmParser/directive_file-g.s

foo:
         .file 1 "a.c"
         .loc 1 1 1
         nop
 
 # CHECK: .debug_info
 ## gcc does generate a DW_TAG_compile_unit in this case, with or without
 ## -g on the command line, but we do not.
 # CHECK-EMPTY:
-# CHECK_NEXT: .debug_line
+# CHECK-NEXT: .debug_line
 # CHECK: file_names[ 1]:
 # CHECK-NEXT: name: "a.c"
 # CHECK-NEXT: dir_index: 0
 # CHECK: 0x{{0+}}0 1 1 1 0 0 is_stmt
 # CHECK: 0x{{0+}}1 1 1 1 0 0 is_stmt end_sequence

llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s

.LSingleInsnBetween$local:
   pld 3, vec@got@pcrel(0), 1
 .Lpcrel2:
         addi 3, 3, 42
   .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   SingleInsnBetween
+# CHECK-LABEL:   SingleInsnBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0xc
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    lwa 3, 4(3)
 # CHECK-NEXT:    blr
 
 
.Lpcrel3:
         addi 3, 3, 42
         addi 3, 3, 42
         addi 3, 3, 42
   .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   MultiInsnBetween
+# CHECK-LABEL:   MultiInsnBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0x1c
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
.Lpcrel4:
         addi 3, 3, 42
         paddi 3, 3, 42, 0
         addi 3, 3, 42
   .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   PrefixInsnBetween
+# CHECK-LABEL:   PrefixInsnBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0x28
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    nop
 # CHECK-NEXT:    paddi 3, 3, 42, 0
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    paddi 3, 3, 42, 0
.Lpcrel5:
         .space 40, 0
         paddi 3, 3, 42, 0
         addi 3, 3, 42
   .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   SpaceBetween
+# CHECK-LABEL:   SpaceBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0x50
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    nop
 # CHECK-NEXT:    paddi 3, 3, 42, 0
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK:         paddi 3, 3, 42, 0
.LVarLabelSingleInsnBetween$local:
   pld 3, vec@got@pcrel(0), 1
 .Lpcrel102=.-8
         addi 3, 3, 42
   .reloc .Lpcrel102,R_PPC64_PCREL_OPT,.-.Lpcrel102
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   VarLabelSingleInsnBetween
+# CHECK-LABEL:   VarLabelSingleInsnBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0xc
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    lwa 3, 4(3)
 # CHECK-NEXT:    blr
 
   .globl  VarLabelMultiInsnBetween                    # -- Begin function
   .p2align  4
   .type VarLabelMultiInsnBetween,@function
 VarLabelMultiInsnBetween:
 .LVarLabelMultiInsnBetween$local:
   pld 3, vec@got@pcrel(0), 1
 .Lpcrel103=.-8
         addi 3, 3, 42
         addi 3, 3, 42
         addi 3, 3, 42
         addi 3, 3, 42
         addi 3, 3, 42
   .reloc .Lpcrel103,R_PPC64_PCREL_OPT,.-.Lpcrel103
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   VarLabelMultiInsnBetween
+# CHECK-LABEL:   VarLabelMultiInsnBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0x1c
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    addi 3, 3, 42
.Lpcrel104=.-8
         addi 3, 3, 42
         paddi 3, 3, 42, 0
         addi 3, 3, 42
   .reloc .Lpcrel104,R_PPC64_PCREL_OPT,.-.Lpcrel104
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   VarLabelPrefixInsnBetween
+# CHECK-LABEL:   VarLabelPrefixInsnBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0x24
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    paddi 3, 3, 42, 0
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    paddi 3, 3, 42, 0
 # CHECK-NEXT:    addi 3, 3, 42
.Lpcrel105=.-8
         .space 40, 0
         paddi 3, 3, 42, 0
         addi 3, 3, 42
   .reloc .Lpcrel105,R_PPC64_PCREL_OPT,.-.Lpcrel105
   lwa 3, 4(3)
   blr
   .long 0
   .quad 0
-# CHECK_LABEL:   VarLabelSpaceBetween
+# CHECK-LABEL:   VarLabelSpaceBetween
 # CHECK:         pld 3, 0(0), 1
 # CHECK-NEXT:    R_PPC64_GOT_PCREL34  vec
 # CHECK-NEXT:    R_PPC64_PCREL_OPT  *ABS*+0x4c
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK-NEXT:    paddi 3, 3, 42, 0
 # CHECK-NEXT:    addi 3, 3, 42
 # CHECK:         paddi 3, 3, 42, 0
 # CHECK-NEXT:    addi 3, 3, 42

llvm/test/MC/WebAssembly/unnamed-data.ll

 ; CHECK-NEXT:       - Index:       2
 ; CHECK-NEXT:         Name:        .data.a
 ; CHECK-NEXT:         Alignment:   3
 ; CHECK-NEXT:         Flags:       [ ]
 ; CHECK-NEXT:       - Index:       3
 ; CHECK-NEXT:         Name:        .data.b
 ; CHECK-NEXT:         Alignment:   3
 ; CHECK-NEXT:         Flags:       [ ]
-; CHECK_NEXT:   ...
+; CHECK-NEXT:   ...

llvm/test/Transforms/Inline/inline-strictfp.ll

 ; RUN: opt -inline %s -S | FileCheck %s
 
 
 ; Ordinary function is inlined into strictfp function.
 
 define float @inlined_01(float %a) {
 entry:
   %add = fadd float %a, %a
   ret float %add
 }
 
 define float @host_02(float %a) #0 {
 entry:
   %0 = call float @inlined_01(float %a) #0
   %add = call float @llvm.experimental.constrained.fadd.f32(float %0, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %add
-; CHECK_LABEL: @host_02
+; CHECK-LABEL: @host_02
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
 }
 
 
 ; strictfp function is inlined into another strictfp function.
 
 define float @inlined_03(float %a) #0 {
 entry:
   %add = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.downward", metadata !"fpexcept.maytrap") #0
   ret float %add
 }
 
 define float @host_04(float %a) #0 {
 entry:
   %0 = call float @inlined_03(float %a) #0
   %add = call float @llvm.experimental.constrained.fadd.f32(float %0, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %add
-; CHECK_LABEL: @host_04
+; CHECK-LABEL: @host_04
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, metadata !"round.downward", metadata !"fpexcept.maytrap") #0
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
 }
 
 
 ; strictfp function is NOT inlined into ordinary function.
 
 define float @inlined_05(float %a) strictfp {
 entry:
   %add = call float @llvm.experimental.constrained.fadd.f32(float %a, float %a, metadata !"round.downward", metadata !"fpexcept.maytrap") #0
   ret float %add
 }
 
 define float @host_06(float %a) {
 entry:
   %0 = call float @inlined_05(float %a)
   %add = fadd float %0, 2.000000e+00
   ret float %add
-; CHECK_LABEL: @host_06
+; CHECK-LABEL: @host_06
 ; CHECK: call float @inlined_05(float %a)
 ; CHECK: fadd float %0, 2.000000e+00
 }
 
 
 ; Calls in inlined function must get strictfp attribute.
 
 declare float @func_ext(float);
 
 define float @inlined_07(float %a) {
 entry:
   %0 = call float @func_ext(float %a)
   %add = fadd float %0, %a
 
   ret float %add
 }
 
 define float @host_08(float %a) #0 {
 entry:
   %0 = call float @inlined_07(float %a) #0
   %add = call float @llvm.experimental.constrained.fadd.f32(float %0, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %add
-; CHECK_LABEL: @host_08
+; CHECK-LABEL: @host_08
 ; CHECK: call float @func_ext(float {{.*}}) #0
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float {{.*}}, metadata !"round.tonearest", metadata !"fpexcept.ignore") #0
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
 }
 
 
 ; Cloning particular instructions.
 
 ; fpext has two overloaded types.
 define double @inlined_09(float %a) {
 entry:
   %t = fpext float %a to double
   ret double %t
 }
 
 define double @host_10(float %a) #0 {
 entry:
   %0 = call double @inlined_09(float %a) #0
   %add = call double @llvm.experimental.constrained.fadd.f64(double %0, double 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret double %add
-; CHECK_LABEL: @host_10
+; CHECK-LABEL: @host_10
 ; CHECK: call double @llvm.experimental.constrained.fpext.f64.f32(float {{.*}}, metadata !"fpexcept.ignore") #0
 ; CHECK: call double @llvm.experimental.constrained.fadd.f64(double {{.*}}, double 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
 }
 
 ; fcmp does not depend on rounding mode and has metadata argument.
 define i1 @inlined_11(float %a, float %b) {
 entry:
   %t = fcmp oeq float %a, %b
   ret i1 %t
 }
 
 define i1 @host_12(float %a, float %b) #0 {
 entry:
   %add = call float @llvm.experimental.constrained.fadd.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   %cmp = call i1 @inlined_11(float %a, float %b) #0
   ret i1 %cmp
-; CHECK_LABEL: @host_12
+; CHECK-LABEL: @host_12
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float %a, float %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
 ; CHECK: call i1 @llvm.experimental.constrained.fcmp.f32(float {{.*}}, metadata !"oeq", metadata !"fpexcept.ignore") #0
 }
 
 ; Intrinsic 'ceil' has constrained variant.
 define float @inlined_13(float %a) {
 entry:
   %t = call float @llvm.ceil.f32(float %a)
   ret float %t
 }
 
 define float @host_14(float %a) #0 {
 entry:
   %0 = call float @inlined_13(float %a) #0
   %add = call float @llvm.experimental.constrained.fadd.f32(float %0, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret float %add
-; CHECK_LABEL: @host_14
+; CHECK-LABEL: @host_14
 ; CHECK: call float @llvm.experimental.constrained.ceil.f32(float %a, metadata !"fpexcept.ignore") #0
 ; CHECK: call float @llvm.experimental.constrained.fadd.f32(float {{.*}}, float 2.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
 }
 
 attributes #0 = { strictfp }
 
 declare float  @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
 declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
 declare i1     @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
 declare float  @llvm.experimental.constrained.ceil.f32(float, metadata)
 declare float  @llvm.ceil.f32(float)

llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll

 ;    B[i] = A[i] + 5;
 ;  }
 ;}
 
 @A = global [10240 x i64] zeroinitializer, align 16
 @B = global [10240 x i64] zeroinitializer, align 16
 
 
-; CHECK_LABEL: strided_load_i64
+; CHECK-LABEL: strided_load_i64
 ; CHECK: masked.gather
 define void @strided_load_i64() {
   br label %1
 
 ; <label>:1:                                      ; preds = %0, %1
   %indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
   %2 = getelementptr inbounds [10240 x i64], [10240 x i64]* @A, i64 0, i64 %indvars.iv
   %3 = load i64, i64* %2, align 16

llvm/test/Transforms/MergeFunc/alias.ll

 ; RUN: opt -S -mergefunc -mergefunc-use-aliases < %s | FileCheck %s
 
 ; Aliases should always be created for the weak functions, and
 ; for external functions if there is no local function
 
 ; CHECK: @external_external_2 = unnamed_addr alias void (float*), bitcast (void (i32*)* @external_external_1 to void (float*)*)
 ; CHECK: @weak_weak_2 = weak unnamed_addr alias void (float*), bitcast (void (i32*)* @0 to void (float*)*)
 ; CHECK: @weak_weak_1 = weak unnamed_addr alias void (i32*), void (i32*)* @0
 ; CHECK: @weak_external_1 = weak unnamed_addr alias void (i32*), bitcast (void (float*)* @weak_external_2 to void (i32*)*)
 ; CHECK: @external_weak_2 = weak unnamed_addr alias void (float*), bitcast (void (i32*)* @external_weak_1 to void (float*)*)
 ; CHECK: @weak_internal_1 = weak unnamed_addr alias void (i32*), bitcast (void (float*)* @weak_internal_2 to void (i32*)*)
 ; CHECK: @internal_weak_2 = weak unnamed_addr alias void (float*), bitcast (void (i32*)* @internal_weak_1 to void (float*)*)
 
 ; A strong backing function had to be created for the weak-weak pair
 
 ; CHECK: define private void @0(i32* %a) unnamed_addr
-; CHECK_NEXT: call void @dummy4()
+; CHECK-NEXT: call void @dummy4()
 
 ; These internal functions are dropped in favor of the external ones
 
 ; CHECK-NOT: define internal void @external_internal_2(float *%a) unnamed_addr
 ; CHECK-NOT: define internal void @internal_external_1(i32 *%a) unnamed_addr
 ; CHECK-NOT: define internal void @internal_external_1(i32 *%a) unnamed_addr
 ; CHECK-NOT: define internal void @internal_external_2(float *%a) unnamed_addr
 

llvm/test/Transforms/PGOProfile/PR41279.ll

16:
   br i1 %19, label %15, label %6
 ; USE: br i1 %19, label %15, label %6
 ; USE-SAME: !prof ![[BW_ENTRY2:[0-9]+]]
 }
 
 ; USE-DAG: {{![0-9]+}} = !{i32 1, !"ProfileSummary", {{![0-9]+}}}
 ; USE-DAG: {{![0-9]+}} = !{!"DetailedSummary", {{![0-9]+}}}
 ; USE-DAG: ![[FUNC_ENTRY_COUNT]] = !{!"function_entry_count", i64 8}
-; USE_DAG: ![[BW_ENTRY1]] = !{!"branch_weights", i32 5, i32 3}
-; USE_DAG: ![[BW_ENTRY2]] = !{!"branch_weights", i32 2, i32 1}
+; USE-DAG: ![[BW_ENTRY1]] = !{!"branch_weights", i32 5, i32 3}
+; USE-DAG: ![[BW_ENTRY2]] = !{!"branch_weights", i32 2, i32 1}
 

llvm/test/Transforms/PGOProfile/memop_clone.ll

 ; RUN: opt < %s -passes=pgo-memop-opt -verify-dom-info -S | FileCheck %s
 
 define i32 @test(i8* %a, i8* %b) !prof !1 {
-; CHECK_LABEL: test
+; CHECK-LABEL: test
 ; CHECK: MemOP.Case.3:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 3, i1 false)
 ; CHECK: MemOP.Case.2:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 2, i1 false)
 ; CHECK: MemOP.Default:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* %a, i32 undef, i1 false)
 ; CHECK: MemOP.Case.33:
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* %b, i64 3, i1 false)

llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll

 ; RUN: opt < %s -passes=pgo-instr-gen -S | FileCheck %s
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1)
 declare i32 @strlen(i8* nocapture)
 
-; CHECK_LABEL: test
+; CHECK-LABEL: test
 ; CHECK: %1 = zext i32 %c to i64
 ; CHECK:  call void @llvm.instrprof.value.profile(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @__profn_test, i32 0, i32 0), i64 {{[0-9]+}}, i64 %1, i32 1, i32 0)
 
 define void @test(i8* %a, i8* %p) {
   %c = call i32 @strlen(i8* %p)
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %p, i32 %c, i1 false)
   ret void
 }

llvm/test/tools/llvm-dwp/X86/tu_units_v5.s

 # This test checks if llvm-dwp can correctly generate the tu index section (v5).
 
 # RUN: llvm-mc -triple x86_64-unknown-linux %s -filetype=obj -o %t.o \
 # RUN:         -split-dwarf-file=%t.dwo -dwarf-version=5
 # RUN: llvm-dwp %t.dwo -o %t.dwp
 # RUN: llvm-dwarfdump -debug-info -debug-tu-index %t.dwp | FileCheck %s
 
 ## Note: In order to check whether the type unit index is generated
 ## there is no need to add the missing DIEs for the structure type of the type unit.
 
 # CHECK-DAG: .debug_info.dwo contents:
 # CHECK: 0x00000000: Type Unit: length = 0x00000017, format = DWARF32, version = 0x0005, unit_type = DW_UT_split_type, abbr_offset = 0x0000, addr_size = 0x08, name = '', type_signature = [[TUID1:.*]], type_offset = 0x0019 (next unit at 0x0000001b)
 # CHECK: 0x0000001b: Type Unit: length = 0x00000017, format = DWARF32, version = 0x0005, unit_type = DW_UT_split_type, abbr_offset = 0x0000, addr_size = 0x08, name = '', type_signature = [[TUID2:.*]], type_offset = 0x0019 (next unit at 0x00000036)
-# CHECK_DAG: .debug_tu_index contents:
+# CHECK-DAG: .debug_tu_index contents:
 # CHECK: version = 5, units = 2, slots = 4
 # CHECK: Index Signature          INFO                     ABBREV
 # CHECK:     1 [[TUID1]]          [0x00000000, 0x0000001b) [0x00000000, 0x00000010)
 # CHECK:     4 [[TUID2]]          [0x0000001b, 0x00000036) [0x00000000, 0x00000010)
 
     .section  .debug_info.dwo,"e",@progbits
     .long .Ldebug_info_dwo_end0-.Ldebug_info_dwo_start0 # Length of Unit
 .Ldebug_info_dwo_start0:

llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test

 # This test checks if llvm-dwp can deduplicate tu units (v5).
 
 # RUN: llvm-mc -triple x86_64-unknown-linux %p/../Inputs/type_dedup_v5/a.s -filetype=obj -o %t-a.o \
 # RUN:         -split-dwarf-file=%t-a.dwo -dwarf-version=5
 # RUN: llvm-mc -triple x86_64-unknown-linux %p/../Inputs/type_dedup_v5/b.s -filetype=obj -o %t-b.o \
 # RUN:         -split-dwarf-file=%t-b.dwo -dwarf-version=5
 # RUN: llvm-dwp %t-a.dwo %t-b.dwo -o %t.dwp
 # RUN: llvm-dwarfdump -debug-tu-index %t.dwp | FileCheck %s
 
-# CHECK_DAG: .debug_tu_index contents:
+# CHECK-DAG: .debug_tu_index contents:
 # CHECK: version = 5, units = 1, slots = 2

llvm/test/tools/llvm-objdump/MachO/disassemble-all.test

 // RUN: llvm-objdump --macho -d --full-leading-addr --print-imm-hex --no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s --check-prefix=TEXT
 
 TEXT:      (__TEXT,__text) section
-TEXT_NEXT: _main:
-TEXT_NEXT: 0000000100000f60 pushq %rbp
-TEXT_NEXT: 0000000100000f61 movq  %rsp, %rbp
-TEXT_NEXT: 0000000100000f64 subq  $0x10, %rsp
-TEXT_NEXT: 0000000100000f68 movl  $0x0, -0x4(%rbp)
-TEXT_NEXT: 0000000100000f6f callq _hello
-TEXT_NEXT: 0000000100000f74 xorl  %eax, %eax
-TEXT_NEXT: 0000000100000f76 addq  $0x10, %rsp
-TEXT_NEXT: 0000000100000f7a popq  %rbp
-TEXT_NEXT: 0000000100000f7b retq
+TEXT-NEXT: _main:
+TEXT-NEXT: 0000000100000f60 pushq %rbp
+TEXT-NEXT: 0000000100000f61 movq  %rsp, %rbp
+TEXT-NEXT: 0000000100000f64 subq  $0x10, %rsp
+TEXT-NEXT: 0000000100000f68 movl  $0x0, -0x4(%rbp)
+TEXT-NEXT: 0000000100000f6f callq _hello
+TEXT-NEXT: 0000000100000f74 xorl  %eax, %eax
+TEXT-NEXT: 0000000100000f76 addq  $0x10, %rsp
+TEXT-NEXT: 0000000100000f7a popq  %rbp
+TEXT-NEXT: 0000000100000f7b retq
 
 // RUN: llvm-objdump --macho -D --full-leading-addr --print-imm-hex --no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s --check-prefix=ALL
 
 ALL:      (__TEXT,__text) section
-ALL_NEXT: _main:
-ALL_NEXT: 0000000100000f60  pushq %rbp
-ALL_NEXT: 0000000100000f61  movq  %rsp, %rbp
-ALL_NEXT: 0000000100000f64  subq  $0x10, %rsp
-ALL_NEXT: 0000000100000f68  movl  $0x0, -0x4(%rbp)
-ALL_NEXT: 0000000100000f6f  callq _hello
-ALL_NEXT: 0000000100000f74  xorl  %eax, %eax
-ALL_NEXT: 0000000100000f76  addq  $0x10, %rsp
-ALL_NEXT: 0000000100000f7a  popq  %rbp
-ALL_NEXT: 0000000100000f7b  retq
+ALL-NEXT: _main:
+ALL-NEXT: 0000000100000f60  pushq %rbp
+ALL-NEXT: 0000000100000f61  movq  %rsp, %rbp
+ALL-NEXT: 0000000100000f64  subq  $0x10, %rsp
+ALL-NEXT: 0000000100000f68  movl  $0x0, -0x4(%rbp)
+ALL-NEXT: 0000000100000f6f  callq _hello
+ALL-NEXT: 0000000100000f74  xorl  %eax, %eax
+ALL-NEXT: 0000000100000f76  addq  $0x10, %rsp
+ALL-NEXT: 0000000100000f7a  popq  %rbp
+ALL-NEXT: 0000000100000f7b  retq
 ALL:      (__TEXT_EXEC,__text) section
-ALL_NEXT: _hello:
-ALL_NEXT: 0000000100001000  pushq %rbp
-ALL_NEXT: 0000000100001001  movq  %rsp, %rbp
-ALL_NEXT: 0000000100001004  subq  $0x10, %rsp
-ALL_NEXT: 0000000100001008  leaq  -0x71(%rip), %rdi ## literal pool for: "hello, world!\n"
-ALL_NEXT: 000000010000100f  movb  $0x0, %al
-ALL_NEXT: 0000000100001011  callq 0x100000f7c ## symbol stub for: _printf
-ALL_NEXT: 0000000100001016  movl  %eax, -0x4(%rbp)
-ALL_NEXT: 0000000100001019  addq  $0x10, %rsp
-ALL_NEXT: 000000010000101d  popq  %rbp
-ALL_NEXT: 000000010000101e  retq
+ALL-NEXT: _hello:
+ALL-NEXT: 0000000100001000  pushq %rbp
+ALL-NEXT: 0000000100001001  movq  %rsp, %rbp
+ALL-NEXT: 0000000100001004  subq  $0x10, %rsp
+ALL-NEXT: 0000000100001008  leaq  -0x71(%rip), %rdi ## literal pool for: "hello, world!\n"
+ALL-NEXT: 000000010000100f  movb  $0x0, %al
+ALL-NEXT: 0000000100001011  callq 0x100000f7c ## symbol stub for: _printf
+ALL-NEXT: 0000000100001016  movl  %eax, -0x4(%rbp)
+ALL-NEXT: 0000000100001019  addq  $0x10, %rsp
+ALL-NEXT: 000000010000101d  popq  %rbp
+ALL-NEXT: 000000010000101e  retq

llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test

 UNWIND1-NEXT:      Epilogue [
 UNWIND1-NEXT:        0xe002dac8          ; add sp, #2993280
 UNWIND1-NEXT:        0xd885              ; ldp d10, d11, [sp, #40]
 UNWIND1-NEXT:        0xd803              ; ldp d8, d9, [sp, #24]
 UNWIND1-NEXT:        0xd2c2              ; ldr x30, [sp, #16]
 UNWIND1-NEXT:        0x28                ; ldp x19, x20, [sp], #64
 UNWIND1-NEXT:        0xe4                ; end
 UNWIND1-NEXT:      ]
-UNWIND1_NEXT:    }
+UNWIND1-NEXT:    }
 
 
 UNWIND2:         ExceptionData {
 UNWIND2-NEXT:      FunctionLength: 72
 UNWIND2-NEXT:      Version: 0
 UNWIND2-NEXT:      ExceptionData: No
 UNWIND2-NEXT:      EpiloguePacked: No
 UNWIND2-NEXT:      EpilogueScopes: 2

mlir/test/Conversion/MemRefToSPIRV/alloc.mlir

func.func @alloc_dealloc_workgroup_mem(%arg0 : index, %arg1 : index) {
     memref.store %1, %0[%arg0, %arg1] : memref<4x5xi16, 3>
     memref.dealloc %0 : memref<4x5xi16, 3>
     return
   }
 }
 
 //       CHECK: spv.GlobalVariable @__workgroup_mem__{{[0-9]+}}
 //  CHECK-SAME:   !spv.ptr<!spv.struct<(!spv.array<20 x i32>)>, Workgroup>
-// CHECK_LABEL: spv.func @alloc_dealloc_workgroup_mem
+//  TODO-LABEL: spv.func @alloc_dealloc_workgroup_mem
 //       CHECK:   %[[VAR:.+]] = spv.mlir.addressof @__workgroup_mem__0
 //       CHECK:   %[[LOC:.+]] = spv.SDiv
 //       CHECK:   %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]]
 //       CHECK:   %{{.+}} = spv.Load "Workgroup" %[[PTR]] : i32
 //       CHECK:   %[[LOC:.+]] = spv.SDiv
 //       CHECK:   %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]]
 //       CHECK:   %{{.+}} = spv.AtomicAnd "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup>
 //       CHECK:   %{{.+}} = spv.AtomicOr "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup>

mlir/test/Dialect/Affine/loop-coalescing.mlir

scf.for %i = %c0 to %c10 step %c1 {
     // coalesced as well.  The preparation step for coalescing will inject the
     // subtraction operation unlike the IV remapping.
     // CHECK-NOT: scf.for
     // CHECK: arith.subi
     scf.for %j = %c0 to %c10 step %c1 {
       // The inner pair of loops is coalesced separately.
       // CHECK: scf.for
       scf.for %k = %i to %j step %c1 {
-        // CHECK_NOT: scf.for
+        // CHECK-NOT: scf.for
         scf.for %l = %i to %j step %c1 {
           "foo"() : () -> ()
         }
       }
     }
   }
   return
 }

mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir

 //  CHECK-DAG:   %[[INIT:.+]] = linalg.init_tensor [2, 3, 4, 5, 6, 7, 8, 9]
 //  CHECK-DAG:   %[[ARG1_RESHAPE:.+]] = tensor.collapse_shape %[[ARG1]] {{\[}}[0], [1, 2]{{\]}}
 //  CHECK-DAG:   %[[ARG2_RESHAPE:.+]] = tensor.collapse_shape %[[ARG2]] {{\[}}[0], [1, 2, 3]{{\]}}
 //  CHECK-DAG:   %[[INIT_RESHAPE:.+]] = tensor.collapse_shape %[[INIT]] {{\[}}[0], [1, 2], [3], [4, 5, 6], [7]{{\]}}
 //      CHECK:   %[[COLLAPSED_OP:.+]] = linalg.generic
 // CHECK-SAME:       indexing_maps = [#[[MAP0]], #[[MAP1]], #[[MAP2]], #[[MAP0]]]
 // CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "parallel", "parallel"]
 // CHECK-SAME:       ins(%[[ARG0]], %[[ARG1_RESHAPE]], %[[ARG2_RESHAPE]] :
-// CHECK_SAME:       outs(%[[INIT_RESHAPE]] :
+// CHECK-SAME:       outs(%[[INIT_RESHAPE]] :
 //      CHECK:   %[[RESULT_RESHAPE:.+]] = tensor.expand_shape %[[COLLAPSED_OP]] {{\[}}[0], [1, 2], [3], [4, 5, 6], [7]{{\]}}
 //      CHECK:   return %[[RESULT_RESHAPE]]
 
 //      CONTROL: func @fuse_by_collapsing(
 // CONTROL-SAME:   %[[ARG0:.+]]: tensor<2x12x5x336x9xi32>
 // CONTROL-SAME:   %[[ARG1:.+]]: tensor<2x3x4xi32>
 // CONTROL-SAME:   %[[ARG2:.+]]: tensor<5x6x7x8xi32>
 //      CONTROL:   %[[EXPAND:.+]] = tensor.expand_shape %[[ARG0]]

 //  CHECK-DAG:   %[[INIT:.+]] = linalg.init_tensor [2, 3, 4, 5, 6, 7, 8, 9]
 //  CHECK-DAG:   %[[ARG1_RESHAPE:.+]] = tensor.collapse_shape %[[ARG1]] {{\[}}[0, 1], [2]{{\]}}
 //  CHECK-DAG:   %[[ARG2_RESHAPE:.+]] = tensor.collapse_shape %[[ARG2]] {{\[}}[0], [1, 2, 3]{{\]}}
 //  CHECK-DAG:   %[[INIT_RESHAPE:.+]] = tensor.collapse_shape %[[INIT]] {{\[}}[0], [1, 2, 3], [4], [5, 6], [7]{{\]}}
 //      CHECK:   %[[COLLAPSED_OP:.+]] = linalg.generic
 // CHECK-SAME:       indexing_maps = [#[[MAP0]], #[[MAP1]], #[[MAP2]], #[[MAP3]]]
 // CHECK-SAME:       iterator_types = ["parallel", "parallel", "parallel", "parallel", "parallel"]
 // CHECK-SAME:       ins(%[[ARG0]], %[[ARG1_RESHAPE]], %[[ARG2_RESHAPE]] :
-// CHECK_SAME:       outs(%[[INIT_RESHAPE]] :
+// CHECK-SAME:       outs(%[[INIT_RESHAPE]] :
 //      CHECK:   %[[RESULT_RESHAPE:.+]] = tensor.expand_shape %[[COLLAPSED_OP]] {{\[}}[0], [1, 2, 3], [4], [5, 6], [7]{{\]}}
 //      CHECK:   return %[[RESULT_RESHAPE]]
 
 // -----
 
 // Dynamic case. Only checks things not covered by `fuse_by_collapsing` test above.
 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d7, d5, d6, d0, d1, d2, d3, d4)>
 #map1 = affine_map<(d0, d1, d2, d3, d4, d5, d6, d7) -> (d5, d6, d0)>

mlir/test/Dialect/Linalg/tile-and-fuse-no-fuse.mlir

func.func @tile_sizes_zero(%arg0 : tensor<?x?xf32>, %arg1 : tensor<?x?xf32>) -> tensor<?x?xf32> {
   //       MATMUL:   linalg.matmul
   %result = linalg.matmul ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
       outs(%fill : tensor<?x?xf32>) -> tensor<?x?xf32>
   func.return %result : tensor<?x?xf32>
 }
 
 // -----
 
-// UNARY_LABEL: @shape_only(
+// UNARY-LABEL: @shape_only(
 func.func @shape_only(%arg0 : tensor<?x?xf32>, %arg1 : tensor<?x?xf32>) -> tensor<?x?xf32> {
   %cst = arith.constant 0.0 : f32
 
   //       UNARY:   linalg.fill
   %0 = linalg.fill ins(%cst : f32) outs(%arg1 : tensor<?x?xf32>) -> tensor<?x?xf32>
 
   //       UNARY:   scf.for
   //       UNARY:     scf.for
   //   UNARY-NOT:       linalg.fill
   //       UNARY:       linalg.elemwise_unary
   %1 = linalg.elemwise_unary {fun = #linalg.unary_fn<exp>}
       ins(%arg0 : tensor<?x?xf32>) outs(%0 : tensor<?x?xf32>) -> tensor<?x?xf32>
   func.return %1 : tensor<?x?xf32>
 }

mlir/test/Dialect/MemRef/canonicalize.mlir

func.func @collapse_after_memref_cast_type_change(%arg0 : memref<?x512x1x1xf32>) -> memref<?x?xf32> {
   return %collapsed : memref<?x?xf32>
 }
 
 // -----
 
 // CHECK-LABEL:   func @collapse_after_memref_cast(
 // CHECK-SAME:      %[[INPUT:.*]]: memref<?x512x1x?xf32>) -> memref<?x?xf32> {
 // CHECK:           %[[COLLAPSED:.*]] = memref.collapse_shape %[[INPUT]]
-// CHECK_SAME:        {{\[\[}}0], [1, 2, 3]] : memref<?x512x1x?xf32> into memref<?x?xf32>
+// CHECK-SAME:        {{\[\[}}0], [1, 2, 3]] : memref<?x512x1x?xf32> into memref<?x?xf32>
 // CHECK:           return %[[COLLAPSED]] : memref<?x?xf32>
 func.func @collapse_after_memref_cast(%arg0 : memref<?x512x1x?xf32>) -> memref<?x?xf32> {
   %dynamic = memref.cast %arg0: memref<?x512x1x?xf32> to memref<?x?x?x?xf32>
   %collapsed = memref.collapse_shape %dynamic [[0], [1, 2, 3]] : memref<?x?x?x?xf32> into memref<?x?xf32>
   return %collapsed : memref<?x?xf32>
 }
 
 // -----
 
 // CHECK-LABEL:   func @collapse_after_memref_cast_type_change_dynamic(
 // CHECK-SAME:      %[[INPUT:.*]]: memref<1x1x1x?xi64>) -> memref<?x?xi64> {
 // CHECK:           %[[COLLAPSED:.*]] = memref.collapse_shape %[[INPUT]]
-// CHECK_SAME:        {{\[\[}}0, 1, 2], [3]] : memref<1x1x1x?xi64> into memref<1x?xi64>
+// CHECK-SAME:        {{\[\[}}0, 1, 2], [3]] : memref<1x1x1x?xi64> into memref<1x?xi64>
 // CHECK:           %[[DYNAMIC:.*]] = memref.cast %[[COLLAPSED]] :
 // CHECK-SAME:         memref<1x?xi64> to memref<?x?xi64>
 // CHECK:           return %[[DYNAMIC]] : memref<?x?xi64>
 func.func @collapse_after_memref_cast_type_change_dynamic(%arg0: memref<1x1x1x?xi64>) -> memref<?x?xi64> {
   %casted = memref.cast %arg0 : memref<1x1x1x?xi64> to memref<1x1x?x?xi64>
   %collapsed = memref.collapse_shape %casted [[0, 1, 2], [3]] : memref<1x1x?x?xi64> into memref<?x?xi64>
   return %collapsed : memref<?x?xi64>
 }

mlir/test/Dialect/SPIRV/IR/memory-ops.mlir

func.func @aligned_load_incorrect_attributes() -> () {
   return
 }
 
 // -----
 
 spv.module Logical GLSL450 {
   spv.GlobalVariable @var0 : !spv.ptr<f32, Input>
   spv.GlobalVariable @var1 : !spv.ptr<!spv.sampled_image<!spv.image<f32, Dim2D, IsDepth, Arrayed, SingleSampled, NeedSampler, Unknown>>, UniformConstant>
-  // CHECK_LABEL: @simple_load
+  // CHECK-LABEL: @simple_load
   spv.func @simple_load() -> () "None" {
     // CHECK: spv.Load "Input" {{%.*}} : f32
     %0 = spv.mlir.addressof @var0 : !spv.ptr<f32, Input>
     %1 = spv.Load "Input" %0 : f32
     %2 = spv.mlir.addressof @var1 : !spv.ptr<!spv.sampled_image<!spv.image<f32, Dim2D, IsDepth, Arrayed, SingleSampled, NeedSampler, Unknown>>, UniformConstant>
     // CHECK: spv.Load "UniformConstant" {{%.*}} : !spv.sampled_image
     %3 = spv.Load "UniformConstant" %2 : !spv.sampled_image<!spv.image<f32, Dim2D, IsDepth, Arrayed, SingleSampled, NeedSampler, Unknown>>
     spv.Return
   }
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.StoreOp
 //===----------------------------------------------------------------------===//
 
 func.func @simple_store(%arg0 : f32) -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Store  "Function" %0, %arg0 : f32
   spv.Store  "Function" %0, %arg0 : f32
   return
 }
 
-// CHECK_LABEL: @volatile_store
+// CHECK-LABEL: @volatile_store
 func.func @volatile_store(%arg0 : f32) -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Store  "Function" %0, %arg0 ["Volatile"] : f32
   spv.Store  "Function" %0, %arg0 ["Volatile"] : f32
   return
 }
 
-// CHECK_LABEL: @aligned_store
+// CHECK-LABEL: @aligned_store
 func.func @aligned_store(%arg0 : f32) -> () {
   %0 = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: spv.Store  "Function" %0, %arg0 ["Aligned", 4] : f32
   spv.Store  "Function" %0, %arg0 ["Aligned", 4] : f32
   return
 }
 
 // -----

mlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir

func.func @split_vector_transfer_read_2d(%A: memref<?x8xf32>, %i: index, %j: index) -> vector<4x8xf32> {
   // CHECK-SAME:     memref<4x8xf32> to memref<vector<4x8xf32>>
   //      CHECK:   store %[[slow]], %[[cast_alloc]][] : memref<vector<4x8xf32>>
   //      CHECK:   %[[yielded:.*]] = memref.cast %[[alloc]] :
   // CHECK-SAME:     memref<4x8xf32> to memref<?x8xf32>
   //      CHECK:   scf.yield %[[yielded]], %[[c0]], %[[c0]] :
   // CHECK-SAME:     memref<?x8xf32>, index, index
   //      CHECK: }
   //      CHECK: %[[res:.*]] = vector.transfer_read %[[ifres]]#0[%[[ifres]]#1, %[[ifres]]#2], %cst
-  // CHECK_SAME:   {in_bounds = [true, true]} : memref<?x8xf32>, vector<4x8xf32>
+  // CHECK-SAME:   {in_bounds = [true, true]} : memref<?x8xf32>, vector<4x8xf32>
 
   //  LINALG-DAG: %[[c0:.*]] = arith.constant 0 : index
   //  LINALG-DAG: %[[c4:.*]] = arith.constant 4 : index
   //  LINALG-DAG: %[[c8:.*]] = arith.constant 8 : index
   // alloca for boundary full tile
   //      LINALG: %[[alloc:.*]] = memref.alloca() {alignment = 32 : i64} : memref<4x8xf32>
   // %i + 4 <= dim(%A, 0)
   //      LINALG: %[[idx0:.*]] = affine.apply #[[$map_p4]]()[%[[i]]]
func.func @split_vector_transfer_read_2d(%A: memref<?x8xf32>, %i: index, %j: index) -> vector<4x8xf32> {
   //      LINALG:   %[[alloc_view:.*]] = memref.subview %[[alloc]][0, 0] [%[[sv0]], %[[sv1]]] [1, 1]
   //      LINALG:   memref.copy %[[sv]], %[[alloc_view]] : memref<?x?xf32, #[[$map_2d_stride_8x1]]> to memref<?x?xf32, #{{.*}}>
   //      LINALG:   %[[yielded:.*]] = memref.cast %[[alloc]] :
   // LINALG-SAME:     memref<4x8xf32> to memref<?x8xf32>
   //      LINALG:   scf.yield %[[yielded]], %[[c0]], %[[c0]] :
   // LINALG-SAME:     memref<?x8xf32>, index, index
   //      LINALG: }
   //      LINALG: %[[res:.*]] = vector.transfer_read %[[ifres]]#0[%[[ifres]]#1, %[[ifres]]#2], %cst
-  // LINALG_SAME:   {in_bounds = [true, true]} : memref<?x8xf32>, vector<4x8xf32>
+  // LINALG-SAME:   {in_bounds = [true, true]} : memref<?x8xf32>, vector<4x8xf32>
   %1 = vector.transfer_read %A[%i, %j], %f0 : memref<?x8xf32>, vector<4x8xf32>
 
   // LINALG: return %[[res]] : vector<4x8xf32>
   return %1: vector<4x8xf32>
 }
 
 // CHECK-LABEL: split_vector_transfer_read_strided_2d(
 //  CHECK-SAME: %[[A:[a-zA-Z0-9]*]]: memref

mlir/test/IR/dynamic.mlir

 // RUN: mlir-opt -allow-unregistered-dialect %s -split-input-file -verify-diagnostics | FileCheck %s
 // Verify that extensible dialects can register dynamic operations and types.
 
 //===----------------------------------------------------------------------===//
 // Dynamic type
 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: func @succeededDynamicTypeVerifier
 func.func @succeededDynamicTypeVerifier() {
   // CHECK: %{{.*}} = "unregistered_op"() : () -> !test.dynamic_singleton
   "unregistered_op"() : () -> !test.dynamic_singleton
   // CHECK-NEXT: "unregistered_op"() : () -> !test.dynamic_pair<i32, f64>
   "unregistered_op"() : () -> !test.dynamic_pair<i32, f64>
-  // CHECK_NEXT: %{{.*}} = "unregistered_op"() : () -> !test.dynamic_pair<!test.dynamic_pair<i32, f64>, !test.dynamic_singleton>
+  // CHECK-NEXT: %{{.*}} = "unregistered_op"() : () -> !test.dynamic_pair<!test.dynamic_pair<i32, f64>, !test.dynamic_singleton>
   "unregistered_op"() : () -> !test.dynamic_pair<!test.dynamic_pair<i32, f64>, !test.dynamic_singleton>
   return
 }
 
 // -----
 
 func.func @failedDynamicTypeVerifier() {
   // expected-error@+1 {{expected 0 type arguments, but had 1}}

 //===----------------------------------------------------------------------===//
 
 // CHECK-LABEL: func @succeededDynamicAttributeVerifier
 func.func @succeededDynamicAttributeVerifier() {
   // CHECK: "unregistered_op"() {test_attr = #test.dynamic_singleton} : () -> ()
   "unregistered_op"() {test_attr = #test.dynamic_singleton} : () -> ()
   // CHECK-NEXT: "unregistered_op"() {test_attr = #test.dynamic_pair<3 : i32, 5 : i32>} : () -> ()
   "unregistered_op"() {test_attr = #test.dynamic_pair<3 : i32, 5 : i32>} : () -> ()
-  // CHECK_NEXT: "unregistered_op"() {test_attr = #test.dynamic_pair<3 : i32, 5 : i32>} : () -> ()
+  // CHECK-NEXT: "unregistered_op"() {test_attr = #test.dynamic_pair<#test.dynamic_pair<3 : i32, 5 : i32>, f64>} : () -> ()
   "unregistered_op"() {test_attr = #test.dynamic_pair<#test.dynamic_pair<3 : i32, 5 : i32>, f64>} : () -> ()
   return
 }
 
 // -----
 
 func.func @failedDynamicAttributeVerifier() {
   // expected-error@+1 {{expected 0 attribute arguments, but had 1}}

mlir/test/mlir-tblgen/op-decl-and-defs.td

 
 // Check default value for collective params builder. Check that other builders
 // are generated as well.
 def NS_HCollectiveParamsOp : NS_Op<"op_collective_params", []> {
   let arguments = (ins AnyType:$a);
   let results = (outs AnyType:$b);
 }
 
-// CHECK_LABEL: class HCollectiveParamsOp :
+// CHECK-LABEL: class HCollectiveParamsOp :
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type b, ::mlir::Value a);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::Value a);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {})
 
 // Check suppression of "separate arg, separate result" build method for an op
 // with single variadic arg and single variadic result (since it will be
 // ambiguous with the collective params build method).
 def NS_HCollectiveParamsSuppress0Op : NS_Op<"op_collective_suppress0", []> {
   let arguments = (ins Variadic<I32>:$a);
   let results = (outs Variadic<I32>:$b);
 }
 
-// CHECK_LABEL: class HCollectiveParamsSuppress0Op :
+// CHECK-LABEL: class HCollectiveParamsSuppress0Op :
 // CHECK-NOT: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange b, ::mlir::ValueRange a);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 
 // Check suppression of "separate arg, collective result" build method for an op
 // with single variadic arg and non variadic result (since it will be
 // ambiguous with the collective params build method).
 def NS_HCollectiveParamsSuppress1Op : NS_Op<"op_collective_suppress1", []> {
   let arguments = (ins Variadic<I32>:$a);
   let results = (outs I32:$b);
 }
 
-// CHECK_LABEL: class HCollectiveParamsSuppress1Op :
+// CHECK-LABEL: class HCollectiveParamsSuppress1Op :
 // CHECK-NOT: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange b, ::mlir::ValueRange a);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 
 // Check suppression of "separate arg, collective result" build method for an op
 // with single variadic arg and > 1 variadic result (since it will be
 // ambiguous with the collective params build method). Note that "separate arg,
 // separate result" build method should be generated in this case as its not
 // ambiguous with the collective params build method.
 def NS_HCollectiveParamsSuppress2Op : NS_Op<"op_collective_suppress2", [SameVariadicResultSize]> {
   let arguments = (ins Variadic<I32>:$a);
   let results = (outs Variadic<I32>:$b, Variadic<F32>:$c);
 }
-// CHECK_LABEL: class HCollectiveParamsSuppress2Op :
+// CHECK-LABEL: class HCollectiveParamsSuppress2Op :
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange b, ::mlir::TypeRange c, ::mlir::ValueRange a);
 // CHECK-NOT: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange b, ::mlir::ValueRange a);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 
 // Check default value of `attributes` for the `genUseOperandAsResultTypeCollectiveParamBuilder` builder
 def NS_IOp : NS_Op<"op_with_same_operands_and_result_types_trait", [SameOperandsAndResultType]> {
   let arguments = (ins AnyType:$a, AnyType:$b);
   let results = (outs AnyType:$r);
 }
-// CHECK_LABEL: class IOp :
+// CHECK-LABEL: class IOp :
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::Value a, ::mlir::Value b);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Value a, ::mlir::Value b);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::Value a, ::mlir::Value b);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 
 // Check default value of `attributes` for the `genInferredTypeCollectiveParamBuilder` builder
 def NS_JOp : NS_Op<"op_with_InferTypeOpInterface_interface", [DeclareOpInterfaceMethods<InferTypeOpInterface>]> {
   let arguments = (ins AnyType:$a, AnyType:$b);
   let results = (outs AnyType:$r);
 }
-// CHECK_LABEL: class JOp :
+// CHECK-LABEL: class JOp :
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::Value a, ::mlir::Value b);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Value a, ::mlir::Value b);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::Value a, ::mlir::Value b);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 
 // Test usage of TraitList getting flattened during emission.
 def NS_KOp : NS_Op<"k_op", [IsolatedFromAbove,

 // CHECK-LABEL: NS::KWithTraitOp declarations
 // CHECK:       class KWithTraitOp : public ::mlir::Op<KWithTraitOp
 // CHECK-SAME:      SomeNamespace::TestTrait
 
 def NS_LOp : NS_Op<"op_with_same_operands_and_result_types_unwrapped_attr", [SameOperandsAndResultType]> {
   let arguments = (ins AnyType:$a, AnyType:$b, I32Attr:$attr1);
   let results = (outs AnyType:$r);
 }
-// CHECK_LABEL: class LOp :
+// CHECK-LABEL: class LOp :
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::Value a, ::mlir::Value b, ::mlir::IntegerAttr attr1);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Value a, ::mlir::Value b, ::mlir::IntegerAttr attr1);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::Value a, ::mlir::Value b, ::mlir::IntegerAttr attr1);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::Value a, ::mlir::Value b, uint32_t attr1);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Value a, ::mlir::Value b, uint32_t attr1);
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::Value a, ::mlir::Value b, uint32_t attr1);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});
 // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {});