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chill (Momchil Velikov)
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May 24 2017, 3:29 AM (139 w, 5 d)

Recent Activity

Today

chill added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

I've a added a few words of documentation here: https://reviews.llvm.org/D73459

Mon, Jan 27, 3:29 AM
chill created D73459: [ARM] Add documentation for -march= and -mfpu= copmmand line options.
Mon, Jan 27, 3:29 AM

Fri, Jan 24

chill added inline comments to D73176: [ARM] Fix dropped dollar sign from symbols in branch targets.
Fri, Jan 24, 6:58 AM · Restricted Project
chill added inline comments to D73176: [ARM] Fix dropped dollar sign from symbols in branch targets.
Fri, Jan 24, 6:32 AM · Restricted Project
chill added a comment to D73176: [ARM] Fix dropped dollar sign from symbols in branch targets.

There's obviously lexer ambiguity in interpreting, e.g. the character sequence $4 as a single <identifier> token, or as the two tokens $ and a <constant>.
Looks like the tokenisation needs to be context dependent: in certain directives (.global $4) and instructions (b $4) the sequence needs to be interpreted a single identifier, and
in other contexts (ldr r0, [r0, $4]) as two separate tokens.

Fri, Jan 24, 6:31 AM · Restricted Project

Thu, Jan 23

chill added inline comments to D73176: [ARM] Fix dropped dollar sign from symbols in branch targets.
Thu, Jan 23, 7:07 AM · Restricted Project

Mon, Jan 20

chill added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

I don't like fiddling with the ABI based on CPU features; it's common to mix code with different CPU features enabled (particularly for desktop/mobile CPUs; less so on microcontrollers, but it can still happen).

If we want to support some other ABI for performance reasons, we should make the user request it explicitly.

Absolutely, we are definitely not proposing a new ABI.

Mon, Jan 20, 6:08 AM

Fri, Jan 17

chill added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

It is not redundant with respect to -mfloat-abi=soft, as it leaves the door open to passing integer vector arguments via the so-called "FP registers".

So then "-mfloat-abi=hard -mfpu=none" means "pass floating-point values in registers, but don't use any other floating-point operations"?

No, it does not mean that, at least not yet, and it's not immediately obvious if that would be of any advantage. But it does affect integer vectors.

Fri, Jan 17, 4:25 AM

Thu, Jan 16

chill added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

It is not redundant with respect to -mfloat-abi=soft, as it leaves the door open to passing integer vector arguments via the so-called "FP registers".

So then "-mfloat-abi=hard -mfpu=none" means "pass floating-point values in registers, but don't use any other floating-point operations"?

No, it does not mean that, at least not yet, and it's not immediately obvious if that would be of any advantage. But it does affect integer vectors.

Thu, Jan 16, 3:22 AM

Wed, Jan 15

chill added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

In terms of the user-visible behavior, I guess my question is whether it would make sense to add "-mfpu=mve"/"-mfpu=mve.fp", and make "-mfpu=none" mean "no FP registers". I'm not sure why a user would specify "-mfpu=none" if they didn't want to disable the floating-point registers altogether.

Wed, Jan 15, 11:18 AM
chill updated the diff for D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.
Wed, Jan 15, 10:40 AM
chill updated the diff for D72762: [ARM][TargetParser] Improve handling of dependencies between target features.
Wed, Jan 15, 8:55 AM · Restricted Project
chill planned changes to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.
Wed, Jan 15, 5:52 AM
chill added inline comments to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.
Wed, Jan 15, 5:52 AM
chill added a parent revision for D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none: D72762: [ARM][TargetParser] Improve handling of dependencies between target features.
Wed, Jan 15, 5:52 AM
chill added a child revision for D72762: [ARM][TargetParser] Improve handling of dependencies between target features: D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.
Wed, Jan 15, 5:52 AM · Restricted Project
chill created D72762: [ARM][TargetParser] Improve handling of dependencies between target features.
Wed, Jan 15, 5:52 AM · Restricted Project

Tue, Jan 14

chill added inline comments to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.
Tue, Jan 14, 3:50 AM
chill added a comment to D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.

I guess this makes probably sense, but just checking why this should have the effect of enabling MVE-I? Is there prior art -mfpu=none has a similar effect?

Tue, Jan 14, 3:24 AM

Mon, Jan 13

chill added reviewers for D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none: simon_tatham, SjoerdMeijer, efriedma.
Mon, Jan 13, 10:54 AM
chill created D72633: [ARM][MVE] Fix a corner case of checking for MVE-I with -mfpu=none.
Mon, Jan 13, 10:54 AM

Thu, Jan 9

chill committed rG173b711e83d7: [ARM][MVE] MVE-I should not be disabled by -mfpu=none (authored by chill).
[ARM][MVE] MVE-I should not be disabled by -mfpu=none
Thu, Jan 9, 6:09 AM
chill closed D71843: [ARM][MVE] MVE-I should not be disabled by -mfpu=none.
Thu, Jan 9, 6:09 AM · Restricted Project, Restricted Project
chill updated the diff for D71843: [ARM][MVE] MVE-I should not be disabled by -mfpu=none.
Thu, Jan 9, 6:09 AM · Restricted Project, Restricted Project

Wed, Jan 8

chill resigned from D72215: [AArch64] Add function attribute "patchable-function-entry" to add NOPs at function entry.
Wed, Jan 8, 2:11 AM · Restricted Project

Tue, Jan 7

chill updated the diff for D71843: [ARM][MVE] MVE-I should not be disabled by -mfpu=none.
Tue, Jan 7, 3:32 AM · Restricted Project, Restricted Project

Mon, Jan 6

chill added a comment to D71843: [ARM][MVE] MVE-I should not be disabled by -mfpu=none.

Ping?

Mon, Jan 6, 2:54 AM · Restricted Project, Restricted Project

Dec 23 2019

chill created D71843: [ARM][MVE] MVE-I should not be disabled by -mfpu=none.
Dec 23 2019, 9:15 AM · Restricted Project, Restricted Project

Dec 13 2019

chill committed rG8e8e3181aa52: [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm (authored by chill).
[ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm
Dec 13 2019, 10:25 AM
chill closed D71266: [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm.
Dec 13 2019, 10:24 AM · Restricted Project
chill retitled D71266: [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm from [ARM] Return a number of micro-ops for vlldm/vlstm to [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm.
Dec 13 2019, 10:24 AM · Restricted Project
chill committed rGd53e61863d48: [AArch64] Emit PAC/BTI .note.gnu.property flags (authored by chill).
[AArch64] Emit PAC/BTI .note.gnu.property flags
Dec 13 2019, 9:39 AM
chill closed D71019: [AArch64] Emit PAC/BTI .note.gnu.property flags.
Dec 13 2019, 9:39 AM · Restricted Project
chill added a comment to D71129: [ARM][CMSE] Implement CMSE attributes.

Ping?

Dec 13 2019, 7:11 AM

Dec 12 2019

chill closed D70817: [ARM][CMSE] Add CMSE header and builtins.

Closing manually, since I misspelled "Diferential" in the commit message.

Dec 12 2019, 7:36 AM
chill committed rG600d123c6ff1: [ARM][CMSE] Add CMSE header and builtins (authored by chill).
[ARM][CMSE] Add CMSE header and builtins
Dec 12 2019, 7:02 AM
chill updated the diff for D71266: [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm.
Dec 12 2019, 2:43 AM · Restricted Project

Dec 11 2019

chill added a comment to D71266: [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm.

Is there some reason we can't handle these using tablegen'ed data, like other instructions?

In a sense we do use tablegen, it just that tablegen says "defer that to C++ code". (cf. "dynamic uops" in ARMScheduleA8.td and ARMScheduleA9.td).

Dec 11 2019, 3:51 AM · Restricted Project

Dec 10 2019

chill created D71266: [ARM] Fix in ICE when retrieving the number of micro-ops for vlldm/vlstm.
Dec 10 2019, 6:29 AM · Restricted Project

Dec 9 2019

chill updated the diff for D70817: [ARM][CMSE] Add CMSE header and builtins.
Dec 9 2019, 7:47 AM
chill added inline comments to D71019: [AArch64] Emit PAC/BTI .note.gnu.property flags.
Dec 9 2019, 6:13 AM · Restricted Project
chill updated the diff for D71019: [AArch64] Emit PAC/BTI .note.gnu.property flags.
Dec 9 2019, 6:07 AM · Restricted Project
chill added inline comments to D70817: [ARM][CMSE] Add CMSE header and builtins.
Dec 9 2019, 3:19 AM

Dec 6 2019

chill created D71129: [ARM][CMSE] Implement CMSE attributes.
Dec 6 2019, 9:53 AM
chill updated the diff for D70817: [ARM][CMSE] Add CMSE header and builtins.
Dec 6 2019, 3:25 AM

Dec 4 2019

chill added reviewers for D71019: [AArch64] Emit PAC/BTI .note.gnu.property flags: psmith, t.p.northover.
Dec 4 2019, 9:04 AM · Restricted Project
chill created D71019: [AArch64] Emit PAC/BTI .note.gnu.property flags.
Dec 4 2019, 8:17 AM · Restricted Project

Nov 28 2019

chill added reviewers for D70817: [ARM][CMSE] Add CMSE header and builtins: snidertm, sigvartmh, dmgreen, hug-dev.
Nov 28 2019, 6:16 AM
chill created D70817: [ARM][CMSE] Add CMSE header and builtins.
Nov 28 2019, 6:11 AM

Nov 25 2019

chill committed rG09555ce07176: [ARM] Generate CMSE instructions from CMSE intrinsics (authored by chill).
[ARM] Generate CMSE instructions from CMSE intrinsics
Nov 25 2019, 10:36 AM
chill closed D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.
Nov 25 2019, 10:36 AM · Restricted Project

Nov 22 2019

chill updated the diff for D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.
Nov 22 2019, 7:18 AM · Restricted Project
chill added a comment to D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.

Will commit next week, since we're on the move and might not be able to promptly react to breakage.

Nov 22 2019, 7:18 AM · Restricted Project
chill added a comment to D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.

Question: Is this sufficient to generate code which sets the processor into non-secure handler/thread mode? I'm fine with not having everything clean up all the registeres etc. I'm just going to use it for testing purposes at the moment to prepare a build system to handle llvm as a back-end for ARMv8-m.

Nov 22 2019, 6:14 AM · Restricted Project

Nov 20 2019

chill updated the diff for D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.
Nov 20 2019, 11:16 AM · Restricted Project
sigvartmh awarded D70407: [ARM] Generate CMSE instructions from CMSE intrinsics a Yellow Medal token.
Nov 20 2019, 4:51 AM · Restricted Project

Nov 19 2019

chill planned changes to D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.
Nov 19 2019, 10:06 AM · Restricted Project
chill updated subscribers of D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.

Maybe I'm doing something wrong tried to apply these patches but when trying to build code which uses cmse I get

Cannot select: intrinsic %llvm.arm.cmse.tt
fatal error: error in backend: Cannot select: intrinsic %llvm.arm.cmse.tt
clang-10: error: clang frontend command failed with exit code 70 (use -v to see invocation)

Nov 19 2019, 3:06 AM · Restricted Project

Nov 18 2019

chill created D70407: [ARM] Generate CMSE instructions from CMSE intrinsics.
Nov 18 2019, 10:31 AM · Restricted Project
chill added reviewers for D70407: [ARM] Generate CMSE instructions from CMSE intrinsics: snidertm, dmgreen.
Nov 18 2019, 10:31 AM · Restricted Project

Nov 15 2019

chill committed rGaa6d48fa70eb: Implement target(branch-protection) attribute for AArch64 (authored by chill).
Implement target(branch-protection) attribute for AArch64
Nov 15 2019, 7:43 AM
chill closed D68711: Implement target(branch-protection) attribute for AArch64.
Nov 15 2019, 7:42 AM · Restricted Project, Restricted Project

Nov 14 2019

chill added a reviewer for D68711: Implement target(branch-protection) attribute for AArch64: ostannard.

Ping?

Nov 14 2019, 2:52 AM · Restricted Project, Restricted Project

Nov 10 2019

chill updated the diff for D68916: [ARM] Accept ldrb.w mnemonic for certain addressing modes (PR43382).

Added some comments.

Nov 10 2019, 4:03 AM · Restricted Project
chill added a comment to D66459: Make ShrinkWrap more consistent..

V8 needs to save a specific set of registers at the entry of a function depending on the type of this function. For example, a JS function needs to save r0, r1,r7 along with fp, lr. And a wasm function needs to spill r3 at sp - 16.

Nov 10 2019, 2:46 AM · Restricted Project

Nov 6 2019

chill updated the diff for D68711: Implement target(branch-protection) attribute for AArch64.

Moved parsing of branch protection spec to TargetParser.

Nov 6 2019, 10:27 AM · Restricted Project, Restricted Project
chill committed rGd91ea7fc6fd0: [AArch64] Move the branch relaxation pass after BTI insertion (authored by chill).
[AArch64] Move the branch relaxation pass after BTI insertion
Nov 6 2019, 4:47 AM
chill closed D69118: [AArch64] Move the branch relaxation pass after BTI insertion.
Nov 6 2019, 4:47 AM · Restricted Project

Nov 1 2019

chill updated the diff for D69118: [AArch64] Move the branch relaxation pass after BTI insertion.

Rebase, retest.
A wild CFGuardLongjmpPass appeared in the meantime, but it does not create instructions, only symbols, AFAICT, so
its placement is fine.

Nov 1 2019, 10:58 AM · Restricted Project
chill committed rG7849862f4693: [AArch64] Output the pseudo SPACE in asm and object files (authored by chill).
[AArch64] Output the pseudo SPACE in asm and object files
Nov 1 2019, 8:03 AM
chill closed D69185: [AArch64] Output the pseudo SPACE in asm and object files.
Nov 1 2019, 8:02 AM · Restricted Project
chill updated the diff for D69185: [AArch64] Output the pseudo SPACE in asm and object files.
Nov 1 2019, 5:58 AM · Restricted Project

Oct 30 2019

chill updated the diff for D68711: Implement target(branch-protection) attribute for AArch64.

Moved parsing out of Attr.td to TargetInfo, following the example (good or bad) of validateOutputConstraint or validateGlobalregisterVariable ;)
Now issue a warning if attribute is not supported by target, like for other unsupported target options.

Oct 30 2019, 8:36 AM · Restricted Project, Restricted Project

Oct 29 2019

chill planned changes to D68711: Implement target(branch-protection) attribute for AArch64.
Oct 29 2019, 6:43 AM · Restricted Project, Restricted Project

Oct 25 2019

chill accepted D69297: [ARM][AArch64] Implement __arm_rsrf, __arm_rsrf64, __arm_wsrf & __arm_wsrf64.
Oct 25 2019, 4:19 AM · Restricted Project
chill added a comment to D69185: [AArch64] Output the pseudo SPACE in asm and object files.

Ping?

Oct 25 2019, 12:20 AM · Restricted Project

Oct 24 2019

chill added a comment to D68916: [ARM] Accept ldrb.w mnemonic for certain addressing modes (PR43382).

Ping?

Oct 24 2019, 12:12 AM · Restricted Project

Oct 22 2019

chill added a comment to D69297: [ARM][AArch64] Implement __arm_rsrf, __arm_rsrf64, __arm_wsrf & __arm_wsrf64.

I'm a bit unsure how much we're willing to pollute the namespace: in this particular case looking at the four __bitcast_* functions.
I appreciate that getting rid of them would require emitting LLVM IR bitcasts, so a bit more effort compared to the macro approach.

Oct 22 2019, 5:43 AM · Restricted Project
chill added reviewers for D69297: [ARM][AArch64] Implement __arm_rsrf, __arm_rsrf64, __arm_wsrf & __arm_wsrf64: t.p.northover, efriedma.
Oct 22 2019, 5:43 AM · Restricted Project
chill edited reviewers for D69297: [ARM][AArch64] Implement __arm_rsrf, __arm_rsrf64, __arm_wsrf & __arm_wsrf64, added: chill; removed: momchil.velikov.
Oct 22 2019, 4:02 AM · Restricted Project
chill added a comment to D68711: Implement target(branch-protection) attribute for AArch64.

Ping?

Oct 22 2019, 12:21 AM · Restricted Project, Restricted Project

Oct 21 2019

chill accepted D69012: [Headers] Fix compatibility between arm_acle.h and intrin.h.
Oct 21 2019, 12:30 AM · Restricted Project

Oct 18 2019

chill added reviewers for D69185: [AArch64] Output the pseudo SPACE in asm and object files: t.p.northover, ostannard.
Oct 18 2019, 10:48 AM · Restricted Project
chill added a parent revision for D69118: [AArch64] Move the branch relaxation pass after BTI insertion: D69185: [AArch64] Output the pseudo SPACE in asm and object files.
Oct 18 2019, 10:48 AM · Restricted Project
chill added a comment to D69118: [AArch64] Move the branch relaxation pass after BTI insertion.

For testing, we have the SPACE pseudo-instruction, which can be used to emulate very large basic blocks, maybe you could reduce your reproducer using that?

Oct 18 2019, 10:48 AM · Restricted Project
chill created D69185: [AArch64] Output the pseudo SPACE in asm and object files.
Oct 18 2019, 10:48 AM · Restricted Project
chill added a child revision for D69185: [AArch64] Output the pseudo SPACE in asm and object files: D69118: [AArch64] Move the branch relaxation pass after BTI insertion.
Oct 18 2019, 10:48 AM · Restricted Project
chill updated the diff for D69118: [AArch64] Move the branch relaxation pass after BTI insertion.
Oct 18 2019, 10:48 AM · Restricted Project

Oct 17 2019

chill added inline comments to D68916: [ARM] Accept ldrb.w mnemonic for certain addressing modes (PR43382).
Oct 17 2019, 10:52 AM · Restricted Project
chill updated the diff for D69118: [AArch64] Move the branch relaxation pass after BTI insertion.

Updated pipeline tests.

Oct 17 2019, 10:14 AM · Restricted Project
chill created D69118: [AArch64] Move the branch relaxation pass after BTI insertion.
Oct 17 2019, 10:04 AM · Restricted Project

Oct 15 2019

chill updated the diff for D68711: Implement target(branch-protection) attribute for AArch64.
Oct 15 2019, 3:47 AM · Restricted Project, Restricted Project

Oct 14 2019

chill added a comment to D68916: [ARM] Accept ldrb.w mnemonic for certain addressing modes (PR43382).

Adding aliases seems like the right approach; we have aliases for a bunch of other instructions.

I'm not sure why you need the AsmMatchConverter, though; needs a comment to explain.

Why is Rt listed twice here?

Oct 14 2019, 3:56 PM · Restricted Project
chill added a comment to D68862: [ARM] Allocatable Global Register Variables for ARM.

IMHO, since reserved registes are per-function, this strongly suggests implementation as function attribute(s), rather than subtarget features (also for the pre-existing r9).

What do you mean reserved registers are per-function? That sounds like you're describing local register variables, which I don't believe Clang has any support for (and there aren't a great deal of use-cases for anyway).
We're specifically talking about global usage here.

Oct 14 2019, 9:11 AM · Restricted Project, Restricted Project

Oct 12 2019

chill created D68916: [ARM] Accept ldrb.w mnemonic for certain addressing modes (PR43382).
Oct 12 2019, 11:22 AM · Restricted Project

Oct 11 2019

chill added inline comments to D68862: [ARM] Allocatable Global Register Variables for ARM.
Oct 11 2019, 6:03 AM · Restricted Project, Restricted Project
chill added a comment to D68862: [ARM] Allocatable Global Register Variables for ARM.

TBH, I quite dislike the creeping abuse of SubtargetFeatures as code generation options.

Oct 11 2019, 6:03 AM · Restricted Project, Restricted Project

Oct 9 2019

chill committed rGd037a5f06538: [AArch64] Ensure no tagged memory is left in the unallocated portion of the… (authored by chill).
[AArch64] Ensure no tagged memory is left in the unallocated portion of the…
Oct 9 2019, 9:31 AM
chill closed D68469: [AArch64] Ensure no tagged memory is left in the unallocated portion of the stack.
Oct 9 2019, 9:31 AM · Restricted Project
chill committed rL374182: [AArch64] Ensure no tagged memory is left in the unallocated portion of the.
[AArch64] Ensure no tagged memory is left in the unallocated portion of the
Oct 9 2019, 9:31 AM