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alex-t (Alexander)
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User Since
Jul 26 2016, 7:17 AM (309 w, 6 d)

Recent Activity

Wed, Jun 29

alex-t added inline comments to D128252: [AMDGPU] VGPR to SGPR copies lowering.
Wed, Jun 29, 1:49 PM · Restricted Project, Restricted Project

Tue, Jun 28

alex-t updated the diff for D128252: [AMDGPU] VGPR to SGPR copies lowering.

LIT tests updated

Tue, Jun 28, 7:31 AM · Restricted Project, Restricted Project

Fri, Jun 24

alex-t added reviewers for D128252: [AMDGPU] VGPR to SGPR copies lowering: rampitec, foad.
Fri, Jun 24, 3:35 AM · Restricted Project, Restricted Project
alex-t updated the diff for D128252: [AMDGPU] VGPR to SGPR copies lowering.

LIT tests changed. Description updated.

Fri, Jun 24, 3:33 AM · Restricted Project, Restricted Project

Tue, Jun 21

alex-t updated the diff for D128252: [AMDGPU] VGPR to SGPR copies lowering.

debug output fixed

Tue, Jun 21, 2:27 AM · Restricted Project, Restricted Project
alex-t requested review of D128252: [AMDGPU] VGPR to SGPR copies lowering.
Tue, Jun 21, 2:11 AM · Restricted Project, Restricted Project

Apr 1 2022

alex-t accepted D122737: [AMDGPU] Fix crash in SIOptimizeExecMaskingPreRA.

LGTM if we do not want to change the COPY processing in the SIInstrInfo::isOperandLegal

Apr 1 2022, 11:03 AM · Restricted Project, Restricted Project
alex-t added inline comments to D122737: [AMDGPU] Fix crash in SIOptimizeExecMaskingPreRA.
Apr 1 2022, 11:02 AM · Restricted Project, Restricted Project

Mar 30 2022

alex-t accepted D122653: [AMDGPU] Document the intended semantics of llvm.amdgcn.s.buffer.load.
Mar 30 2022, 1:46 PM · Restricted Project, Restricted Project
alex-t added inline comments to D122653: [AMDGPU] Document the intended semantics of llvm.amdgcn.s.buffer.load.
Mar 30 2022, 3:49 AM · Restricted Project, Restricted Project

Mar 22 2022

alex-t committed rG7636c9a9297d: [AMDGPU] use scalar shift for SALU users in frame index elimination (authored by alex-t).
[AMDGPU] use scalar shift for SALU users in frame index elimination
Mar 22 2022, 5:16 AM · Restricted Project
alex-t committed rG0a488cba2c1b: [AMDGPU] use scalar shift for SALU users in frame index elimination (authored by alex-t).
[AMDGPU] use scalar shift for SALU users in frame index elimination
Mar 22 2022, 3:43 AM · Restricted Project
alex-t closed D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.
Mar 22 2022, 3:43 AM · Restricted Project, Restricted Project

Mar 21 2022

alex-t updated the diff for D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.

test updated

Mar 21 2022, 2:08 PM · Restricted Project, Restricted Project
alex-t committed rGa0ea7ec90ff8: [AMDGPU] divergence patterns for the BUILD_VECTOR i16, undef expansion. (authored by alex-t).
[AMDGPU] divergence patterns for the BUILD_VECTOR i16, undef expansion.
Mar 21 2022, 1:11 PM · Restricted Project
alex-t closed D122068: [AMDGPU] divergence patterns for the BUILD_VECTOR i16, undef expansion..
Mar 21 2022, 1:11 PM · Restricted Project, Restricted Project

Mar 19 2022

alex-t requested review of D122068: [AMDGPU] divergence patterns for the BUILD_VECTOR i16, undef expansion..
Mar 19 2022, 8:15 AM · Restricted Project, Restricted Project
alex-t added inline comments to D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.
Mar 19 2022, 6:32 AM · Restricted Project, Restricted Project
alex-t updated the diff for D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.

test case for SCC multiple defs added. Unnecessary compiler options removed from the test command line.

Mar 19 2022, 6:30 AM · Restricted Project, Restricted Project

Mar 18 2022

alex-t added inline comments to D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.
Mar 18 2022, 12:50 PM · Restricted Project, Restricted Project
alex-t added inline comments to D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.
Mar 18 2022, 11:41 AM · Restricted Project, Restricted Project
alex-t updated the diff for D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.

formatting

Mar 18 2022, 8:33 AM · Restricted Project, Restricted Project
alex-t added inline comments to D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.
Mar 18 2022, 7:03 AM · Restricted Project, Restricted Project
alex-t updated the diff for D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.

IsSALU check chamged to query operand register class.
MIR test were made auto-generated

Mar 18 2022, 7:02 AM · Restricted Project, Restricted Project
alex-t updated the diff for D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.

SCC clobbering case added. MIR test simplified.

Mar 18 2022, 5:32 AM · Restricted Project, Restricted Project

Mar 12 2022

alex-t requested review of D121524: [AMDGPU] use scalar shift for SALU users in frame index elimination.
Mar 12 2022, 7:28 AM · Restricted Project, Restricted Project

Mar 10 2022

alex-t committed rGd159b4444c88: [AMDGPU] Enable divergence predicates for negative inline constant subtraction (authored by alex-t).
[AMDGPU] Enable divergence predicates for negative inline constant subtraction
Mar 10 2022, 4:03 AM · Restricted Project
alex-t closed D121360: [AMDGPU] Enable divergence predicates for negative inline constant subtraction.
Mar 10 2022, 4:03 AM · Restricted Project, Restricted Project
alex-t requested review of D121360: [AMDGPU] Enable divergence predicates for negative inline constant subtraction.
Mar 10 2022, 2:06 AM · Restricted Project, Restricted Project

Feb 14 2022

alex-t committed rGc23198ec1348: [AMDGPU] Divergence-driven abs instruction selection (authored by alex-t).
[AMDGPU] Divergence-driven abs instruction selection
Feb 14 2022, 10:33 AM
alex-t closed D119581: [AMDGPU] Divergence-driven abs instruction selection.
Feb 14 2022, 10:33 AM · Restricted Project
alex-t accepted D119706: [AMDGPU] Divergence-driven instruction selection for bfm patterns.
Feb 14 2022, 10:02 AM · Restricted Project
alex-t added a comment to D119706: [AMDGPU] Divergence-driven instruction selection for bfm patterns.

LGTM

Feb 14 2022, 10:01 AM · Restricted Project
alex-t added a comment to D119702: [AMDGPU] Divergence-driven instruction selection for bitreverse.

Looks good but I'd like to see the selection-only LIT test:
uniform bitreverse i32,
divergent bitreverse i32,
uniform bitreverse i64,
divergent bitreverse i64
with -stop-after=amdgpu-isel
The purpose of the selection-only tests is to control the divergence-driven selection not broken.
Otherwise, it could be broken but full-stack tests are still matching because of the moveToVALU hackery.

Feb 14 2022, 9:59 AM · Restricted Project
alex-t updated the diff for D119581: [AMDGPU] Divergence-driven abs instruction selection.

Test corrected. Added complexity for the AddNoCarry case.

Feb 14 2022, 6:56 AM · Restricted Project

Feb 11 2022

alex-t requested review of D119581: [AMDGPU] Divergence-driven abs instruction selection.
Feb 11 2022, 1:06 PM · Restricted Project

Feb 10 2022

alex-t committed rGd88a146f2bc1: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction… (authored by alex-t).
[AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction…
Feb 10 2022, 8:33 AM
alex-t closed D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection.
Feb 10 2022, 8:33 AM · Restricted Project
alex-t updated the diff for D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection.

One more test attributes corrected

Feb 10 2022, 8:30 AM · Restricted Project
alex-t updated the diff for D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection.

Test file attributes corrected

Feb 10 2022, 7:44 AM · Restricted Project

Feb 9 2022

alex-t added inline comments to D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection.
Feb 9 2022, 10:44 AM · Restricted Project
alex-t updated the diff for D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection.

Odd comments and copy-paste typo corrected

Feb 9 2022, 10:42 AM · Restricted Project

Feb 8 2022

alex-t requested review of D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection.
Feb 8 2022, 4:35 PM · Restricted Project

Jan 26 2022

alex-t committed rG5157f984ae2c: [AMDGPU] Enable divergence-driven XNOR selection (authored by alex-t).
[AMDGPU] Enable divergence-driven XNOR selection
Jan 26 2022, 4:30 AM
alex-t closed D116270: [AMDGPU] Enable divergence-driven XNOR selection.
Jan 26 2022, 4:30 AM · Restricted Project

Jan 25 2022

alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

FIXME v_perm_b32 added

Jan 25 2022, 3:19 PM · Restricted Project
alex-t added inline comments to D116270: [AMDGPU] Enable divergence-driven XNOR selection.
Jan 25 2022, 2:33 PM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

removed accidentally added files

Jan 25 2022, 2:33 PM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Added detailed comment explainingthe new target hook.
Memory access pattern check changed to match exactly the address operand.
Minor fixes.

Jan 25 2022, 2:24 PM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

LGTM provided comments are fixed.

Jan 25 2022, 3:01 AM · Restricted Project

Jan 24 2022

alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Added comment to common target hook declaration. Condition changed.

Jan 24 2022, 1:47 PM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Removed constant folding heuristic, prooved useless.

Jan 24 2022, 9:36 AM · Restricted Project

Jan 21 2022

alex-t added inline comments to D116270: [AMDGPU] Enable divergence-driven XNOR selection.
Jan 21 2022, 9:31 AM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Bug fixed: Memory access DAG pattern check must ensure that "base + offset" pattern has MemSDNode users

Jan 21 2022, 9:09 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Initial DAG


DAG after the transformation and constant folding

This can be selected to v_perm_b32

Jan 21 2022, 3:40 AM · Restricted Project

Jan 20 2022

alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Initial DAG


DAG after the transformation and constant folding

This can be selected to v_perm_b32

Jan 20 2022, 9:30 AM · Restricted Project
alex-t added inline comments to D116270: [AMDGPU] Enable divergence-driven XNOR selection.
Jan 20 2022, 9:04 AM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

condition was made more readable

Jan 20 2022, 7:09 AM · Restricted Project

Jan 17 2022

alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

DAG combiner hook added to control divergence-driven peephole optimizatoins.

Jan 17 2022, 12:29 PM · Restricted Project

Jan 13 2022

alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

In general, I don't like the idea of making the DAGCombiner::reassociateOpsCommutative take into account the divergence.

Jan 13 2022, 6:27 AM · Restricted Project

Jan 11 2022

alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

I think it is worth trying to change this generic combine to give up if x is uniform and y is divergent.

Jan 11 2022, 12:11 PM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Once again, in my case BOTH nodes (not,xor) are divergent!

 %s.load = load i32, i32 addrspace(4)* %s.kernarg.offset.cast, align 4, !invariant.load !0
DIVERGENT:       %v = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
DIVERGENT:       %xor = xor i32 %v, %s.load
DIVERGENT:       %d = xor i32 %xor, -1
DIVERGENT:       store i32 %d, i32 addrspace(1)* %out.load, align 4

I know. I am suggesting that a DAG combine can rewrite this code to the equivalent of:

                 %s.load = load i32, i32 addrspace(4)* %s.kernarg.offset.cast, align 4, !invariant.load !0
DIVERGENT:       %v = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
                 %not = xor i32 %s.load, -1
DIVERGENT:       %d = xor i32 %v, %not
DIVERGENT:       store i32 %d, i32 addrspace(1)* %out.load, align 4

Now %not is uniform, so it is trivial to select it to s_not.

Jan 11 2022, 8:36 AM · Restricted Project

Jan 10 2022

alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Once again, in my case BOTH nodes (not,xor) are divergent!

 %s.load = load i32, i32 addrspace(4)* %s.kernarg.offset.cast, align 4, !invariant.load !0
DIVERGENT:       %v = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
DIVERGENT:       %xor = xor i32 %v, %s.load
DIVERGENT:       %d = xor i32 %xor, -1
DIVERGENT:       store i32 %d, i32 addrspace(1)* %out.load, align 4

I know. I am suggesting that a DAG combine can rewrite this code to the equivalent of:

                 %s.load = load i32, i32 addrspace(4)* %s.kernarg.offset.cast, align 4, !invariant.load !0
DIVERGENT:       %v = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
                 %not = xor i32 %s.load, -1
DIVERGENT:       %d = xor i32 %v, %not
DIVERGENT:       store i32 %d, i32 addrspace(1)* %out.load, align 4

Now %not is uniform, so it is trivial to select it to s_not.

Jan 10 2022, 8:09 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Now:

We select the divergent NOT to V_NOT_B32_e32 and divergent XOR to V_XOR_B32_e64. The selection is correct but we missed the opportunity to exploit the fact that even divergent NOT may be selected to S_NOT_B32 w/o the correctness lost.

No, you cannot correctly select divergent NOT to S_NOT_B32. That is not what was happening before your patch (see https://reviews.llvm.org/D116270?vs=on&id=396159#change-5HrmrjqhUdXJ). What was happening was that an input like ~(uniform ^ divergent) was being "reassociated" to ~uniform ^ divergent so it could be correctly selected to S_NOT + V_XOR. I assume this was done with a very clever selection pattern, but I am suggesting that instead of that you could implement it as a DAG combine (to do the reassociation), so there is no need for clever selection patterns.

Jan 10 2022, 7:56 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

This looks like a regression in xnor.ll :

	s_not_b32 s0, s0                        	v_not_b32_e32 v0, v0
	v_xor_b32_e32 v0, s0, v0                        v_xor_b32_e32 v0, s4, v0

but it is not really. All the nodes in the example are divergent and the divergent ( xor, x -1) is selected to V_NOT_B32 as of https://reviews.llvm.org/D115884 has been committed.
S_NOT_B32 appears at the left because of the custom optimization that converts S_XNOR_B32 back to NOT (XOR) for the targets which have no V_XNOR. This optimization relies on the fact that if the NOT operand is SGPR and V_XOR_B32_e32 can accept SGPR as a first source operand.
I am not sure if it is always safe. The VALU instructions execution is controlled by the EXEC mask but SALU is not.

To repeat what I have already said elsewhere: this is not a correctness issue. This is just an optimization, where you can choose to calculate either ~s0 ^ v0 or s0 ^ ~v0 (or ~(s0 ^ v0)) and get exactly the same result. The optimization is to prefer the first form, because the intermediate result ~s0 is uniform, so you can keep it in an sgpr and not waste vgprs and valu instructions.

Jan 10 2022, 7:37 AM · Restricted Project

Jan 7 2022

alex-t added inline comments to D116270: [AMDGPU] Enable divergence-driven XNOR selection.
Jan 7 2022, 1:12 PM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

Added postprocessing of the selected machine IR. This makes it on par with the existing selection mechanism.

Jan 7 2022, 7:56 AM · Restricted Project
alex-t committed rG5d46263a5ac5: [AMDGPU] Enable divergence-driven 'ctpop' selection (authored by alex-t).
[AMDGPU] Enable divergence-driven 'ctpop' selection
Jan 7 2022, 5:05 AM
alex-t closed D116284: [AMDGPU] Enable divergence-driven 'ctpop' selection.
Jan 7 2022, 5:05 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

This looks like a regression in xnor.ll :

	s_not_b32 s0, s0                        	v_not_b32_e32 v0, v0
	v_xor_b32_e32 v0, s0, v0                        v_xor_b32_e32 v0, s4, v0

but it is not really. All the nodes in the example are divergent and the divergent ( xor, x -1) is selected to V_NOT_B32 as of https://reviews.llvm.org/D115884 has been committed.
S_NOT_B32 appears at the left because of the custom optimization that converts S_XNOR_B32 back to NOT (XOR) for the targets which have no V_XNOR. This optimization relies on the fact that if the NOT operand is SGPR and V_XOR_B32_e32 can accept SGPR as a first source operand.
I am not sure if it is always safe. The VALU instructions execution is controlled by the EXEC mask but SALU is not.

This is indeed a regression. It is always safe to keep s_not_b32 on SALU. Also note this effectively makes SIInstrInfo::lowerScalarXnor() useless. This is why XNOR was left behind by the D111907.

SIInstrInfo::lowerScalarXnor() is exactly the part of the "manual" SALU to VALU lowering that I am trying to get rid of.
The divergent "not" must be selected to the "V_NOT_B32_e32/64" otherwise we still have illegal VGPR to SGPR copies.
This happens because the divergent "not" node has divergent operands and their result will be likely in VGPR.
Also, we should select everything correctly first and can apply some peephole optimizations after.
In other words: we should not "cheat ourselves" during the selection. The selection should be done fairly corresponding to the node divergence bit.
Then we can apply the optimization in case it is safe.
Note that this is not the only case when we would like to further optimize the code after selection.
I'm planning to further add a separate pass for that.

We cannot solve the problem in the custom selection procedure because NOT node operand has not yet been selected and we do not know if it is SGPR or VGPR.
The only way, for now, is to post-process not(xor)/xor(not) in SIFixSGPRCopies. This may be considered a temporary hack until we have no proper pass for that.

SIInstrInfo::lowerScalarXnor() is dead after your patch and thus the patch has to remove it.

Then this is a clear regression, so if this requires a separate peephole later we need that peephole first and make sure the test does not regress.

Jan 7 2022, 3:21 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

SIInstrInfo::lowerScalarXnor() is dead after your patch

I don't understand why it is dead. In general moveToVALU moves instructions to VALU if any of their inputs are VGPRs, which can happen even if the result is uniform -- e.g. if some of the inputs are derived from a floating point calculation which had to use VALU instructions.

Jan 7 2022, 3:10 AM · Restricted Project

Jan 6 2022

alex-t added inline comments to D116284: [AMDGPU] Enable divergence-driven 'ctpop' selection.
Jan 6 2022, 5:15 AM · Restricted Project
alex-t updated the diff for D116284: [AMDGPU] Enable divergence-driven 'ctpop' selection.

odd COPY_TO_REGCLASS removed. Test updated.

Jan 6 2022, 5:11 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

This looks like a regression in xnor.ll :

	s_not_b32 s0, s0                        	v_not_b32_e32 v0, v0
	v_xor_b32_e32 v0, s0, v0                        v_xor_b32_e32 v0, s4, v0

but it is not really. All the nodes in the example are divergent and the divergent ( xor, x -1) is selected to V_NOT_B32 as of https://reviews.llvm.org/D115884 has been committed.
S_NOT_B32 appears at the left because of the custom optimization that converts S_XNOR_B32 back to NOT (XOR) for the targets which have no V_XNOR. This optimization relies on the fact that if the NOT operand is SGPR and V_XOR_B32_e32 can accept SGPR as a first source operand.
I am not sure if it is always safe. The VALU instructions execution is controlled by the EXEC mask but SALU is not.

This is indeed a regression. It is always safe to keep s_not_b32 on SALU. Also note this effectively makes SIInstrInfo::lowerScalarXnor() useless. This is why XNOR was left behind by the D111907.

Jan 6 2022, 3:39 AM · Restricted Project

Dec 26 2021

alex-t updated the diff for D116284: [AMDGPU] Enable divergence-driven 'ctpop' selection.

test file attributes corrected

Dec 26 2021, 4:32 AM · Restricted Project
alex-t requested review of D116284: [AMDGPU] Enable divergence-driven 'ctpop' selection.
Dec 26 2021, 4:30 AM · Restricted Project

Dec 24 2021

alex-t committed rG8020458c5dc2: [AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the divergent 'trunc' to i1… (authored by alex-t).
[AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the divergent 'trunc' to i1…
Dec 24 2021, 7:22 AM
alex-t closed D116241: [AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the divergent 'trunc' to i1 pattern.
Dec 24 2021, 7:22 AM · Restricted Project
alex-t added a comment to D116270: [AMDGPU] Enable divergence-driven XNOR selection.

This looks like a regression in xnor.ll :

Dec 24 2021, 7:19 AM · Restricted Project
alex-t updated the diff for D116270: [AMDGPU] Enable divergence-driven XNOR selection.

LIT test file attributes corrected

Dec 24 2021, 6:57 AM · Restricted Project
alex-t requested review of D116270: [AMDGPU] Enable divergence-driven XNOR selection.
Dec 24 2021, 6:55 AM · Restricted Project

Dec 23 2021

alex-t updated the diff for D116241: [AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the divergent 'trunc' to i1 pattern.

test attributes corrected

Dec 23 2021, 2:08 PM · Restricted Project
alex-t requested review of D116241: [AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the divergent 'trunc' to i1 pattern.
Dec 23 2021, 2:05 PM · Restricted Project

Dec 22 2021

alex-t committed rGe4103c91f857: [AMDGPU] Select build_vector DAG nodes according to the divergence (authored by alex-t).
[AMDGPU] Select build_vector DAG nodes according to the divergence
Dec 22 2021, 3:27 PM
alex-t closed D116187: [AMDGPU] Select build_vector DAG nodes according to the divergence.
Dec 22 2021, 3:27 PM · Restricted Project
alex-t updated the summary of D116187: [AMDGPU] Select build_vector DAG nodes according to the divergence.
Dec 22 2021, 1:46 PM · Restricted Project
alex-t requested review of D116187: [AMDGPU] Select build_vector DAG nodes according to the divergence.
Dec 22 2021, 1:45 PM · Restricted Project

Dec 20 2021

alex-t committed rG19727e31fb2c: [AMDGPU] Enable divergence predicates for ctlz/cttz (authored by alex-t).
[AMDGPU] Enable divergence predicates for ctlz/cttz
Dec 20 2021, 9:52 AM
alex-t closed D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz.
Dec 20 2021, 9:51 AM · Restricted Project
alex-t updated the diff for D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz.

test corrected

Dec 20 2021, 8:28 AM · Restricted Project
alex-t retitled D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz from [AMDGPU] Enable devergence predicates for ctlz/cttz to [AMDGPU] Enable divergence predicates for ctlz/cttz.
Dec 20 2021, 8:15 AM · Restricted Project
alex-t updated the summary of D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz.
Dec 20 2021, 8:14 AM · Restricted Project
alex-t updated the summary of D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz.
Dec 20 2021, 8:14 AM · Restricted Project
alex-t updated the summary of D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz.
Dec 20 2021, 8:12 AM · Restricted Project
alex-t requested review of D116044: [AMDGPU] Enable divergence predicates for ctlz/cttz.
Dec 20 2021, 8:10 AM · Restricted Project
alex-t committed rG98d09705e15c: [AMDGPU] Re-enabling divergence predicates for min/max (authored by alex-t).
[AMDGPU] Re-enabling divergence predicates for min/max
Dec 20 2021, 5:09 AM
alex-t closed D115954: [AMDGPU] Re-enabling divergence predicates for min/max.
Dec 20 2021, 5:08 AM · Restricted Project
alex-t committed rG1448aa9dbdd9: [AMDGPU] Expand not pattern according to the XOR node divergence (authored by alex-t).
[AMDGPU] Expand not pattern according to the XOR node divergence
Dec 20 2021, 3:40 AM
alex-t closed D115884: [AMDGPU] Expand not pattern according to the XOR node divergence.
Dec 20 2021, 3:40 AM · Restricted Project

Dec 17 2021

alex-t updated the summary of D115954: [AMDGPU] Re-enabling divergence predicates for min/max.
Dec 17 2021, 10:41 AM · Restricted Project