- User Since
- Jul 26 2016, 7:17 AM (217 w, 1 d)
Thu, Sep 17
Wed, Sep 16
tests moved to existing rotl/rotr tests
Tue, Sep 15
Tests added. ROTR case added.
Mon, Sep 14
Tue, Sep 8
Mon, Sep 7
Enhanced PSDB passed
The idea is:
Fri, Sep 4
Also I still think that disabling a whole "endif" block is an overkill.
So, since we now have sensible diff to discuss...
Why I decided to disallow split in any block that gets control with exec == 0 and has no restoring code in prologue?
I just did it by example of the code that already does same for the blocks with interference - a bit later below:
Now the correct diff uploaded
Oops. In fact the diff above is not that I was intended to upload. The SIInstrInfo::IsValidForLISplit is a complete nonsense. Probably deleted a part of the function by accident...
I'll get back and upload the working one.
Thu, Sep 3
Wed, Sep 2
diff rebased to latest trunk
Tue, Sep 1
No redundant branches anymore
Fri, Aug 28
The only difference is that now these redundant branch is inserted by MachineBasicBlock::updateTerminator() as Matt suggested.
changed as requested by reviewer
Added MachineDominatorTree and MachineLoopInfo update after redundant block removal.
Thu, Aug 27
Changes as requested by reviewer.
Wed, Aug 26
Jun 26 2020
This small piece was missed from the change.
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 5f1afdd7f10..7180e0a8d52 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -634,6 +634,9 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, }
and as well as the failures it caused spurious debug output like:Test case 'dEQP-VK.subgroups.arithmetic.framebuffer.subgroupmax_int_tess_eval'.. S_CMP_LG_U32 killed $sgpr2_sgpr3, 0, implicit-def $scc S_CMP_LG_U32 killed $sgpr0_sgpr1, 0, implicit-def $scc Fail (Failed!)
Jun 25 2020
Jun 24 2020
Jun 23 2020
udivrem.ll checks updated
Formatting fixed. test extract_vector_dynelt.ll changed.
Jun 20 2020
Code changed according to the reviewer request
Jun 19 2020
May 28 2020
May 27 2020
Ping again. Could you please take a look?
May 26 2020
May 25 2020
Explicit call to isSafeToFoldImmIntoCopy added. Corresponding COPY converted to S_MOV right away.
2 test cases added to check for copy to subreg and inappropriate move opcodes.
May 23 2020
May 22 2020
Explicit check move source operand to be immediate.
May 21 2020
May 20 2020
Explicit register class comparison changed to constrain reg class. Test added.
May 18 2020
May 4 2020
Apr 30 2020
changed code passed through the clang-format
Apr 29 2020
Selection specific test (carryout-selection.ll) added
Apr 24 2020
a few more corrections
Apr 23 2020
Both operands can be immediate - handled. Some other changes to follow up the discussion.
Apr 16 2020
Apr 15 2020
Src1 immediate case handled. Formatting improved.
Apr 14 2020
Mar 20 2020
Mar 19 2020
Mar 18 2020
Mar 17 2020
Mar 16 2020
Mar 10 2020
Mar 4 2020
Mar 2 2020
Feb 5 2020
Feb 4 2020
It should work if we can guarantee that the values produced by the CF intrinsics are only used by the another CF intrinsics.
I mean something like AND/OR the uniform mask with some divergent value and then feeding result to another CF...
but normally this should not happen.
Once again: I like getting rid of requiresUniformRegister but insist on the extended testing.
Also, the trouble with LCSSA use of the uniform mask out of the divergent loop need to be solved anyway.
I agree that current expensive walk on IR should be removed.
I initially consider it as a temporary solution that allows to switch to the new concept
of assignment correct register classes keeping in mind to eventually find another way to workaround CF results exceptions.
Jan 31 2020
llvm.amdgcn.update.dpp test updated
i64 tests added
I haven't seen any tests XFAIL'd by this c12f046eb96f8462b3fd3889344ba344de5ace1f commit.
What did you mean? Could you explain please?
Jan 30 2020
Diff corrected. GFX10 test added.
As far as I remember the origin of this hack: