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alex-t (Alexander)
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Jul 26 2016, 7:17 AM (217 w, 1 d)

Recent Activity

Yesterday

alex-t added a comment to D87882: [AMDGPU] Fix merging m0 inits.

Doesn't loop block self dominate?

Tue, Sep 22, 12:31 PM · Restricted Project

Thu, Sep 17

alex-t committed rG0efbb70b719e: [AMDGPU] should expand ROTL i16 to shifts. (authored by alex-t).
[AMDGPU] should expand ROTL i16 to shifts.
Thu, Sep 17, 7:35 AM
alex-t closed D87618: [AMDGPU] should expand ROTL i16 to shifts..
Thu, Sep 17, 7:34 AM · Restricted Project

Wed, Sep 16

alex-t updated the diff for D87618: [AMDGPU] should expand ROTL i16 to shifts..

tests moved to existing rotl/rotr tests

Wed, Sep 16, 2:04 AM · Restricted Project

Tue, Sep 15

alex-t updated the diff for D87618: [AMDGPU] should expand ROTL i16 to shifts..

Tests added. ROTR case added.

Tue, Sep 15, 10:32 AM · Restricted Project

Mon, Sep 14

alex-t requested review of D87618: [AMDGPU] should expand ROTL i16 to shifts..
Mon, Sep 14, 9:55 AM · Restricted Project

Tue, Sep 8

alex-t added a comment to D87107: [AMDGPU] Target hook to apply target specific split constraint.

The idea is:

For the block that is queried

  1. Look for it's predecessors that can pass control through the S_EXECZ/EXECNZ
  2. If found one, look for exec restoring code starting the beginning of the block being queried.
  3. Since exec restoring code always belong to the block prologue, search the prologue and if not found return false.

Considering your comment that exec == 0 does not matter, we'd rather search upwards before the immediate dominator block in encountered to check what we met first - exec modify or exec restore. The problem here is that XOR can be both.

Thanks. More or less you want to disable split in an empty block preceded by c_branch_exec[n]z. I can understand why this would be a problem. In reality such block can be either empty or contain another branch, because it does not make any sense to pass a control to a block with vector instructions and have no active lanes.

But this leaves couple problems:

  1. It does not disallow a split in a block prologue before exec is restored. This creates exactly the same problem.
  2. It does not disallow a split even in an empty block where EXEC is not zero, but just wrong. The problem is not zero EXEC, the problem is wrong EXEC, zero is just once case of this.

JBTW, even with all of this it is still OK to split an LI of SGPR. I'd say at the very least callback needs to take an LI in question as well.

Tue, Sep 8, 11:31 AM · Restricted Project

Mon, Sep 7

alex-t committed rG2480a31e5d69: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block (authored by alex-t).
[AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block
Mon, Sep 7, 9:38 AM
alex-t closed D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.
Mon, Sep 7, 9:37 AM · Restricted Project
alex-t added a comment to D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

Enhanced PSDB passed

Mon, Sep 7, 8:57 AM · Restricted Project
alex-t added a comment to D87107: [AMDGPU] Target hook to apply target specific split constraint.

The idea is:

Mon, Sep 7, 7:14 AM · Restricted Project

Fri, Sep 4

alex-t added a comment to D87107: [AMDGPU] Target hook to apply target specific split constraint.

Also I still think that disabling a whole "endif" block is an overkill.

It only is disabled if S_OR_B64 exec, ... is in the middle of the block that should never happen.

while (isBasicBlockPrologue(*J)) {
  if (IsExecRestore(&*J))
    return true;

assumes that if exec is restored in the block prologue it is valid

So practically it never happens and split is effectively only disabled in an empty block? I said it already: it does not matter that exec is zero, what matters is that it does not match. It does not matter that a block is empty as well, it is enough to split before s_or to hit the bug.

Fri, Sep 4, 1:28 PM · Restricted Project
alex-t added a comment to D87107: [AMDGPU] Target hook to apply target specific split constraint.

Also I still think that disabling a whole "endif" block is an overkill.

Fri, Sep 4, 11:30 AM · Restricted Project
alex-t added a comment to D87107: [AMDGPU] Target hook to apply target specific split constraint.

So, since we now have sensible diff to discuss...
Why I decided to disallow split in any block that gets control with exec == 0 and has no restoring code in prologue?
I just did it by example of the code that already does same for the blocks with interference - a bit later below:

Fri, Sep 4, 10:27 AM · Restricted Project
alex-t updated the diff for D87107: [AMDGPU] Target hook to apply target specific split constraint.

Now the correct diff uploaded

Fri, Sep 4, 10:22 AM · Restricted Project
alex-t added a comment to D87107: [AMDGPU] Target hook to apply target specific split constraint.

Oops. In fact the diff above is not that I was intended to upload. The SIInstrInfo::IsValidForLISplit is a complete nonsense. Probably deleted a part of the function by accident...
I'll get back and upload the working one.

Fri, Sep 4, 9:15 AM · Restricted Project

Thu, Sep 3

alex-t requested review of D87107: [AMDGPU] Target hook to apply target specific split constraint.
Thu, Sep 3, 12:05 PM · Restricted Project

Wed, Sep 2

alex-t updated the diff for D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

diff rebased to latest trunk

Wed, Sep 2, 2:34 AM · Restricted Project

Tue, Sep 1

alex-t updated the diff for D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

No redundant branches anymore

Tue, Sep 1, 7:15 AM · Restricted Project

Fri, Aug 28

alex-t added a comment to D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

The only difference is that now these redundant branch is inserted by MachineBasicBlock::updateTerminator() as Matt suggested.

Fri, Aug 28, 3:04 PM · Restricted Project
alex-t added inline comments to D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.
Fri, Aug 28, 3:02 PM · Restricted Project
alex-t updated the diff for D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

changed as requested by reviewer

Fri, Aug 28, 1:56 PM · Restricted Project
alex-t added inline comments to D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.
Fri, Aug 28, 9:19 AM · Restricted Project
alex-t updated the diff for D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

Added MachineDominatorTree and MachineLoopInfo update after redundant block removal.

Fri, Aug 28, 9:19 AM · Restricted Project

Thu, Aug 27

alex-t added a comment to D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

Should also add a few cases with other empty block situations, including with debug info.

Also should add an example where the original problem occurred

Thu, Aug 27, 12:43 PM · Restricted Project
alex-t added inline comments to D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.
Thu, Aug 27, 12:39 PM · Restricted Project
alex-t updated the diff for D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.

Changes as requested by reviewer.

Thu, Aug 27, 12:37 PM · Restricted Project

Wed, Aug 26

alex-t requested review of D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block.
Wed, Aug 26, 8:58 AM · Restricted Project

Jun 26 2020

alex-t added a comment to D82194: [AMDGPU] Enable compare operations to be selected by divergence.

This small piece was missed from the change.

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 5f1afdd7f10..7180e0a8d52 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -634,6 +634,9 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   }
Jun 26 2020, 8:44 AM · Restricted Project
alex-t added a comment to D82194: [AMDGPU] Enable compare operations to be selected by divergence.

This change broke thousands of piglit gpu profile tests with Mesa radeonsi on Navi 14.

Jun 26 2020, 1:36 AM · Restricted Project
alex-t added a comment to D82194: [AMDGPU] Enable compare operations to be selected by divergence.

and as well as the failures it caused spurious debug output like:

Test case 'dEQP-VK.subgroups.arithmetic.framebuffer.subgroupmax_int_tess_eval'..
S_CMP_LG_U32 killed $sgpr2_sgpr3, 0, implicit-def $scc
S_CMP_LG_U32 killed $sgpr0_sgpr1, 0, implicit-def $scc
  Fail (Failed!)
Jun 26 2020, 1:04 AM · Restricted Project

Jun 25 2020

alex-t added a comment to D82194: [AMDGPU] Enable compare operations to be selected by divergence.

This change broke thousands of piglit gpu profile tests with Mesa radeonsi on Navi 14.

Jun 25 2020, 8:34 AM · Restricted Project

Jun 24 2020

alex-t committed rG521ac0b5cea0: [AMDGPU] Enable compare operations to be selected by divergence (authored by alex-t).
[AMDGPU] Enable compare operations to be selected by divergence
Jun 24 2020, 2:08 AM
alex-t closed D82194: [AMDGPU] Enable compare operations to be selected by divergence.
Jun 24 2020, 2:08 AM · Restricted Project
alex-t added inline comments to D82194: [AMDGPU] Enable compare operations to be selected by divergence.
Jun 24 2020, 1:02 AM · Restricted Project

Jun 23 2020

alex-t updated the diff for D82194: [AMDGPU] Enable compare operations to be selected by divergence.

udivrem.ll checks updated

Jun 23 2020, 5:49 AM · Restricted Project
alex-t added inline comments to D82248: AMDGPU: Don't ignore carry out user when expanding add_co_pseudo.
Jun 23 2020, 3:40 AM · Restricted Project
alex-t updated the diff for D82194: [AMDGPU] Enable compare operations to be selected by divergence.

Formatting fixed. test extract_vector_dynelt.ll changed.

Jun 23 2020, 2:04 AM · Restricted Project

Jun 20 2020

alex-t updated the diff for D82194: [AMDGPU] Enable compare operations to be selected by divergence.

Code changed according to the reviewer request

Jun 20 2020, 7:54 AM · Restricted Project

Jun 19 2020

alex-t created D82194: [AMDGPU] Enable compare operations to be selected by divergence.
Jun 19 2020, 8:05 AM · Restricted Project

May 28 2020

alex-t committed rGb726d071b4aa: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move… (authored by alex-t).
[AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move…
May 28 2020, 9:53 AM
alex-t closed D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.
May 28 2020, 9:51 AM · Restricted Project

May 27 2020

alex-t committed rGeb1092ada32d: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in… (authored by alex-t).
[AMDGPU] Fix for the lost CarryOut/CarryIn register operands in…
May 27 2020, 1:04 PM
alex-t closed D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO..
May 27 2020, 1:04 PM · Restricted Project
alex-t added inline comments to D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.
May 27 2020, 3:45 AM · Restricted Project
alex-t updated the diff for D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

test corrected

May 27 2020, 3:44 AM · Restricted Project
alex-t added a comment to D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO..

Ping again. Could you please take a look?

May 27 2020, 3:12 AM · Restricted Project

May 26 2020

alex-t reopened D70085: [AMDGPU] NFC target dependent requiresUniformRegister refactored out.
May 26 2020, 10:49 AM · Restricted Project
alex-t added inline comments to D70085: [AMDGPU] NFC target dependent requiresUniformRegister refactored out.
May 26 2020, 10:49 AM · Restricted Project
alex-t committed rGfb38b98338cc: [AMDGPU] NFC target dependent requiresUniformRegister refactored out (authored by alex-t).
[AMDGPU] NFC target dependent requiresUniformRegister refactored out
May 26 2020, 10:18 AM
alex-t closed D70085: [AMDGPU] NFC target dependent requiresUniformRegister refactored out.
May 26 2020, 10:18 AM · Restricted Project

May 25 2020

alex-t updated the diff for D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

Explicit call to isSafeToFoldImmIntoCopy added. Corresponding COPY converted to S_MOV right away.
2 test cases added to check for copy to subreg and inappropriate move opcodes.

May 25 2020, 8:01 AM · Restricted Project

May 23 2020

alex-t added a comment to D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

You do not even need a loop to get PHI. A PHI might occur after an simple IF.
Nevertheless, patch retains an illegal copy which it is supposed to remove. The fact that it works in this testcase does not mean it will always work.
I would suggest to fold the immediate copy instead. I.e. you can replace COPY with an S_MOV_B32 (given it fits 32 bit of course).

The following code does it in one of the next iterations

// If we are just copying an immediate, we can replace the copy with
// s_mov_b32.
if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) {
  MI.getOperand(1).ChangeToImmediate(Imm);
  MI.addImplicitDefUseOperands(MF);
  MI.setDesc(TII->get(SMovOp));
  break;
}

What if not isSafeToFoldImmIntoCopy?

May 23 2020, 4:12 AM · Restricted Project

May 22 2020

alex-t added a comment to D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

You do not even need a loop to get PHI. A PHI might occur after an simple IF.
Nevertheless, patch retains an illegal copy which it is supposed to remove. The fact that it works in this testcase does not mean it will always work.
I would suggest to fold the immediate copy instead. I.e. you can replace COPY with an S_MOV_B32 (given it fits 32 bit of course).

May 22 2020, 1:57 PM · Restricted Project
alex-t updated the diff for D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

Explicit check move source operand to be immediate.

May 22 2020, 12:52 PM · Restricted Project
alex-t added a comment to D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

Every mov isMoveImmediate(), it is just a property on MCDesc.
I also assume it relies on the folding later. If that folding will not happen for whatever reason it will be a broken IR. Right?

May 22 2020, 12:52 PM · Restricted Project
alex-t added a comment to D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO..

ping

May 22 2020, 12:20 PM · Restricted Project
alex-t updated the diff for D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.

test added

May 22 2020, 5:51 AM · Restricted Project
alex-t created D80434: [AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate.
May 22 2020, 5:51 AM · Restricted Project

May 21 2020

alex-t updated the diff for D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO..

test reworked.

May 21 2020, 12:26 PM · Restricted Project

May 20 2020

alex-t updated the diff for D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO..

Explicit register class comparison changed to constrain reg class. Test added.

May 20 2020, 5:41 PM · Restricted Project

May 18 2020

alex-t created D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO..
May 18 2020, 2:06 PM · Restricted Project
alex-t accepted D79901: AMDGPU: Fix DAG divergence for implicit function arguments.

LGTM

May 18 2020, 11:54 AM · Restricted Project

May 4 2020

alex-t committed rG5b898bddff51: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction… (authored by alex-t).
[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction…
May 4 2020, 6:55 AM
alex-t closed D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..
May 4 2020, 6:54 AM · Restricted Project

Apr 30 2020

alex-t updated the diff for D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

changed code passed through the clang-format

Apr 30 2020, 5:38 AM · Restricted Project
alex-t added a comment to D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

Can you add tests with both immediates? You will probably need to -start-before=amdgpu-isel or -O0 if it will be constant folded.
Also fix formatting issues.

Apr 30 2020, 1:48 AM · Restricted Project

Apr 29 2020

alex-t updated the diff for D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

Selection specific test (carryout-selection.ll) added

Apr 29 2020, 12:54 PM · Restricted Project

Apr 24 2020

alex-t added inline comments to D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..
Apr 24 2020, 5:23 AM · Restricted Project
alex-t updated the diff for D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

a few more corrections

Apr 24 2020, 5:22 AM · Restricted Project

Apr 23 2020

alex-t added inline comments to D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..
Apr 23 2020, 11:21 AM · Restricted Project
alex-t updated the diff for D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

Both operands can be immediate - handled. Some other changes to follow up the discussion.

Apr 23 2020, 11:21 AM · Restricted Project

Apr 16 2020

alex-t added a comment to D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

You need to add tests for selection and moveToVALU, including immediates and wave32.

Apr 16 2020, 10:01 AM · Restricted Project

Apr 15 2020

alex-t updated the diff for D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..

Src1 immediate case handled. Formatting improved.

Apr 15 2020, 4:20 AM · Restricted Project
alex-t added inline comments to D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..
Apr 15 2020, 4:20 AM · Restricted Project

Apr 14 2020

alex-t created D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection..
Apr 14 2020, 2:37 AM · Restricted Project

Mar 20 2020

alex-t committed rG6e34e71869ab: [AMDGPU] Enable divergence driven ISel for ADD/SUB i64 (authored by alex-t).
[AMDGPU] Enable divergence driven ISel for ADD/SUB i64
Mar 20 2020, 7:33 AM
alex-t closed D76371: [AMDGPU] Enable divergence driven ISel for ADD/SUB i64.
Mar 20 2020, 7:33 AM · Restricted Project

Mar 19 2020

alex-t updated the diff for D76371: [AMDGPU] Enable divergence driven ISel for ADD/SUB i64.

static const

Mar 19 2020, 11:59 AM · Restricted Project

Mar 18 2020

alex-t created D76371: [AMDGPU] Enable divergence driven ISel for ADD/SUB i64.
Mar 18 2020, 10:20 AM · Restricted Project

Mar 17 2020

alex-t committed rG48a9cf90439a: [AMDGPU] Enable SEXT divergence driven selection. (authored by alex-t).
[AMDGPU] Enable SEXT divergence driven selection.
Mar 17 2020, 8:00 AM
alex-t closed D76230: [AMDGPU] Enable SEXT divergence driven selection..
Mar 17 2020, 7:58 AM · Restricted Project

Mar 16 2020

alex-t added a comment to D76230: [AMDGPU] Enable SEXT divergence driven selection..

Test name is misleading, this should just go in the realgar sext test. Also I would expect this to already be well covered

Mar 16 2020, 8:08 AM · Restricted Project
alex-t added a reviewer for D76230: [AMDGPU] Enable SEXT divergence driven selection.: rampitec.
Mar 16 2020, 6:26 AM · Restricted Project
alex-t created D76230: [AMDGPU] Enable SEXT divergence driven selection..
Mar 16 2020, 6:26 AM · Restricted Project

Mar 10 2020

alex-t committed rG39e1a90784b3: [AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to… (authored by alex-t).
[AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to…
Mar 10 2020, 4:34 AM
alex-t closed D75472: [AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to separate basic block.
Mar 10 2020, 4:34 AM · Restricted Project

Mar 4 2020

alex-t added a comment to D75472: [AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to separate basic block.

Ping!

Mar 4 2020, 3:26 AM · Restricted Project

Mar 2 2020

alex-t updated the diff for D75472: [AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to separate basic block.

Test updated

Mar 2 2020, 11:36 AM · Restricted Project
alex-t created D75472: [AMDGPU] SI_INDIRECT_DST_V* pseudos expansion should place EXEC restore to separate basic block.
Mar 2 2020, 10:40 AM · Restricted Project

Feb 5 2020

alex-t accepted D73815: AMDGPU: Fix divergence analysis of control flow intrinsics.
Feb 5 2020, 8:12 AM · Restricted Project

Feb 4 2020

alex-t added a comment to D73815: AMDGPU: Fix divergence analysis of control flow intrinsics.

I agree that current expensive walk on IR should be removed.
I initially consider it as a temporary solution that allows to switch to the new concept
of assignment correct register classes keeping in mind to eventually find another way to workaround CF results exceptions.

What I conceptually don't like here is mixing the "divergence" and register class notions.
The mask produced by the CF intrinsics is always scalar - not same as always uniform.

Scalar is the only modeled concept of uniform we have. We don't currently try to model workgroup uniform, so these should be the same

It should work if we can guarantee that the values produced by the CF intrinsics are only used by the another CF intrinsics.
I mean something like AND/OR the uniform mask with some divergent value and then feeding result to another CF...
but normally this should not happen.
Once again: I like getting rid of requiresUniformRegister but insist on the extended testing.
Also, the trouble with LCSSA use of the uniform mask out of the divergent loop need to be solved anyway.

Feb 4 2020, 8:49 AM · Restricted Project
alex-t added a comment to D73815: AMDGPU: Fix divergence analysis of control flow intrinsics.

I agree that current expensive walk on IR should be removed.
I initially consider it as a temporary solution that allows to switch to the new concept
of assignment correct register classes keeping in mind to eventually find another way to workaround CF results exceptions.

Feb 4 2020, 7:54 AM · Restricted Project

Jan 31 2020

alex-t committed rG5df1ac7846c8: [AMDGPU] fixed divergence driven shift operations selection (authored by alex-t).
[AMDGPU] fixed divergence driven shift operations selection
Jan 31 2020, 9:59 AM
alex-t closed D73483: [AMDGPU] fixed divergence driven shift operations selection.
Jan 31 2020, 9:59 AM · Restricted Project
alex-t updated the diff for D73483: [AMDGPU] fixed divergence driven shift operations selection.

llvm.amdgcn.update.dpp test updated

Jan 31 2020, 7:02 AM · Restricted Project
alex-t updated the diff for D73483: [AMDGPU] fixed divergence driven shift operations selection.

i64 tests added

Jan 31 2020, 4:44 AM · Restricted Project
alex-t added a comment to D73483: [AMDGPU] fixed divergence driven shift operations selection.

I expected this to fix the test XFAIL'd in c12f046eb96f8462b3fd3889344ba344de5ace1f, but it seems to to have?

I haven't seen any tests XFAIL'd by this c12f046eb96f8462b3fd3889344ba344de5ace1f commit.
What did you mean? Could you explain please?

Jan 31 2020, 3:13 AM · Restricted Project

Jan 30 2020

alex-t updated the diff for D73483: [AMDGPU] fixed divergence driven shift operations selection.

Diff corrected. GFX10 test added.

Jan 30 2020, 7:36 AM · Restricted Project
alex-t added a comment to D71941: AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses.

As far as I remember the origin of this hack:

Jan 30 2020, 5:08 AM · Restricted Project