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Differential D126292

[MLIR][NFC] Fix the Conversion/MemRefToSPIRV/alloc.mlir test.
ClosedPublic

Authored by kosarev on May 24 2022, 5:19 AM.

Details

Reviewers
antiagainst
rriddle
Commits
rGb3c856d10cee: [MLIR][NFC] Fix the Conversion/MemRefToSPIRV/alloc.mlir test.
Summary

Caught with D125604.

Diff Detail

Event Timeline

kosarev created this revision.May 24 2022, 5:19 AM
Herald added a reviewer: antiagainst. · View Herald TranscriptMay 24 2022, 5:19 AM
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Herald added subscribers: bzcheeseman, sdasgup3, wenzhicui and 21 others. · View Herald Transcript
kosarev requested review of this revision.May 24 2022, 5:19 AM
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kosarev added a reviewer: rriddle.May 24 2022, 5:19 AM
Harbormaster completed remote builds in B166034: Diff 431647.May 24 2022, 5:39 AM
antiagainst accepted this revision.May 24 2022, 8:12 AM
This revision is now accepted and ready to land.May 24 2022, 8:12 AM
Closed by commit rGb3c856d10cee: [MLIR][NFC] Fix the Conversion/MemRefToSPIRV/alloc.mlir test. (authored by kosarev). · Explain WhyMay 25 2022, 6:05 AM
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rGb3c856d10cee: [MLIR][NFC] Fix the Conversion/MemRefToSPIRV/alloc.mlir test..

Revision Contents

PathSize
mlir/
test/
Conversion/
MemRefToSPIRV/
2 lines

Diff 431956

mlir/test/Conversion/MemRefToSPIRV/alloc.mlir

Show All 35 Lines func.func @alloc_dealloc_workgroup_mem(%arg0 : index, %arg1 : index) {
memref.store %1, %0[%arg0, %arg1] : memref<4x5xi16, 3> memref.store %1, %0[%arg0, %arg1] : memref<4x5xi16, 3>
memref.dealloc %0 : memref<4x5xi16, 3> memref.dealloc %0 : memref<4x5xi16, 3>
return return
} }
} }
// CHECK: spv.GlobalVariable @__workgroup_mem__{{[0-9]+}} // CHECK: spv.GlobalVariable @__workgroup_mem__{{[0-9]+}}
// CHECK-SAME: !spv.ptr<!spv.struct<(!spv.array<20 x i32>)>, Workgroup> // CHECK-SAME: !spv.ptr<!spv.struct<(!spv.array<20 x i32>)>, Workgroup>
// CHECK_LABEL: spv.func @alloc_dealloc_workgroup_mem // CHECK: func @alloc_dealloc_workgroup_mem
// CHECK: %[[VAR:.+]] = spv.mlir.addressof @__workgroup_mem__0 // CHECK: %[[VAR:.+]] = spv.mlir.addressof @__workgroup_mem__0
// CHECK: %[[LOC:.+]] = spv.SDiv // CHECK: %[[LOC:.+]] = spv.SDiv
// CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] // CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]]
// CHECK: %{{.+}} = spv.Load "Workgroup" %[[PTR]] : i32 // CHECK: %{{.+}} = spv.Load "Workgroup" %[[PTR]] : i32
// CHECK: %[[LOC:.+]] = spv.SDiv // CHECK: %[[LOC:.+]] = spv.SDiv
// CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]] // CHECK: %[[PTR:.+]] = spv.AccessChain %[[VAR]][%{{.+}}, %[[LOC]]]
// CHECK: %{{.+}} = spv.AtomicAnd "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup> // CHECK: %{{.+}} = spv.AtomicAnd "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup>
// CHECK: %{{.+}} = spv.AtomicOr "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup> // CHECK: %{{.+}} = spv.AtomicOr "Workgroup" "AcquireRelease" %[[PTR]], %{{.+}} : !spv.ptr<i32, Workgroup>
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