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ThomasRaoux (Thomas Raoux)
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User Since
Jul 29 2019, 2:32 PM (60 w, 3 d)

Recent Activity

Wed, Sep 16

ThomasRaoux committed rG4ce84b0e704e: [mlir][spirv] Add GroupNonUniformBroadcastOp (authored by abialas).
[mlir][spirv] Add GroupNonUniformBroadcastOp
Wed, Sep 16, 11:14 PM
ThomasRaoux closed D87688: [mlir][spirv] Add GroupNonUniformBroadcastOp.
Wed, Sep 16, 11:14 PM · Restricted Project
ThomasRaoux added a comment to D87688: [mlir][spirv] Add GroupNonUniformBroadcastOp.

Thanks Thomas for the review, may I ask you to push this change to llvm master?
Btw, to not bother you again with this, is there a process to get RW access to the repo so I can push future changes on my own?

Wed, Sep 16, 10:58 PM · Restricted Project

Tue, Sep 15

ThomasRaoux accepted D87688: [mlir][spirv] Add GroupNonUniformBroadcastOp.
Tue, Sep 15, 7:55 AM · Restricted Project

Fri, Sep 11

ThomasRaoux committed rGaeb4314391f2: [mlir][spirv] OpConvertSToF support operands with different bitwidth. (authored by XinWangIntel).
[mlir][spirv] OpConvertSToF support operands with different bitwidth.
Fri, Sep 11, 10:58 AM
ThomasRaoux closed D87265: OpConvertSToF support operands with different bitwidth, close SameBitWidth check in verifier..
Fri, Sep 11, 10:58 AM · Restricted Project

Wed, Sep 9

ThomasRaoux accepted D87307: [mlir][Analysis] Allow Slice Analysis to work with linalg::LinalgOp.
Wed, Sep 9, 2:14 PM · Restricted Project

Tue, Sep 8

ThomasRaoux accepted D87265: OpConvertSToF support operands with different bitwidth, close SameBitWidth check in verifier..
Tue, Sep 8, 11:47 PM · Restricted Project
ThomasRaoux requested changes to D87265: OpConvertSToF support operands with different bitwidth, close SameBitWidth check in verifier..
Tue, Sep 8, 10:46 PM · Restricted Project
ThomasRaoux added a comment to D87265: OpConvertSToF support operands with different bitwidth, close SameBitWidth check in verifier..

Why is this only for SToFP op? We should keep it consistent for the different converts. Also you need to add test(s).

Tue, Sep 8, 6:15 AM · Restricted Project

Wed, Sep 2

ThomasRaoux added a comment to D86876: [mlir][spirv] Add block read and write from SPV_INTEL_subgroups.

Thanks Thomas, good catch. Please take a look at the updated version. If it looks good, may I ask you to push this change to llvm master?

Wed, Sep 2, 8:08 PM · Restricted Project
ThomasRaoux committed rGd9b4245f56a9: [mlir][spirv] Add block read and write from SPV_INTEL_subgroups (authored by abialas).
[mlir][spirv] Add block read and write from SPV_INTEL_subgroups
Wed, Sep 2, 8:07 PM
ThomasRaoux closed D86876: [mlir][spirv] Add block read and write from SPV_INTEL_subgroups.
Wed, Sep 2, 8:07 PM · Restricted Project
ThomasRaoux accepted D86876: [mlir][spirv] Add block read and write from SPV_INTEL_subgroups.
Wed, Sep 2, 7:50 PM · Restricted Project

Tue, Sep 1

ThomasRaoux added inline comments to D86876: [mlir][spirv] Add block read and write from SPV_INTEL_subgroups.
Tue, Sep 1, 9:58 PM · Restricted Project
ThomasRaoux closed D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..

Committed with https://github.com/llvm/llvm-project/commit/8d655042233bcfe572cdffe529b52e2fc285badf

Tue, Sep 1, 7:22 PM · Restricted Project
ThomasRaoux committed rG8d655042233b: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points. (authored by ThomasRaoux).
[mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points.
Tue, Sep 1, 3:38 PM
ThomasRaoux added a comment to D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..

My only concern with that is that this is compiler dependent. (for instance visual studio doesn't use this notation). Are you suggesting handling this with a ifdef to deal with different compilers? That's what I was trying to avoid.

Putting into the source code makes it more explicit and serves as documentation too. Is there any downside doing that other than handling different compilers? (BTW, IIRC, ORCJIT at the moment does not properly handle Windows COFF so that these runners cannot be run on Windows. But I could miss something.)

Tue, Sep 1, 10:29 AM · Restricted Project
ThomasRaoux updated the diff for D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..
Tue, Sep 1, 10:28 AM · Restricted Project
ThomasRaoux added inline comments to D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..
Tue, Sep 1, 9:46 AM · Restricted Project

Sat, Aug 29

ThomasRaoux added a comment to D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..

The file path is quite... unusual ;)

Sat, Aug 29, 9:37 AM · Restricted Project
ThomasRaoux updated the diff for D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..
Sat, Aug 29, 9:37 AM · Restricted Project

Fri, Aug 28

ThomasRaoux added a reviewer for D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points.: GMNGeoffrey.
Fri, Aug 28, 6:54 PM · Restricted Project
ThomasRaoux requested review of D86829: [mlir][vulkan-runner] Explicitly export vulkan-runtime-wrapper entry points..
Fri, Aug 28, 6:50 PM · Restricted Project

Wed, Aug 26

ThomasRaoux committed rG5fbfe2ec4f8b: [mlir][vector] Add vector.bitcast operation (authored by ThomasRaoux).
[mlir][vector] Add vector.bitcast operation
Wed, Aug 26, 2:17 PM
ThomasRaoux closed D86580: [mlir][vector] Add vector.bitcast operation.
Wed, Aug 26, 2:17 PM · Restricted Project
ThomasRaoux updated the diff for D86580: [mlir][vector] Add vector.bitcast operation.
Wed, Aug 26, 2:10 PM · Restricted Project
ThomasRaoux added a comment to D86580: [mlir][vector] Add vector.bitcast operation.

Thanks Aart. Please take another look.

Wed, Aug 26, 12:36 PM · Restricted Project
ThomasRaoux updated the diff for D86580: [mlir][vector] Add vector.bitcast operation.

Address code review comments

Wed, Aug 26, 12:35 PM · Restricted Project

Tue, Aug 25

ThomasRaoux committed rG6a3c69e918b1: [mlir][spirv] Infer converted type of scf.for from the init value (authored by ThomasRaoux).
[mlir][spirv] Infer converted type of scf.for from the init value
Tue, Aug 25, 11:36 PM
ThomasRaoux closed D86582: [mlir][spirv] Infer converted type of scf.for from the init value.
Tue, Aug 25, 11:36 PM · Restricted Project
ThomasRaoux added a comment to D86582: [mlir][spirv] Infer converted type of scf.for from the init value.

Thanks Mahesh for the review. I added extra context explaining why we do it that way and we can revisit later.

Tue, Aug 25, 11:13 PM · Restricted Project
ThomasRaoux updated the diff for D86582: [mlir][spirv] Infer converted type of scf.for from the init value.

Add extra comment

Tue, Aug 25, 11:12 PM · Restricted Project

Aug 25 2020

ThomasRaoux added inline comments to D86580: [mlir][vector] Add vector.bitcast operation.
Aug 25 2020, 5:27 PM · Restricted Project
ThomasRaoux updated the diff for D86580: [mlir][vector] Add vector.bitcast operation.
Aug 25 2020, 5:27 PM · Restricted Project
ThomasRaoux requested review of D86582: [mlir][spirv] Infer converted type of scf.for from the init value.
Aug 25 2020, 5:14 PM · Restricted Project
ThomasRaoux requested review of D86580: [mlir][vector] Add vector.bitcast operation.
Aug 25 2020, 4:34 PM · Restricted Project

Aug 21 2020

ThomasRaoux committed rG36ee9a322a44: [mlir][GPUToVulkan] Fix signature of bindMemRef function for f16 (authored by ThomasRaoux).
[mlir][GPUToVulkan] Fix signature of bindMemRef function for f16
Aug 21 2020, 10:48 AM
ThomasRaoux closed D86328: [mlir][GPUToVulkan] Fix signature of bindMemRef function for f16.
Aug 21 2020, 10:48 AM · Restricted Project

Aug 20 2020

ThomasRaoux requested review of D86328: [mlir][GPUToVulkan] Fix signature of bindMemRef function for f16.
Aug 20 2020, 8:13 PM · Restricted Project

Aug 17 2020

ThomasRaoux accepted D86095: [mlir][Linalg] Modify callback for getting id/nprocs in LinalgDistribution options to allow more general distributions..

Looks good to me.

Aug 17 2020, 3:43 PM · Restricted Project

Aug 13 2020

ThomasRaoux accepted D85769: [mlir] [VectorOps] Canonicalization of 1-D memory operations.

Looks good to me

Aug 13 2020, 1:36 PM · Restricted Project

Aug 10 2020

ThomasRaoux committed rG0de60b550b72: [mlir] Fix mlir build break due to warning when NDEBUG is not set (authored by ThomasRaoux).
[mlir] Fix mlir build break due to warning when NDEBUG is not set
Aug 10 2020, 3:35 PM
ThomasRaoux committed rGa8fe40d97327: [mlir][spirv] Add OpGroupBroadcast (authored by abialas).
[mlir][spirv] Add OpGroupBroadcast
Aug 10 2020, 9:50 AM
ThomasRaoux closed D85435: [mlir][spirv] Add OpGroupBroadcast.
Aug 10 2020, 9:50 AM · Restricted Project
ThomasRaoux committed rG68330ee0a977: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand (authored by ThomasRaoux).
[mlir][vector] Relax transfer_read/transfer_write restriction on memref operand
Aug 10 2020, 8:58 AM
ThomasRaoux closed D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.
Aug 10 2020, 8:58 AM · Restricted Project
ThomasRaoux updated the diff for D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.

Address review comments

Aug 10 2020, 8:29 AM · Restricted Project

Aug 7 2020

ThomasRaoux accepted D85435: [mlir][spirv] Add OpGroupBroadcast.

Thanks Artur. Looks good to me.

Aug 7 2020, 1:49 AM · Restricted Project

Aug 6 2020

ThomasRaoux added a comment to D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.

The relaxing is too brutal IMO and will likely create multiple issues related to lowering to SCF and LLVM.
To reduce the pain in making this work with transformations I'd suggest to add restrictions on the type.
Basically you're only allowed to:

  1. take elements immediately to the left of your element type in the memref and stick these into the vector.
  2. cast to vector types that have the same number fo bits and a power of 2 size.

Anything else will be a significant amount of pain until we have a solid DataLayout in MLIR.

So basically you can allow the existing semantic + exactly 1 vector type_cast that changes vector type.

memref<axbxcxdxvector<txuxvxf32>> -> memref<axbx | cxdxvector<txuxvxf32>> -> memref<axbx vector<cxdxtxuxvxf32>> -> memref<axbx vector<whatever>> -> vector<whatever>, where:

  1. | is a separator that you can put anywhere on the memref (just like the current vector.type_cast)
  2. whatever has the same bitsize and alignment as cxdxtxuxvxf32.

To make 2. reasonably simple I'd say just allow the most minor of whatever and v x f32 that have a power of 2 size if you want to cast the element type.

I'd recommend very slowly and very carefully relaxing the constraints to match your needs without stepping out of bounds for now.

Aug 6 2020, 5:27 PM · Restricted Project
ThomasRaoux updated the diff for D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.

Add extra restrictions.

Aug 6 2020, 5:25 PM · Restricted Project
ThomasRaoux added inline comments to D85147: [mlir][Linalg] Allow distribution `scf.parallel` loops generated in Linalg to processors..
Aug 6 2020, 1:06 PM · Restricted Project
ThomasRaoux added inline comments to D85435: [mlir][spirv] Add OpGroupBroadcast.
Aug 6 2020, 9:56 AM · Restricted Project

Aug 5 2020

ThomasRaoux added a comment to D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.

The relaxing is too brutal IMO and will likely create multiple issues related to lowering to SCF and LLVM.
To reduce the pain in making this work with transformations I'd suggest to add restrictions on the type.
Basically you're only allowed to:

  1. take elements immediately to the left of your element type in the memref and stick these into the vector.
  2. cast to vector types that have the same number fo bits and a power of 2 size.

Anything else will be a significant amount of pain until we have a solid DataLayout in MLIR.

So basically you can allow the existing semantic + exactly 1 vector type_cast that changes vector type.

memref<axbxcxdxvector<txuxvxf32>> -> memref<axbx | cxdxvector<txuxvxf32>> -> memref<axbx vector<cxdxtxuxvxf32>> -> memref<axbx vector<whatever>> -> vector<whatever>, where:

  1. | is a separator that you can put anywhere on the memref (just like the current vector.type_cast)
  2. whatever has the same bitsize and alignment as cxdxtxuxvxf32.

To make 2. reasonably simple I'd say just allow the most minor of whatever and v x f32 that have a power of 2 size if you want to cast the element type.

I'd recommend very slowly and very carefully relaxing the constraints to match your needs without stepping out of bounds for now.

Aug 5 2020, 2:46 PM · Restricted Project
ThomasRaoux abandoned D85058: [mlir][vector] Add experimental memref cast operation..

I'm abandoning this change as it is not needed after https://reviews.llvm.org/D85244.

Aug 5 2020, 11:55 AM · Restricted Project

Aug 4 2020

ThomasRaoux added inline comments to D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.
Aug 4 2020, 5:03 PM · Restricted Project
ThomasRaoux updated the diff for D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.

rebase

Aug 4 2020, 5:02 PM · Restricted Project
ThomasRaoux added a comment to D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.

also, with the restrictions out of the way, did you make sure this does not crash the lowering to llvm part (try out a few of your new examples). you may have to return failure() in the lowering logic itself if it breaks anything....

Aug 4 2020, 3:45 PM · Restricted Project
ThomasRaoux updated the diff for D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.
Aug 4 2020, 3:44 PM · Restricted Project
ThomasRaoux updated the diff for D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.
Aug 4 2020, 3:18 PM · Restricted Project
ThomasRaoux requested review of D85244: [mlir][vector] Relax transfer_read/transfer_write restriction on memref operand.
Aug 4 2020, 1:59 PM · Restricted Project

Aug 3 2020

ThomasRaoux added a reviewer for D85058: [mlir][vector] Add experimental memref cast operation.: ftynse.
Aug 3 2020, 8:04 AM · Restricted Project

Aug 2 2020

ThomasRaoux added a comment to D85058: [mlir][vector] Add experimental memref cast operation..

Does this op really belong to the vector dialect?

It seems like you're plugging a hole somewhere, but it isn't clear what or why this is desirable. Can you explain this in a thread on Discourse?

I agree that understanding the need better would help. We already have reshape/type_cast/shape_cast ops with somewhat specific behaviors, and I want to make sure we design the right operations (preferable just a few).

Aug 2 2020, 6:01 PM · Restricted Project

Jul 31 2020

ThomasRaoux requested review of D85058: [mlir][vector] Add experimental memref cast operation..
Jul 31 2020, 4:39 PM · Restricted Project
ThomasRaoux committed rGcfb955ac370c: [mlir][spirv] Relax restriction on pointer type for CooperativeMatrix load/store (authored by ThomasRaoux).
[mlir][spirv] Relax restriction on pointer type for CooperativeMatrix load/store
Jul 31 2020, 9:03 AM
ThomasRaoux closed D84993: [mlir][spirv] Relax restriction on pointer type for CooperativeMatrix load/store.
Jul 31 2020, 9:03 AM · Restricted Project

Jul 30 2020

ThomasRaoux added inline comments to D84993: [mlir][spirv] Relax restriction on pointer type for CooperativeMatrix load/store.
Jul 30 2020, 7:56 PM · Restricted Project
ThomasRaoux updated the diff for D84993: [mlir][spirv] Relax restriction on pointer type for CooperativeMatrix load/store.
Jul 30 2020, 7:53 PM · Restricted Project
ThomasRaoux requested review of D84993: [mlir][spirv] Relax restriction on pointer type for CooperativeMatrix load/store.
Jul 30 2020, 5:53 PM · Restricted Project
ThomasRaoux committed rG59156bad03ff: [mlir][spirv] Add support for converting memref of vector to SPIR-V (authored by ThomasRaoux).
[mlir][spirv] Add support for converting memref of vector to SPIR-V
Jul 30 2020, 3:06 PM
ThomasRaoux closed D84982: [mlir][spirv] Add support for converting memref of vector to SPIR-V.
Jul 30 2020, 3:06 PM · Restricted Project
ThomasRaoux added inline comments to D84982: [mlir][spirv] Add support for converting memref of vector to SPIR-V.
Jul 30 2020, 2:54 PM · Restricted Project
ThomasRaoux updated the diff for D84982: [mlir][spirv] Add support for converting memref of vector to SPIR-V.
Jul 30 2020, 2:53 PM · Restricted Project
ThomasRaoux added inline comments to D84982: [mlir][spirv] Add support for converting memref of vector to SPIR-V.
Jul 30 2020, 2:35 PM · Restricted Project
ThomasRaoux updated the diff for D84982: [mlir][spirv] Add support for converting memref of vector to SPIR-V.

Address review comments

Jul 30 2020, 2:33 PM · Restricted Project
ThomasRaoux requested review of D84982: [mlir][spirv] Add support for converting memref of vector to SPIR-V.
Jul 30 2020, 1:56 PM · Restricted Project

Jul 22 2020

ThomasRaoux committed rGa1b9fb220f6d: [mlir][linalg] Add vectorization transform for CopyOp (authored by ThomasRaoux).
[mlir][linalg] Add vectorization transform for CopyOp
Jul 22 2020, 12:41 PM
ThomasRaoux closed D83739: [mlir][linalg] Add vectorization transform for CopyOp.
Jul 22 2020, 12:41 PM · Restricted Project

Jul 15 2020

ThomasRaoux added inline comments to D83739: [mlir][linalg] Add vectorization transform for CopyOp.
Jul 15 2020, 10:26 AM · Restricted Project
ThomasRaoux updated the diff for D83739: [mlir][linalg] Add vectorization transform for CopyOp.

Handle scalar case and add a test for it.

Jul 15 2020, 10:26 AM · Restricted Project

Jul 13 2020

Herald added a project to D83739: [mlir][linalg] Add vectorization transform for CopyOp: Restricted Project.
Jul 13 2020, 9:14 PM · Restricted Project
ThomasRaoux accepted D83714: [mlir][StandardToSPIRV] Use spv.UMod for index re-calculation.
Jul 13 2020, 1:26 PM · Restricted Project
ThomasRaoux committed rG2f23270af9bb: [mlir] Support operations with multiple results in slicing (authored by ThomasRaoux).
[mlir] Support operations with multiple results in slicing
Jul 13 2020, 1:25 PM
ThomasRaoux closed D83627: [mlir] Support operations with multiple results in slicing.
Jul 13 2020, 1:25 PM · Restricted Project
ThomasRaoux added inline comments to D83627: [mlir] Support operations with multiple results in slicing.
Jul 13 2020, 1:02 PM · Restricted Project
ThomasRaoux updated the diff for D83627: [mlir] Support operations with multiple results in slicing.
Jul 13 2020, 12:56 PM · Restricted Project
ThomasRaoux updated the diff for D83627: [mlir] Support operations with multiple results in slicing.
Jul 13 2020, 11:22 AM · Restricted Project
ThomasRaoux accepted D83679: [mlir][StandardToSPIRV] Fix conversion for signed remainder.
Jul 13 2020, 10:59 AM · Restricted Project

Jul 12 2020

ThomasRaoux updated the diff for D83627: [mlir] Support operations with multiple results in slicing.
Jul 12 2020, 10:25 PM · Restricted Project
ThomasRaoux added inline comments to D83627: [mlir] Support operations with multiple results in slicing.
Jul 12 2020, 10:24 PM · Restricted Project
ThomasRaoux updated the diff for D83627: [mlir] Support operations with multiple results in slicing.

Address review comments.

Jul 12 2020, 10:21 PM · Restricted Project

Jul 11 2020

Herald added a project to D83627: [mlir] Support operations with multiple results in slicing: Restricted Project.
Jul 11 2020, 11:47 AM · Restricted Project

Jul 10 2020

ThomasRaoux committed rG6d5aeb0dceeb: [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write (authored by ThomasRaoux).
[mlir][linalg] Improve aliasing approximation for hoisting transfer read/write
Jul 10 2020, 3:09 PM
ThomasRaoux closed D83538: [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write. .
Jul 10 2020, 3:09 PM · Restricted Project
ThomasRaoux updated the diff for D83538: [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write. .

Address review comments

Jul 10 2020, 2:50 PM · Restricted Project
ThomasRaoux updated the diff for D83538: [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write. .

Thanks Nicolas. I addressed the review, please take another look to confirm that I got it right. Based on what you mentioned my understanding is that if any indices are different in the first ranks (from 0 to memrefRank-vectorRank) then the slices are disjoint for the rest of the ranks I check that the distance between the offset is smaller that the vector size (since I check that the vector types must match)

Jul 10 2020, 12:50 PM · Restricted Project
Herald added a project to D83538: [mlir][linalg] Improve aliasing approximation for hoisting transfer read/write. : Restricted Project.
Jul 10 2020, 12:27 AM · Restricted Project

Jul 9 2020

ThomasRaoux accepted D83476: [mlir][Vector] Fold chains of ExtractOp.

LGTM

Jul 9 2020, 10:32 AM · Restricted Project

Jul 6 2020

ThomasRaoux added inline comments to D83146: [mlir][Vector] Add custom slt / SCF.if folding to VectorToSCF.
Jul 6 2020, 12:54 AM · Restricted Project

Jul 1 2020

ThomasRaoux committed rGfbce9855e9d5: [mlir][NFC] Move conversion of scf to spir-v ops in their own file (authored by ThomasRaoux).
[mlir][NFC] Move conversion of scf to spir-v ops in their own file
Jul 1 2020, 5:18 PM