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ThomasRaoux (Thomas Raoux)
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User Since
Jul 29 2019, 2:32 PM (7 w, 1 d)

Recent Activity

Yesterday

ThomasRaoux added a comment to D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..

On the other hand, I don't really want to spend much time thinking about how to make SelectionDAG better at this point.

I agree, that's kind of my worry with opening this pandora's box. Changing hooks in SDAG and maintaining performance parity is very hard, and we have a longer term solution in Global Isel.

Given that, and given the NFC-ness of this patch, are you happy for it to go in?

I'm not happy about it but not too opposed. I'd like someone else's opinion

I would somewhat prefer we split the current function into something like memoryAccessIsLegalForAlignment that has the current behavior, and this would be a separate function defaulting to calling it (Yes, I know this makes the problem worse)

Tue, Sep 17, 6:18 PM · Restricted Project

Mon, Sep 9

ThomasRaoux updated the diff for D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Mon, Sep 9, 6:24 PM · Restricted Project
ThomasRaoux added a comment to D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..

I added a new function allowsMemoryAccessForAlignment to handle the behavior of the previous allowsMemoryAccess function. I replaced the calls every except for DAGCombine as my understanding is that this place really mean to check that the memory access is legal and won't require legalization to expensive code sequence.

Mon, Sep 9, 6:15 PM · Restricted Project
ThomasRaoux updated the summary of D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Mon, Sep 9, 6:11 PM · Restricted Project
ThomasRaoux updated the diff for D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Mon, Sep 9, 6:10 PM · Restricted Project

Thu, Sep 5

ThomasRaoux accepted D66936: [DFAPacketizer] Track resources for packetized instructions.
Thu, Sep 5, 9:40 AM · Restricted Project

Wed, Sep 4

ThomasRaoux added a comment to D66936: [DFAPacketizer] Track resources for packetized instructions.

Your summary says that the extended tracking is disable by default on hexagon. Which extra tracking is that? I don't see any part disabled for Hexagon?

Wed, Sep 4, 10:47 AM · Restricted Project

Tue, Sep 3

ThomasRaoux accepted D67081: [ModuloSchedule] Introduce PeelingModuloScheduleExpander.
Tue, Sep 3, 4:50 PM · Restricted Project
ThomasRaoux added a comment to D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..

It seems to me like this is a workaround for the quite inadequate system for defining legality for a load/store. I think allowsMemoryAccess is poorly named; It exists to just check if the type is aligned before calling allowsMisalignedMemoryAccesses. Your problem sounds more like we need a better system for checking if a store/trunc store is legal

Tue, Sep 3, 11:49 AM · Restricted Project
ThomasRaoux created D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Tue, Sep 3, 11:26 AM · Restricted Project

Mon, Sep 2

ThomasRaoux accepted D67011: [MachinePipeliner] Add a way to unit-test the schedule emitter.

Looks good to me

Mon, Sep 2, 9:52 PM · Restricted Project
ThomasRaoux abandoned D65424: [Packetizer] Increase the size of DFAInput bitfield to allow up to 32 units.
Mon, Sep 2, 9:34 PM · Restricted Project
ThomasRaoux added inline comments to D67081: [ModuloSchedule] Introduce PeelingModuloScheduleExpander.
Mon, Sep 2, 9:34 PM · Restricted Project
ThomasRaoux closed D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Mon, Sep 2, 9:34 PM · Restricted Project

Fri, Aug 30

ThomasRaoux accepted D66940: [DFAPacketizer] Allow namespacing of automata per-itinerary.

This is great, will be very helpful.

Fri, Aug 30, 9:58 AM · Restricted Project
ThomasRaoux accepted D67006: [MachinePipeliner] Separate schedule emission, NFC.

Looks good to me.

Fri, Aug 30, 9:30 AM · Restricted Project

Tue, Aug 20

ThomasRaoux committed rG53ab6bef98e7: [CodeGen] Add EarlyIfConvert test missed in previous commit (authored by ThomasRaoux).
[CodeGen] Add EarlyIfConvert test missed in previous commit
Tue, Aug 20, 9:35 AM
ThomasRaoux committed rL369405: [CodeGen] Add EarlyIfConvert test missed in previous commit.
[CodeGen] Add EarlyIfConvert test missed in previous commit
Tue, Aug 20, 9:35 AM
ThomasRaoux committed rGbe699bf38995: [CodeGen] Add a pass to do block predication on SSA machine IR. (authored by ThomasRaoux).
[CodeGen] Add a pass to do block predication on SSA machine IR.
Tue, Aug 20, 8:56 AM
ThomasRaoux committed rL369395: [CodeGen] Add a pass to do block predication on SSA machine IR..
[CodeGen] Add a pass to do block predication on SSA machine IR.
Tue, Aug 20, 8:56 AM

Mon, Aug 19

ThomasRaoux committed rGa08e139d5074: [NFC] Test commit, fix some comment spelling. (authored by ThomasRaoux).
[NFC] Test commit, fix some comment spelling.
Mon, Aug 19, 10:21 PM
ThomasRaoux committed rL369326: [NFC] Test commit, fix some comment spelling..
[NFC] Test commit, fix some comment spelling.
Mon, Aug 19, 10:21 PM

Aug 19 2019

ThomasRaoux updated the summary of D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 19 2019, 11:09 AM · Restricted Project

Aug 16 2019

ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 16 2019, 11:08 AM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 16 2019, 11:08 AM · Restricted Project

Aug 15 2019

ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 15 2019, 3:36 PM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 15 2019, 3:29 PM · Restricted Project
ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 15 2019, 12:42 AM · Restricted Project

Aug 14 2019

ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 6:12 PM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 6:10 PM · Restricted Project
ThomasRaoux added a comment to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.

I figured the functionality can be tested with Hexagon backend, so I added a test in Hexagon target to test the predication.

Aug 14 2019, 3:54 PM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 3:50 PM · Restricted Project
ThomasRaoux added a comment to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.

One more question - i can't recall if there's precedent for bundling more than one pass
into the same source file, that does not look ideal.

Aug 14 2019, 8:09 AM · Restricted Project
ThomasRaoux added a comment to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.

Tests missing; please upload all patches with full context (-U99999)

Aug 14 2019, 1:45 AM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 1:40 AM · Restricted Project

Aug 13 2019

ThomasRaoux created D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 13 2019, 5:32 PM · Restricted Project

Aug 2 2019

ThomasRaoux added a comment to D65424: [Packetizer] Increase the size of DFAInput bitfield to allow up to 32 units.

This seems to hang when compiling HexagonInstrInfo.cpp.

Aug 2 2019, 12:46 AM · Restricted Project

Jul 29 2019

ThomasRaoux created D65424: [Packetizer] Increase the size of DFAInput bitfield to allow up to 32 units.
Jul 29 2019, 4:38 PM · Restricted Project