Page MenuHomePhabricator

ThomasRaoux (Thomas Raoux)
User

Projects

User does not belong to any projects.

User Details

User Since
Jul 29 2019, 2:32 PM (25 w, 1 d)

Recent Activity

Dec 10 2019

ThomasRaoux accepted D71273: [CodeGen] Use MachineBranchProbabilityInfo in EarlyIfPredicator to avoid the potential bug.

LGTM

Dec 10 2019, 6:09 PM · Restricted Project

Dec 9 2019

ThomasRaoux added a comment to D71122: [ModuloSchedule] Fix data types in ModuloScheduleExpander::isLoopCarried.

Thank you very much for your quick review.
I don't have commit access.
Could you commit this patch?

Committed:
https://github.com/llvm/llvm-project/commit/caabb713ea157f8c449c8d3eb00410bbef734a22

Dec 9 2019, 7:47 AM · Restricted Project

Dec 6 2019

ThomasRaoux accepted D71122: [ModuloSchedule] Fix data types in ModuloScheduleExpander::isLoopCarried.

Thanks for catching that!

Dec 6 2019, 8:57 AM · Restricted Project

Nov 22 2019

ThomasRaoux added a comment to D70213: [ModuloSchedule] Fix a bug in experimental expander during prologue/epilogue stitching..

LGTM, sorry for the delay.

Nov 22 2019, 9:03 AM · Restricted Project
ThomasRaoux added a comment to D70213: [ModuloSchedule] Fix a bug in experimental expander during prologue/epilogue stitching..

@jmolloy, could you take one more look when you get a chance?

Nov 22 2019, 7:27 AM · Restricted Project

Nov 14 2019

ThomasRaoux added inline comments to D70213: [ModuloSchedule] Fix a bug in experimental expander during prologue/epilogue stitching..
Nov 14 2019, 10:06 AM · Restricted Project
ThomasRaoux updated the diff for D70213: [ModuloSchedule] Fix a bug in experimental expander during prologue/epilogue stitching..
Nov 14 2019, 9:57 AM · Restricted Project
ThomasRaoux updated the diff for D70213: [ModuloSchedule] Fix a bug in experimental expander during prologue/epilogue stitching..
Nov 14 2019, 9:57 AM · Restricted Project

Nov 13 2019

ThomasRaoux created D70213: [ModuloSchedule] Fix a bug in experimental expander during prologue/epilogue stitching..
Nov 13 2019, 4:40 PM · Restricted Project

Nov 11 2019

ThomasRaoux closed D69912: [ModuloSchedule] Do target loop analysis before peeling..

Committed with 03da6e8c00de2320e6b9dacba8f7850faceae319

Nov 11 2019, 10:37 PM · Restricted Project

Nov 6 2019

ThomasRaoux added inline comments to D69538: [ModuloSchedule] Fix experimental modulo expansion for data loop carried dependencies..
Nov 6 2019, 2:56 PM · Restricted Project
ThomasRaoux updated the diff for D69538: [ModuloSchedule] Fix experimental modulo expansion for data loop carried dependencies..
Nov 6 2019, 2:56 PM · Restricted Project
ThomasRaoux created D69912: [ModuloSchedule] Do target loop analysis before peeling..
Nov 6 2019, 10:36 AM · Restricted Project

Oct 31 2019

ThomasRaoux accepted D69110: [DFAPacketizer] Allow up to 64 functional units.

Looks good to me.

Oct 31 2019, 10:29 AM · Restricted Project

Oct 28 2019

ThomasRaoux created D69538: [ModuloSchedule] Fix experimental modulo expansion for data loop carried dependencies..
Oct 28 2019, 4:36 PM · Restricted Project

Oct 16 2019

ThomasRaoux accepted D68992: [DFAPacketizer] Use DFAEmitter. NFC..

Awesome cleanup!

Oct 16 2019, 5:37 PM · Restricted Project

Oct 1 2019

ThomasRaoux accepted D68205: [ModuloSchedule] Peel out prologs and epilogs, generate actual code.

Hi Thomas,

I made an example to show how this is handled.

%11:intregs = S2_addasl_rrri %7, %6, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
%12:intregs = L2_loadruh_io %11, -4, post-instr-symbol <mcsymbol Stage-1_Cycle-0> :: (load 2 from %ir.cgep2, !tbaa !0)
%5:intregs = S2_storerh_pi %6, -2, %12, post-instr-symbol <mcsymbol Stage-2_Cycle-0> :: (store 2 into %ir.lsr.iv, !tbaa !0)
ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0

We generate this code, annotated:

 <... prolog, boring ...>
 
bb.3.b2 (address-taken):  // Kernel.
  successors: %bb.3(0x7c000000), %bb.10(0x04000000)
 
  %15:intregs = PHI %25, %bb.6, %11, %bb.3
  %17:intregs = PHI %26, %bb.6, %12, %bb.3
  %11:intregs = S2_addasl_rrri %7, %6, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
  %12:intregs = L2_loadruh_io %15, -4, post-instr-symbol <mcsymbol Stage-1_Cycle-0> :: (load 2 from %ir.cgep2, !tbaa !0)
  dead %5:intregs = S2_storerh_pi %6, -2, %17, post-instr-symbol <mcsymbol Stage-2_Cycle-0> :: (store 2 into %ir.lsr.iv, !tbaa !0)
  ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
  J2_jump %bb.10, implicit-def $pc
 
bb.10.b2:  // Epilog 0, runs stage 2
  successors: %bb.9(0x80000000)
 
  %40:intregs = PHI %11, %bb.3, %25, %bb.6
  %41:intregs = PHI %12, %bb.3, %26, %bb.6
  dead %44:intregs = S2_storerh_pi %6, -2, %41, post-instr-symbol <mcsymbol Stage-2_Cycle-0> :: (store 2 into %ir.lsr.iv, !tbaa !0)
  J2_jump %bb.9, implicit-def $pc
 
bb.9.b2:  // Start of Epilog 1, runs stage 1
  successors: %bb.8(0x80000000)
 
  %35:intregs = PHI %40, %bb.10, %20, %bb.5
  %38:intregs = L2_loadruh_io %35, -4, post-instr-symbol <mcsymbol Stage-1_Cycle-0> :: (load 2 from %ir.cgep2, !tbaa !0)
  J2_jump %bb.8, implicit-def $pc
 
bb.8.b2:  // Next stage of Epilog 1, runs stage 2
  successors: %bb.7(0x80000000)
 
  dead %34:intregs = S2_storerh_pi %6, -2, %38, post-instr-symbol <mcsymbol Stage-2_Cycle-0> :: (store 2 into %ir.lsr.iv, !tbaa !0)
  J2_jump %bb.7, implicit-def $pc

The key is that though E1 runs stages {1,2}, we *don't* create a block with both stages {1,2} enabled. This would cause the invalid code issue you mentioned. Instead, we expand this into *two* blocks. The first performs stage 1, the second stage 2 which consumes its input from stage 1.

That means we do generate superfluous epilog blocks, but these get merged by the control flow optimizer later.

That said, I'm not guaranteeing there are no bugs here. Perhaps the testcase you're thinking of distills to something more complex than my testcase?

Cheers,

James

Oct 1 2019, 9:37 AM · Restricted Project

Sep 30 2019

ThomasRaoux added inline comments to D68205: [ModuloSchedule] Peel out prologs and epilogs, generate actual code.
Sep 30 2019, 9:18 PM · Restricted Project

Sep 25 2019

ThomasRaoux committed rG3c8c6672358a: [TargetLowering] Make allowsMemoryAccess methode virtual. (authored by ThomasRaoux).
[TargetLowering] Make allowsMemoryAccess methode virtual.
Sep 25 2019, 5:17 PM
ThomasRaoux committed rL372935: [TargetLowering] Make allowsMemoryAccess methode virtual..
[TargetLowering] Make allowsMemoryAccess methode virtual.
Sep 25 2019, 5:17 PM
ThomasRaoux closed D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Sep 25 2019, 5:17 PM · Restricted Project

Sep 17 2019

ThomasRaoux added a comment to D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..

On the other hand, I don't really want to spend much time thinking about how to make SelectionDAG better at this point.

I agree, that's kind of my worry with opening this pandora's box. Changing hooks in SDAG and maintaining performance parity is very hard, and we have a longer term solution in Global Isel.

Given that, and given the NFC-ness of this patch, are you happy for it to go in?

I'm not happy about it but not too opposed. I'd like someone else's opinion

I would somewhat prefer we split the current function into something like memoryAccessIsLegalForAlignment that has the current behavior, and this would be a separate function defaulting to calling it (Yes, I know this makes the problem worse)

Sep 17 2019, 6:18 PM · Restricted Project

Sep 9 2019

ThomasRaoux updated the diff for D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Sep 9 2019, 6:24 PM · Restricted Project
ThomasRaoux added a comment to D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..

I added a new function allowsMemoryAccessForAlignment to handle the behavior of the previous allowsMemoryAccess function. I replaced the calls every except for DAGCombine as my understanding is that this place really mean to check that the memory access is legal and won't require legalization to expensive code sequence.

Sep 9 2019, 6:15 PM · Restricted Project
ThomasRaoux updated the summary of D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Sep 9 2019, 6:11 PM · Restricted Project
ThomasRaoux updated the diff for D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Sep 9 2019, 6:10 PM · Restricted Project

Sep 5 2019

ThomasRaoux accepted D66936: [DFAPacketizer] Track resources for packetized instructions.
Sep 5 2019, 9:40 AM · Restricted Project

Sep 4 2019

ThomasRaoux added a comment to D66936: [DFAPacketizer] Track resources for packetized instructions.

Your summary says that the extended tracking is disable by default on hexagon. Which extra tracking is that? I don't see any part disabled for Hexagon?

Sep 4 2019, 10:47 AM · Restricted Project

Sep 3 2019

ThomasRaoux accepted D67081: [ModuloSchedule] Introduce PeelingModuloScheduleExpander.
Sep 3 2019, 4:50 PM · Restricted Project
ThomasRaoux added a comment to D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..

It seems to me like this is a workaround for the quite inadequate system for defining legality for a load/store. I think allowsMemoryAccess is poorly named; It exists to just check if the type is aligned before calling allowsMisalignedMemoryAccesses. Your problem sounds more like we need a better system for checking if a store/trunc store is legal

Sep 3 2019, 11:49 AM · Restricted Project
ThomasRaoux created D67121: [TargetLowering] Make allowsMemoryAccess methode virtual..
Sep 3 2019, 11:26 AM · Restricted Project

Sep 2 2019

ThomasRaoux accepted D67011: [MachinePipeliner] Add a way to unit-test the schedule emitter.

Looks good to me

Sep 2 2019, 9:52 PM · Restricted Project
ThomasRaoux abandoned D65424: [Packetizer] Increase the size of DFAInput bitfield to allow up to 32 units.
Sep 2 2019, 9:34 PM · Restricted Project
ThomasRaoux added inline comments to D67081: [ModuloSchedule] Introduce PeelingModuloScheduleExpander.
Sep 2 2019, 9:34 PM · Restricted Project
ThomasRaoux closed D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Sep 2 2019, 9:34 PM · Restricted Project

Aug 30 2019

ThomasRaoux accepted D66940: [DFAPacketizer] Allow namespacing of automata per-itinerary.

This is great, will be very helpful.

Aug 30 2019, 9:58 AM · Restricted Project
ThomasRaoux accepted D67006: [MachinePipeliner] Separate schedule emission, NFC.

Looks good to me.

Aug 30 2019, 9:30 AM · Restricted Project

Aug 20 2019

ThomasRaoux committed rG53ab6bef98e7: [CodeGen] Add EarlyIfConvert test missed in previous commit (authored by ThomasRaoux).
[CodeGen] Add EarlyIfConvert test missed in previous commit
Aug 20 2019, 9:35 AM
ThomasRaoux committed rL369405: [CodeGen] Add EarlyIfConvert test missed in previous commit.
[CodeGen] Add EarlyIfConvert test missed in previous commit
Aug 20 2019, 9:35 AM
ThomasRaoux committed rGbe699bf38995: [CodeGen] Add a pass to do block predication on SSA machine IR. (authored by ThomasRaoux).
[CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 20 2019, 8:56 AM
ThomasRaoux committed rL369395: [CodeGen] Add a pass to do block predication on SSA machine IR..
[CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 20 2019, 8:56 AM

Aug 19 2019

ThomasRaoux committed rGa08e139d5074: [NFC] Test commit, fix some comment spelling. (authored by ThomasRaoux).
[NFC] Test commit, fix some comment spelling.
Aug 19 2019, 10:21 PM
ThomasRaoux committed rL369326: [NFC] Test commit, fix some comment spelling..
[NFC] Test commit, fix some comment spelling.
Aug 19 2019, 10:21 PM
ThomasRaoux updated the summary of D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 19 2019, 11:09 AM · Restricted Project

Aug 16 2019

ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 16 2019, 11:08 AM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 16 2019, 11:08 AM · Restricted Project

Aug 15 2019

ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 15 2019, 3:36 PM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 15 2019, 3:29 PM · Restricted Project
ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 15 2019, 12:42 AM · Restricted Project

Aug 14 2019

ThomasRaoux added inline comments to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 6:12 PM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 6:10 PM · Restricted Project
ThomasRaoux added a comment to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.

I figured the functionality can be tested with Hexagon backend, so I added a test in Hexagon target to test the predication.

Aug 14 2019, 3:54 PM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 3:50 PM · Restricted Project
ThomasRaoux added a comment to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.

One more question - i can't recall if there's precedent for bundling more than one pass
into the same source file, that does not look ideal.

Aug 14 2019, 8:09 AM · Restricted Project
ThomasRaoux added a comment to D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.

Tests missing; please upload all patches with full context (-U99999)

Aug 14 2019, 1:45 AM · Restricted Project
ThomasRaoux updated the diff for D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 14 2019, 1:40 AM · Restricted Project

Aug 13 2019

ThomasRaoux created D66190: [CodeGen] Add a pass to do block predication on SSA machine IR.
Aug 13 2019, 5:32 PM · Restricted Project

Aug 2 2019

ThomasRaoux added a comment to D65424: [Packetizer] Increase the size of DFAInput bitfield to allow up to 32 units.

This seems to hang when compiling HexagonInstrInfo.cpp.

Aug 2 2019, 12:46 AM · Restricted Project

Jul 29 2019

ThomasRaoux created D65424: [Packetizer] Increase the size of DFAInput bitfield to allow up to 32 units.
Jul 29 2019, 4:38 PM · Restricted Project