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Differential D125900

[AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir.
ClosedPublic

Authored by kosarev on May 18 2022, 9:10 AM.

Details

Reviewers
foad
alex-t
arsenm
Group Reviewers
Restricted Project
Commits
rG70ace420c1f0: [AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir.
Summary

Discovered with D125604.

Diff Detail

Event Timeline

kosarev created this revision.May 18 2022, 9:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 18 2022, 9:10 AM
Herald added subscribers: kerbowa, t-tye, tpr and 4 others. · View Herald Transcript
kosarev requested review of this revision.May 18 2022, 9:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 18 2022, 9:10 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
kosarev added reviewers: foad, alex-t, Restricted Project.May 18 2022, 9:11 AM
arsenm accepted this revision.May 18 2022, 9:12 AM
arsenm added a subscriber: arsenm.

LGTM, this kind of fix doesn't really need review

This revision is now accepted and ready to land.May 18 2022, 9:12 AM
Harbormaster completed remote builds in B165145: Diff 430407.May 18 2022, 9:54 AM
This revision was landed with ongoing or failed builds.May 19 2022, 3:23 AM
Closed by commit rG70ace420c1f0: [AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir. (authored by kosarev). · Explain Why
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rG70ace420c1f0: [AMDGPU][NFC] Fix FileCheck directives in phi-vgpr-input-moveimm.mir..

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
6 lines

Diff 430624

llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
--- ---
# GCN_LABEL: phi_moveimm_input # GCN-LABEL: name: phi_moveimm_input
# GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1 # GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
# GCN: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1 # GCN: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
name: phi_moveimm_input name: phi_moveimm_input
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
Show All 16 Linesbody: |
bb.3: bb.3:
successors: %bb.2 successors: %bb.2
%1:sreg_32 = COPY %0 %1:sreg_32 = COPY %0
S_BRANCH %bb.2 S_BRANCH %bb.2
... ...
--- ---
# GCN_LABEL: phi_moveimm_subreg_input # GCN-LABEL: name: phi_moveimm_subreg_input
# GCN-NOT: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1 # GCN-NOT: %{{[0-9]+}}:sreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
# GCN: %{{[0-9]+}}:vreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1 # GCN: %{{[0-9]+}}:vreg_64 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
name: phi_moveimm_subreg_input name: phi_moveimm_subreg_input
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
Show All 16 Linesbody: |
bb.3: bb.3:
successors: %bb.2 successors: %bb.2
undef %1.sub0:sreg_64 = COPY %0 undef %1.sub0:sreg_64 = COPY %0
S_BRANCH %bb.2 S_BRANCH %bb.2
... ...
--- ---
# GCN_LABEL: phi_moveimm_bad_opcode_input # GCN-LABEL: name: phi_moveimm_bad_opcode_input
# GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1 # GCN-NOT: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
# GCN: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1 # GCN: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
name: phi_moveimm_bad_opcode_input name: phi_moveimm_bad_opcode_input
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
liveins: $sgpr0, $sgpr1, $vgpr0 liveins: $sgpr0, $sgpr1, $vgpr0
Show All 20 Lines