Update @llvm.powi to handle different int sizes for the exponent

[bjope]

Summary

This can be seen as a follow up to commit 0ee439b705e82a4fe20e2,
that changed the second argument of powidf2, powisf2 and
powitf2 in compiler-rt from si_int to int. That was to align with
how those runtimes are defined in libgcc.
One thing that seem to have been missing in that patch was to make
sure that the rest of LLVM also handle that the argument now depends
on the size of int (not using the si_int machine mode for 32-bit).
When using builtin_powi for a target with 16-bit int clang crashed.
And when emitting libcalls to those rtlib functions, typically when
lowering @llvm.powi), the backend would always prepare the exponent
argument as an i32 which caused miscompiles when the rtlib was
compiled with 16-bit int.

The solution used here is to use an overloaded type for the second
argument in @llvm.powi. This way clang can use the "correct" type
when lowering __builtin_powi, and then later when emitting the libcall
it is assumed that the type used in @llvm.powi matches the rtlib
function.

One thing that needed some extra attention was that when vectorizing
calls several passes did not support that several arguments could
be overloaded in the intrinsics. This patch allows overload of a
scalar operand by adding hasVectorInstrinsicOverloadedScalarOpd, with
an entry for powi.

[bjope]

Ping!

[bjope]

Ping!

(This patch is now 1 month old, has a number of reviewers and 41 subscribers, but not a single comment yet. I believe that if you aren't comfortable with reviewing, then it is perfectly OK to remove yourself as reveiwer to let the author know that the original set of reviewers was wrong. But this "silent treatment" is really painful.)

[fhahn]

Probably would be good to split this up in separate LLVM/Clang parts. Do we need to auto-upgrade calls to llvm.powi?

llvm/docs/LangRef.rst

13280

Not sure about the sentence about the size of the exponent. It refers to int and __powi, both of which are not really defined in the LangRef and it is not clear to what they are referring to here.

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

573

Why just allow i32 and i16 here?

Could we restrict the supported offset types to i32 or smaller?

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

1

I don't think we can rely on any specific triple here. If a triple is needed it should be in a sub-directory.

[xbolva00]

This comment was removed by xbolva00.

[bjope]

llvm/docs/LangRef.rst

13280

I see your point. Maybe something like "The type of the exponent should match the libm implementation for a target that lower the intrinsic to such a libcall.". Or maybe I should just skip trying to say something about it here.

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

573

I think that i16 and i32 are the only sizes of "int" that are supported by any in-tree target. And people tend to get very upset if trying to generalize code outside the scope given by in-tree targets.

llvm/test/Transforms/InstCombine/pow-4.ll

4

Need to move these tests to a msp430 subdir.

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

1

Yes, right, I need to move this.

[bjope]

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

1

A bit surprised that there are several tests in test/Transform/InstCombine/ that use -mtriple without the test case being in a target specific subfolder. For example test/Transform/InstCombine/pow-1.ll is verifying 12 different mtriple variants (plus the default). Is that OK? How could one know if a target specific dir is needed when using -mtriple (unless doing some experiments with different targets-to-build settings)?

[bjope]

llvm/test/Transforms/InstCombine/pow-4.ll

4

Or maybe not. This actually works even with LLVM_TARGETS_TO_BUILD=Sparc, without being moved to a subdir (and the test ends up as PASSED rather than UNSUPPORTED). So this just follow how it is done for lots of other test cases that verify libcall support in InstCombine.

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

1

This actually works even with LLVM_TARGETS_TO_BUILD=Sparc, without being moved to a subdir (and the test ends up as PASSED rather than UNSUPPORTED). So so this just follow how things are done for lots of other test cases that verify libcall support in InstCombine, and moving it to a subdir with a requirement to include MSP430 in the build only limits the amount of configs when the test case is executed.

[xbolva00]

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

3

Precommit? And we dont need full copy of existings tests - 2-3 tests for 16bit int are anough.

[xbolva00]

What about IR backward compatibility?

[efriedma]

Seems reasonable. I'd like to see a test for autoupgrade; not sure if you need to make any code changes for that.

llvm/docs/LangRef.rst

13282

Maybe make this a bit more explicit: move the description of the exponent into a separate paragraph, and explicitly state "generally, the only exponent supported is the C type int".

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

581

This is missing a diagnostic for the exponent. We don't want to silently miscompile if someone uses an exponent that isn't supported by the target.

[bjope]

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

581

Not sure exactly what you suggest. Is that a general comment for all places in SelectionDAG where we may emit calls to RTLIB::POWI or what makes this SoftenFloatRes special?

If we end up using mismatching types in the call, wouldn't that being detected as ICE elsewhere? Only reason I made changes to this function in the first place was due to the historical assert above regarding the type of the exponent in FPOWI. Maybe I should just drop that assert instead? This is the only place where that is checked, but I figure that the SoftenFloatRes legalization is just one out of many places where FPOWI is legalized and lowered into libcalls to RTLIB::POWI.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

581

It's a general issue with emitting calls to RTLIB::POWI; the second parameter to the call has to have type "int", to match the definition in libgcc/compiler-rt. I guess there are a few other places that also emit calls to these functions.

If we end up using mismatching types in the call, wouldn't that being detected as ICE elsewhere?

In SelectionDAG, function/pointer types don't exist; the callee of a function call is just a integer. So we'd never detect mismatched types; we'd just silently emit a call using the wrong calling convention.

[bjope]

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

581

One interesting thing when trying to add checks verifying that DAG.getLibInfo().getIntSize() == Node->getOperand(1 + Offset).getValueType().getSizeInBits()) in LegalizeDAG some RISCV (64-bit) test cases fail. Looks like type legalization is promoting the exponent by replacing

    t5: i64,ch = CopyFromReg t0, Register:i64 %1
  t6: i32 = truncate t5
t7: f32 = fpowi t3, t6

by

    t5: i64,ch = CopyFromReg t0, Register:i64 %1
  t13: i64 = sign_extend_inreg t5, ValueType:ch:i32
t7: f32 = fpowi t3, t13

I kind of suspect that promoting the exponent for FPOWI always would be incorrect, if the idea is that the type always should match with sizeof(int).

In this case RISCV would lower the fpowi to a libcall like this

    t5: i64,ch = CopyFromReg t0, Register:i64 %1
  t13: i64 = sign_extend_inreg t5, ValueType:ch:i32
t20: ch,glue = CopyToReg t18, Register:i64 $x11, t13, t18:1
t23: ch,glue = RISCVISD::CALL t20, TargetExternalSymbol:i64'__powisf2' [TF=2], Register:i64 $x10, Register:i64 $x11, RegisterMask:Untyped, t20:1

using a 64-bit argument for the call, while the callee expects a 32-bit int. Depending on the calling conventions for RISCV64 I suppose this might work by coincidence, or it is a bad miscompile.

Not sure exactly how to deal with that when considering this patch. I was kind of aiming at fixing problems for 16-bit targets. Maybe we need to deal with DAGTypeLegalizer::PromoteIntOp_FPOWI first, turning it into a fault situation. And to do that one need to handle FPOWI for RISCV in some sort of way to make the 32-bit exponent legal first?

[efriedma]

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

581

We probably end up getting lucky due to the RISCV calling convention... but it's ugly.

I think the right solution here is to force type legalization to generate the call (when we try to legalize the integer operand), instead of waiting for LegalizeDAG. That should allow the call lowering code to use the right calling convention.

[bjope]

Addressed review comments (and rebased). This includes:

• Add diagnostics for wrong sized exponent when lowering FPOWI to libcall.
• For the above to work this patch now depends on D102918 to avoid that RISCV (64-bit) is promoting the exponent in FPOWI in a way that makes the operation undef.
• Patch now also depends on pre-commit of a test case in D102919.
• Updated the langref part about llvm.powi.
• Updated the ISelOpcodes description about undefined exponent types in FPOWI.
• Added auto-upgrade tests for llvm.powi.

[bjope]

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

3

I've pre-commited the tests now. Remove some of the tests (mainly the ones related to i64. But I think most of the others are relevant as regression test to see that we get what is expected for the different scenarios also with 16-bit int.

[bjope]

Rebased. This now depends on D102950 rather than D102918.

[bjope]

ping!

[efriedma]

LGTM

[bjope]

In D99439#2823338, @efriedma wrote:

LGTM

Thanks!

[xbolva00]

Just to mention, 'llvm.experimental.constrained.powi' uses i32. Probably not a big deal, just small inconsistency with llvm.powi.

clang/lib/CodeGen/CGBuiltin.cpp

 //===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
case Builtin::BI__builtin_unreachable: {
     // We do need to preserve an insertion point.
     EmitBlock(createBasicBlock("unreachable.cont"));
 
     return RValue::get(nullptr);
   }
 
   case Builtin::BI__builtin_powi:
   case Builtin::BI__builtin_powif:
-  case Builtin::BI__builtin_powil:
-    return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(
-        *this, E, Intrinsic::powi, Intrinsic::experimental_constrained_powi));
+  case Builtin::BI__builtin_powil: {
+    llvm::Value *Src0 = EmitScalarExpr(E->getArg(0));
+    llvm::Value *Src1 = EmitScalarExpr(E->getArg(1));
+
+    if (Builder.getIsFPConstrained()) {
+      CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);
+      Function *F = CGM.getIntrinsic(Intrinsic::experimental_constrained_powi,
+                                     Src0->getType());
+      return RValue::get(Builder.CreateConstrainedFPCall(F, { Src0, Src1 }));
+    }
 
+    Function *F = CGM.getIntrinsic(Intrinsic::powi,
+                                   { Src0->getType(), Src1->getType() });
+    return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
+  }
   case Builtin::BI__builtin_isgreater:
   case Builtin::BI__builtin_isgreaterequal:
   case Builtin::BI__builtin_isless:
   case Builtin::BI__builtin_islessequal:
   case Builtin::BI__builtin_islessgreater:
   case Builtin::BI__builtin_isunordered: {
     // Ordered comparisons: we know the arguments to these are matching scalar
     // floating point values.

clang/test/CodeGen/avr-builtins.c

 // CHECK: i32 @llvm.bswap.i32(i32
 
 unsigned long long byteswap64(unsigned long long x) {
     return __builtin_bswap64(x);
 }
 
 // CHECK: define{{.*}} i64 @byteswap64
 // CHECK: i64 @llvm.bswap.i64(i64
+
+double powi(double x, int y) {
+  return __builtin_powi(x, y);
+}
+
+// CHECK: define{{.*}} float @powi
+// CHECK: float @llvm.powi.f32.i16(float %0, i16 %1)
+
+float powif(float x, int y) {
+    return __builtin_powif(x, y);
+}
+
+// CHECK: define{{.*}} float @powif
+// CHECK: float @llvm.powi.f32.i16(float %0, i16 %1)
+
+long double powil(long double x, int y) {
+    return __builtin_powil(x, y);
+}
+
+// CHECK: define{{.*}} float @powil
+// CHECK: float @llvm.powi.f32.i16(float %0, i16 %1)

clang/test/CodeGen/math-builtins.c

 // NO__ERRNO: declare fp128 @llvm.pow.f128(fp128, fp128) [[READNONE_INTRINSIC]]
 // HAS_ERRNO: declare double @pow(double, double) [[NOT_READNONE]]
 // HAS_ERRNO: declare float @powf(float, float) [[NOT_READNONE]]
 // HAS_ERRNO: declare x86_fp80 @powl(x86_fp80, x86_fp80) [[NOT_READNONE]]
 // HAS_ERRNO: declare fp128 @powf128(fp128, fp128) [[NOT_READNONE]]
 
   __builtin_powi(f,f);        __builtin_powif(f,f);       __builtin_powil(f,f);
 
-// NO__ERRNO: declare double @llvm.powi.f64(double, i32) [[READNONE_INTRINSIC]]
-// NO__ERRNO: declare float @llvm.powi.f32(float, i32) [[READNONE_INTRINSIC]]
-// NO__ERRNO: declare x86_fp80 @llvm.powi.f80(x86_fp80, i32) [[READNONE_INTRINSIC]]
-// HAS_ERRNO: declare double @llvm.powi.f64(double, i32) [[READNONE_INTRINSIC]]
-// HAS_ERRNO: declare float @llvm.powi.f32(float, i32) [[READNONE_INTRINSIC]]
-// HAS_ERRNO: declare x86_fp80 @llvm.powi.f80(x86_fp80, i32) [[READNONE_INTRINSIC]]
+// NO__ERRNO: declare double @llvm.powi.f64.i32(double, i32) [[READNONE_INTRINSIC]]
+// NO__ERRNO: declare float @llvm.powi.f32.i32(float, i32) [[READNONE_INTRINSIC]]
+// NO__ERRNO: declare x86_fp80 @llvm.powi.f80.i32(x86_fp80, i32) [[READNONE_INTRINSIC]]
+// HAS_ERRNO: declare double @llvm.powi.f64.i32(double, i32) [[READNONE_INTRINSIC]]
+// HAS_ERRNO: declare float @llvm.powi.f32.i32(float, i32) [[READNONE_INTRINSIC]]
+// HAS_ERRNO: declare x86_fp80 @llvm.powi.f80.i32(x86_fp80, i32) [[READNONE_INTRINSIC]]
 
   /* math */
   __builtin_acos(f);       __builtin_acosf(f);      __builtin_acosl(f); __builtin_acosf128(f);
 
 // NO__ERRNO: declare double @acos(double) [[READNONE]]
 // NO__ERRNO: declare float @acosf(float) [[READNONE]]
 // NO__ERRNO: declare x86_fp80 @acosl(x86_fp80) [[READNONE]]
 // NO__ERRNO: declare fp128 @acosf128(fp128) [[READNONE]]

clang/test/CodeGen/msp430-builtins.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple msp430-unknown-unknown -O3 -emit-llvm -o- %s | FileCheck %s
+// REQUIRES: msp430-registered-target
+
+_Static_assert(sizeof(int) == 2, "Assumption failed");
+_Static_assert(sizeof(long) == 4, "Assumption failed");
+_Static_assert(sizeof(long long) == 8, "Assumption failed");
+_Static_assert(sizeof(float) == 4, "Assumption failed");
+_Static_assert(sizeof(double) == 8, "Assumption failed");
+_Static_assert(sizeof(long double) == 8, "Assumption failed");
+
+// CHECK-LABEL: @powif(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call float @llvm.powi.f32.i16(float [[X:%.*]], i16 [[Y:%.*]])
+// CHECK-NEXT:    ret float [[TMP0]]
+//
+float powif(float x, int y) {
+    return __builtin_powif(x, y);
+}
+
+// CHECK-LABEL: @powi(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call double @llvm.powi.f64.i16(double [[X:%.*]], i16 [[Y:%.*]])
+// CHECK-NEXT:    ret double [[TMP0]]
+//
+double powi(double x, int y) {
+  return __builtin_powi(x, y);
+}
+
+// CHECK-LABEL: @powil(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call double @llvm.powi.f64.i16(double [[X:%.*]], i16 [[Y:%.*]])
+// CHECK-NEXT:    ret double [[TMP0]]
+//
+long double powil(long double x, int y) {
+    return __builtin_powil(x, y);
+}

llvm/docs/LangRef.rst

 
 '``llvm.powi.*``' Intrinsic
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Syntax:
 """""""
 
 This is an overloaded intrinsic. You can use ``llvm.powi`` on any
-floating-point or vector of floating-point type. Not all targets support
+floating-point or vector of floating-point type. The type of the exponent
+should typically match the size of ``int``, at least when the intrinsic maps
+to one of the ``__powi*`` functions in compiler-rt. Not all targets support
 all types however.
 
 ::
 
-      declare float     @llvm.powi.f32(float  %Val, i32 %power)
-      declare double    @llvm.powi.f64(double %Val, i32 %power)
-      declare x86_fp80  @llvm.powi.f80(x86_fp80  %Val, i32 %power)
-      declare fp128     @llvm.powi.f128(fp128 %Val, i32 %power)
-      declare ppc_fp128 @llvm.powi.ppcf128(ppc_fp128  %Val, i32 %power)
+      declare float     @llvm.powi.f32.i32(float  %Val, i32 %power)
+      declare double    @llvm.powi.f64.i16(double %Val, i16 %power)
+      declare x86_fp80  @llvm.powi.f80.i32(x86_fp80  %Val, i32 %power)
+      declare fp128     @llvm.powi.f128.i32(fp128 %Val, i32 %power)
+      declare ppc_fp128 @llvm.powi.ppcf128.i32(ppc_fp128  %Val, i32 %power)
 
 Overview:
 """""""""
 
 The '``llvm.powi.*``' intrinsics return the first operand raised to the
 specified (positive or negative) power. The order of evaluation of
 multiplications is not defined. When a vector of floating-point type is
 used, the second argument remains a scalar integer value.

llvm/include/llvm/Analysis/VectorUtils.h

 //===- llvm/Analysis/VectorUtils.h - Vector utilities -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 /// This method returns true if the intrinsic's argument types are all scalars
 /// for the scalar form of the intrinsic and all vectors (or scalars handled by
 /// hasVectorInstrinsicScalarOpd) for the vector form of the intrinsic.
 bool isTriviallyVectorizable(Intrinsic::ID ID);
 
 /// Identifies if the vector form of the intrinsic has a scalar operand.
 bool hasVectorInstrinsicScalarOpd(Intrinsic::ID ID, unsigned ScalarOpdIdx);
 
+/// Identifies if the vector form of the intrinsic has a scalar operand that has
+/// an overloaded type.
+bool hasVectorInstrinsicOverloadedScalarOpd(Intrinsic::ID ID,
+                                            unsigned ScalarOpdIdx);
+
 /// Returns intrinsic ID for call.
 /// For the input call instruction it finds mapping intrinsic and returns
 /// its intrinsic ID, in case it does not found it return not_intrinsic.
 Intrinsic::ID getVectorIntrinsicIDForCall(const CallInst *CI,
                                           const TargetLibraryInfo *TLI);
 
 /// Find the operand of the GEP that should be checked for consecutive
 /// stores. This ignores trailing indices that have no effect on the final

llvm/include/llvm/IR/Intrinsics.td

let IntrProperties = [IntrNoMem, IntrSpeculatable, IntrWillReturn] in {
   def int_fmuladd : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>,
                                LLVMMatchType<0>]>;
 
   // These functions do not read memory, but are sensitive to the
   // rounding mode. LLVM purposely does not model changes to the FP
   // environment so they can be treated as readnone.
   def int_sqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
-  def int_powi : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>;
+  def int_powi : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_anyint_ty]>;
   def int_sin  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_cos  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_pow  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
                            [LLVMMatchType<0>, LLVMMatchType<0>]>;
   def int_log  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_log10: DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_log2 : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_exp  : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;

llvm/lib/Analysis/VectorUtils.cpp

 //===----------- VectorUtils.cpp - Vectorizer utility functions -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool llvm::hasVectorInstrinsicScalarOpd(Intrinsic::ID ID,
   case Intrinsic::umul_fix:
   case Intrinsic::umul_fix_sat:
     return (ScalarOpdIdx == 2);
   default:
     return false;
   }
 }
 
+bool llvm::hasVectorInstrinsicOverloadedScalarOpd(Intrinsic::ID ID,
+                                                  unsigned ScalarOpdIdx) {
+  switch (ID) {
+  case Intrinsic::powi:
+    return (ScalarOpdIdx == 1);
+  default:
+    return false;
+  }
+}
+
 /// Returns intrinsic ID for call.
 /// For the input call instruction it finds mapping intrinsic and returns
 /// its ID, in case it does not found it return not_intrinsic.
 Intrinsic::ID llvm::getVectorIntrinsicIDForCall(const CallInst *CI,
                                                 const TargetLibraryInfo *TLI) {
   Intrinsic::ID ID = getIntrinsicForCallSite(*CI, TLI);
   if (ID == Intrinsic::not_intrinsic)
     return Intrinsic::not_intrinsic;

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

 //===-------- LegalizeFloatTypes.cpp - Legalization of float types --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
                                                RTLIB::POW_F80,
                                                RTLIB::POW_F128,
                                                RTLIB::POW_PPCF128));
 }
 
 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
   bool IsStrict = N->isStrictFPOpcode();
   unsigned Offset = IsStrict ? 1 : 0;
-  assert(N->getOperand(1 + Offset).getValueType() == MVT::i32 &&
+  assert((N->getOperand(1 + Offset).getValueType() == MVT::i16 ||
+          N->getOperand(1 + Offset).getValueType() == MVT::i32) &&
          "Unsupported power type!");
   RTLIB::Libcall LC = GetFPLibCall(N->getValueType(0),
                                    RTLIB::POWI_F32,
                                    RTLIB::POWI_F64,
                                    RTLIB::POWI_F80,
                                    RTLIB::POWI_F128,
                                    RTLIB::POWI_PPCF128);
   if (!TLI.getLibcallName(LC)) {
     // Some targets don't have a powi libcall; use pow instead.
     // FIXME: Implement this if some target needs it.
     DAG.getContext()->emitError("Don't know how to soften fpowi to fpow");
     return DAG.getUNDEF(N->getValueType(0));
   }
 
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));

llvm/lib/Target/Mips/Mips16HardFloat.cpp

 //===- Mips16HardFloat.cpp for Mips16 Hard Float --------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static const char *const IntrinsicInline[] = {
   "llvm.exp2.f32", "llvm.exp2.f64",
   "llvm.fabs.f32", "llvm.fabs.f64",
   "llvm.floor.f32", "llvm.floor.f64",
   "llvm.fma.f32", "llvm.fma.f64",
   "llvm.log.f32", "llvm.log.f64",
   "llvm.log10.f32", "llvm.log10.f64",
   "llvm.nearbyint.f32", "llvm.nearbyint.f64",
   "llvm.pow.f32", "llvm.pow.f64",
-  "llvm.powi.f32", "llvm.powi.f64",
+  "llvm.powi.f32.i32", "llvm.powi.f64.i32",
   "llvm.rint.f32", "llvm.rint.f64",
   "llvm.round.f32", "llvm.round.f64",
   "llvm.sin.f32", "llvm.sin.f64",
   "llvm.sqrt.f32", "llvm.sqrt.f64",
   "llvm.trunc.f32", "llvm.trunc.f64",
 };
 
 static bool isIntrinsicInline(Function *F) {

llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

 //===- InstCombineMulDivRem.cpp -------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static Instruction *foldFDivPowDivisor(BinaryOperator &I,
   // for better canonicalization and optimization than fdiv.
   Intrinsic::ID IID = II->getIntrinsicID();
   SmallVector<Value *> Args;
   switch (IID) {
   case Intrinsic::pow:
     Args.push_back(II->getArgOperand(0));
     Args.push_back(Builder.CreateFNegFMF(II->getArgOperand(1), &I));
     break;
-  case Intrinsic::powi:
+  case Intrinsic::powi: {
     // Require 'ninf' assuming that makes powi(X, -INT_MIN) acceptable.
     // That is, X ** (huge negative number) is 0.0, ~1.0, or INF and so
     // dividing by that is INF, ~1.0, or 0.0. Code that uses powi allows
     // non-standard results, so this corner case should be acceptable if the
     // code rules out INF values.
     if (!I.hasNoInfs())
       return nullptr;
     Args.push_back(II->getArgOperand(0));
     Args.push_back(Builder.CreateNeg(II->getArgOperand(1)));
-    break;
+    Type *Tys[] = {I.getType(), II->getArgOperand(1)->getType()};
+    Value *Pow = Builder.CreateIntrinsic(IID, Tys, Args, &I);
+    return BinaryOperator::CreateFMulFMF(Op0, Pow, &I);
+  }
   case Intrinsic::exp:
   case Intrinsic::exp2:
     Args.push_back(Builder.CreateFNegFMF(II->getArgOperand(0), &I));
     break;
   default:
     return nullptr;
   }
   Value *Pow = Builder.CreateIntrinsic(IID, I.getType(), Args, &I);

llvm/lib/Transforms/Scalar/Scalarizer.cpp

 //===- Scalarizer.cpp - Scalarize vector operations -----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 static bool isTriviallyScalariable(Intrinsic::ID ID) {
   return isTriviallyVectorizable(ID);
 }
 
 // All of the current scalarizable intrinsics only have one mangled type.
 static Function *getScalarIntrinsicDeclaration(Module *M,
                                                Intrinsic::ID ID,
-                                               VectorType *Ty) {
-  return Intrinsic::getDeclaration(M, ID, { Ty->getScalarType() });
+                                               ArrayRef<Type*> Tys) {
+  return Intrinsic::getDeclaration(M, ID, Tys);
 }
 
 /// If a call to a vector typed intrinsic function, split into a scalar call per
 /// element if possible for the intrinsic.
 bool ScalarizerVisitor::splitCall(CallInst &CI) {
   VectorType *VT = dyn_cast<VectorType>(CI.getType());
   if (!VT)
     return false;
bool ScalarizerVisitor::splitCall(CallInst &CI) {
   unsigned NumElems = cast<FixedVectorType>(VT)->getNumElements();
   unsigned NumArgs = CI.getNumArgOperands();
 
   ValueVector ScalarOperands(NumArgs);
   SmallVector<Scatterer, 8> Scattered(NumArgs);
 
   Scattered.resize(NumArgs);
 
+  SmallVector<llvm::Type *, 3> Tys;
+  Tys.push_back(VT->getScalarType());
+
   // Assumes that any vector type has the same number of elements as the return
   // vector type, which is true for all current intrinsics.
   for (unsigned I = 0; I != NumArgs; ++I) {
     Value *OpI = CI.getOperand(I);
     if (OpI->getType()->isVectorTy()) {
       Scattered[I] = scatter(&CI, OpI);
       assert(Scattered[I].size() == NumElems && "mismatched call operands");
     } else {
       ScalarOperands[I] = OpI;
+      if (hasVectorInstrinsicOverloadedScalarOpd(ID, I))
+        Tys.push_back(OpI->getType());
     }
   }
 
   ValueVector Res(NumElems);
   ValueVector ScalarCallOps(NumArgs);
 
-  Function *NewIntrin = getScalarIntrinsicDeclaration(F->getParent(), ID, VT);
+  Function *NewIntrin = getScalarIntrinsicDeclaration(F->getParent(), ID, Tys);
   IRBuilder<> Builder(&CI);
 
   // Perform actual scalarization, taking care to preserve any scalar operands.
   for (unsigned Elem = 0; Elem < NumElems; ++Elem) {
     ScalarCallOps.clear();
 
     for (unsigned J = 0; J != NumArgs; ++J) {
       if (hasVectorInstrinsicScalarOpd(ID, J))

llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp

 //===------ SimplifyLibCalls.cpp - Library calls simplifier ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (ExpoF->isNegative())
     Sqrt = B.CreateFDiv(ConstantFP::get(Ty, 1.0), Sqrt, "reciprocal");
 
   return Sqrt;
 }
 
 static Value *createPowWithIntegerExponent(Value *Base, Value *Expo, Module *M,
                                            IRBuilderBase &B) {
   Value *Args[] = {Base, Expo};
-  Function *F = Intrinsic::getDeclaration(M, Intrinsic::powi, Base->getType());
+  Type *Types[] = {Base->getType(), Expo->getType()};
+  Function *F = Intrinsic::getDeclaration(M, Intrinsic::powi, Types);
   return B.CreateCall(F, Args);
 }
 
 Value *LibCallSimplifier::optimizePow(CallInst *Pow, IRBuilderBase &B) {
   Value *Base = Pow->getArgOperand(0);
   Value *Expo = Pow->getArgOperand(1);
   Function *Callee = Pow->getCalledFunction();
   StringRef Name = Callee->getName();
if (ExpoA < LimF) {
 
       // If the exponent is negative, then get the reciprocal.
       if (ExpoF->isNegative())
         FMul = B.CreateFDiv(ConstantFP::get(Ty, 1.0), FMul, "reciprocal");
 
       return FMul;
     }
 
-    APSInt IntExpo(32, /*isUnsigned=*/false);
+    APSInt IntExpo(TLI->getIntSize(), /*isUnsigned=*/false);
     // powf(x, n) -> powi(x, n) if n is a constant signed integer value
     if (ExpoF->isInteger() &&
         ExpoF->convertToInteger(IntExpo, APFloat::rmTowardZero, &Ignored) ==
             APFloat::opOK) {
       return createPowWithIntegerExponent(
-          Base, ConstantInt::get(B.getInt32Ty(), IntExpo), M, B);
+          Base, ConstantInt::get(B.getIntNTy(TLI->getIntSize()), IntExpo), M, B);
     }
   }
 
   // powf(x, itofp(y)) -> powi(x, y)
   if (AllowApprox && (isa<SIToFPInst>(Expo) || isa<UIToFPInst>(Expo))) {
-    if (Value *ExpoI = getIntToFPVal(Expo, B, 32))
+    if (Value *ExpoI = getIntToFPVal(Expo, B, TLI->getIntSize()))
       return createPowWithIntegerExponent(Base, ExpoI, M, B);
   }
 
   // Shrink pow() to powf() if the arguments are single precision,
   // unless the result is expected to be double precision.
   if (UnsafeFPShrink && Name == TLI->getName(LibFunc_pow) &&
       hasFloatVersion(Name)) {
     if (Value *Shrunk = optimizeBinaryDoubleFP(Pow, B, true))

llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

 //===- LoopVectorize.cpp - A Loop Vectorizer ------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
void InnerLoopVectorizer::widenCallInstruction(CallInst &I, VPValue *Def,
   InstructionCost IntrinsicCost = ID ? Cost->getVectorIntrinsicCost(CI, VF) : 0;
   bool UseVectorIntrinsic = ID && IntrinsicCost <= CallCost;
   assert((UseVectorIntrinsic || !NeedToScalarize) &&
          "Instruction should be scalarized elsewhere.");
   assert(IntrinsicCost.isValid() && CallCost.isValid() &&
          "Cannot have invalid costs while widening");
 
   for (unsigned Part = 0; Part < UF; ++Part) {
+    SmallVector<Type *, 2> TysForDecl = {CI->getType()};
     SmallVector<Value *, 4> Args;
     for (auto &I : enumerate(ArgOperands.operands())) {
       // Some intrinsics have a scalar argument - don't replace it with a
       // vector.
       Value *Arg;
       if (!UseVectorIntrinsic || !hasVectorInstrinsicScalarOpd(ID, I.index()))
         Arg = State.get(I.value(), Part);
-      else
+      else {
         Arg = State.get(I.value(), VPIteration(0, 0));
+        if (hasVectorInstrinsicOverloadedScalarOpd(ID, I.index()))
+          TysForDecl.push_back(Arg->getType());
+      }
       Args.push_back(Arg);
     }
 
     Function *VectorF;
     if (UseVectorIntrinsic) {
       // Use vector version of the intrinsic.
-      Type *TysForDecl[] = {CI->getType()};
       if (VF.isVector())
         TysForDecl[0] = VectorType::get(CI->getType()->getScalarType(), VF);
       VectorF = Intrinsic::getDeclaration(M, ID, TysForDecl);
       assert(VectorF && "Can't retrieve vector intrinsic.");
     } else {
       // Use vector version of the function call.
       const VFShape Shape = VFShape::get(*CI, VF, false /*HasGlobalPred*/);
 #ifndef NDEBUG

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

 //===- SLPVectorizer.cpp - A bottom up SLP Vectorizer ---------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
case Instruction::Call: {
       Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI);
 
       auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI);
       bool UseIntrinsic = ID != Intrinsic::not_intrinsic &&
                           VecCallCosts.first <= VecCallCosts.second;
 
       Value *ScalarArg = nullptr;
       std::vector<Value *> OpVecs;
+      SmallVector<Type *, 2> TysForDecl =
+          {FixedVectorType::get(CI->getType(), E->Scalars.size())};
       for (int j = 0, e = CI->getNumArgOperands(); j < e; ++j) {
         ValueList OpVL;
         // Some intrinsics have scalar arguments. This argument should not be
         // vectorized.
         if (UseIntrinsic && hasVectorInstrinsicScalarOpd(IID, j)) {
           CallInst *CEI = cast<CallInst>(VL0);
           ScalarArg = CEI->getArgOperand(j);
           OpVecs.push_back(CEI->getArgOperand(j));
+          if (hasVectorInstrinsicOverloadedScalarOpd(IID, j))
+            TysForDecl.push_back(ScalarArg->getType());
           continue;
         }
 
         Value *OpVec = vectorizeTree(E->getOperand(j));
         LLVM_DEBUG(dbgs() << "SLP: OpVec[" << j << "]: " << *OpVec << "\n");
         OpVecs.push_back(OpVec);
       }
 
       Function *CF;
       if (!UseIntrinsic) {
         VFShape Shape =
             VFShape::get(*CI, ElementCount::getFixed(static_cast<unsigned>(
                                   VecTy->getNumElements())),
                          false /*HasGlobalPred*/);
         CF = VFDatabase(*CI).getVectorizedFunction(Shape);
       } else {
-        Type *Tys[] = {FixedVectorType::get(CI->getType(), E->Scalars.size())};
-        CF = Intrinsic::getDeclaration(F->getParent(), ID, Tys);
+        CF = Intrinsic::getDeclaration(F->getParent(), ID, TysForDecl);
       }
 
       SmallVector<OperandBundleDef, 1> OpBundles;
       CI->getOperandBundlesAsDefs(OpBundles);
       Value *V = Builder.CreateCall(CF, OpVecs, OpBundles);
 
       // The scalar argument uses an in-tree scalar so we add the new vectorized
       // call to ExternalUses list to make sure that an extract will be

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $s1
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOW [[LHS]], [[RHS]]
 ; CHECK: $s0 = COPY [[RES]]
   %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.pow.f32(float %l, float %r)
   ret float %res
 }
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 define float @test_powi_intrin(float %l, i32 %r) {
 ; CHECK-LABEL: name: test_powi_intrin
 ; CHECK: [[LHS:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RHS:%[0-9]+]]:_(s32) = COPY $w0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[LHS]], [[RHS]]
 ; CHECK: $s0 = COPY [[RES]]
-  %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.powi.f32(float %l, i32 %r)
+  %res = call nnan ninf nsz arcp contract afn reassoc float @llvm.powi.f32.i32(float %l, i32 %r)
   ret float %res
 }
 
 declare float @llvm.fma.f32(float, float, float)
 define float @test_fma_intrin(float %a, float %b, float %c) {
 ; CHECK-LABEL: name: test_fma_intrin
 ; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[B:%[0-9]+]]:_(s32) = COPY $s1

llvm/test/CodeGen/AArch64/arm64-vfloatintrinsics.ll

define %v4f16 @test_v4f16.sqrt(%v4f16 %a) {
   ; GISEL-FP16-NEXT:      ret
   %1 = call %v4f16 @llvm.sqrt.v4f16(%v4f16 %a)
   ret %v4f16 %1
 }
 define %v4f16 @test_v4f16.powi(%v4f16 %a, i32 %b) {
   ; This operation is expanded, whether with or without +fullfp16.
   ; CHECK-LABEL:   test_v4f16.powi:
   ; CHECK-COUNT-4: bl __powi
-  %1 = call %v4f16 @llvm.powi.v4f16(%v4f16 %a, i32 %b)
+  %1 = call %v4f16 @llvm.powi.v4f16.i32(%v4f16 %a, i32 %b)
   ret %v4f16 %1
 }
 
 ; FALLBACK-NOT: remark{{.*}}test_v4f16.sin
 define %v4f16 @test_v4f16.sin(%v4f16 %a) {
   ; This operation is expanded, whether with or without +fullfp16.
   ; CHECK-LABEL:   test_v4f16.sin:
   ; CHECK-COUNT-4: bl sinf
define %v4f16 @test_v4f16.roundeven(%v4f16 %a) {
   ; GISEL-FP16-NOT:       fcvt
   ; GISEL-FP16:           frintn.4h
   ; GISEL-FP16-NEXT:      ret
   %1 =  call %v4f16 @llvm.roundeven.v4f16(%v4f16 %a)
   ret %v4f16 %1
 }
 
 declare %v4f16 @llvm.sqrt.v4f16(%v4f16) #0
-declare %v4f16 @llvm.powi.v4f16(%v4f16, i32) #0
+declare %v4f16 @llvm.powi.v4f16.i32(%v4f16, i32) #0
 declare %v4f16 @llvm.sin.v4f16(%v4f16) #0
 declare %v4f16 @llvm.cos.v4f16(%v4f16) #0
 declare %v4f16 @llvm.pow.v4f16(%v4f16, %v4f16) #0
 declare %v4f16 @llvm.exp.v4f16(%v4f16) #0
 declare %v4f16 @llvm.exp2.v4f16(%v4f16) #0
 declare %v4f16 @llvm.log.v4f16(%v4f16) #0
 declare %v4f16 @llvm.log10.v4f16(%v4f16) #0
 declare %v4f16 @llvm.log2.v4f16(%v4f16) #0
define %v8f16 @test_v8f16.sqrt(%v8f16 %a) {
   ret %v8f16 %1
 }
 define %v8f16 @test_v8f16.powi(%v8f16 %a, i32 %b) {
   ; This operation is expanded, whether with or without +fullfp16.
   ; CHECK-LABEL:   test_v8f16.powi:
   ; CHECK-COUNT-8: bl __powi
   ; GISEL-LABEL:   test_v8f16.powi:
   ; GISEL-COUNT-8: bl __powi
-  %1 = call %v8f16 @llvm.powi.v8f16(%v8f16 %a, i32 %b)
+  %1 = call %v8f16 @llvm.powi.v8f16.i32(%v8f16 %a, i32 %b)
   ret %v8f16 %1
 }
 
 ; FALLBACK-NOT: remark{{.*}}test_v8f16.sin
 define %v8f16 @test_v8f16.sin(%v8f16 %a) {
   ; This operation is expanded, whether with or without +fullfp16.
   ; CHECK-LABEL:   test_v8f16.sin:
   ; CHECK-COUNT-8: bl sinf
define %v8f16 @test_v8f16.roundeven(%v8f16 %a) {
   ; GISEL-FP16-NOT:       fcvt
   ; GISEL-FP16:           frintn.8h
   ; GISEL-FP16-NEXT:      ret
   %1 =  call %v8f16 @llvm.roundeven.v8f16(%v8f16 %a)
   ret %v8f16 %1
 }
 
 declare %v8f16 @llvm.sqrt.v8f16(%v8f16) #0
-declare %v8f16 @llvm.powi.v8f16(%v8f16, i32) #0
+declare %v8f16 @llvm.powi.v8f16.i32(%v8f16, i32) #0
 declare %v8f16 @llvm.sin.v8f16(%v8f16) #0
 declare %v8f16 @llvm.cos.v8f16(%v8f16) #0
 declare %v8f16 @llvm.pow.v8f16(%v8f16, %v8f16) #0
 declare %v8f16 @llvm.exp.v8f16(%v8f16) #0
 declare %v8f16 @llvm.exp2.v8f16(%v8f16) #0
 declare %v8f16 @llvm.log.v8f16(%v8f16) #0
 declare %v8f16 @llvm.log10.v8f16(%v8f16) #0
 declare %v8f16 @llvm.log2.v8f16(%v8f16) #0
define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
   ; CHECK: fsqrt.2s
   ; GISEL: fsqrt.2s
   %1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
 ; CHECK: test_v2f32.powi:
 define %v2f32 @test_v2f32.powi(%v2f32 %a, i32 %b) {
   ; CHECK: pow
-  %1 = call %v2f32 @llvm.powi.v2f32(%v2f32 %a, i32 %b)
+  %1 = call %v2f32 @llvm.powi.v2f32.i32(%v2f32 %a, i32 %b)
   ret %v2f32 %1
 }
 
 ; FALLBACK-NOT: remark{{.*}}test_v2f32.sin
 ; CHECK: test_v2f32.sin:
 define %v2f32 @test_v2f32.sin(%v2f32 %a) {
   ; CHECK: sin
   ; GISEL: sin

 define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
   ; CHECK: frinti.2s
   ; GISEL: frinti.2s
   %1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
 
 declare %v2f32 @llvm.sqrt.v2f32(%v2f32) #0
-declare %v2f32 @llvm.powi.v2f32(%v2f32, i32) #0
+declare %v2f32 @llvm.powi.v2f32.i32(%v2f32, i32) #0
 declare %v2f32 @llvm.sin.v2f32(%v2f32) #0
 declare %v2f32 @llvm.cos.v2f32(%v2f32) #0
 declare %v2f32 @llvm.pow.v2f32(%v2f32, %v2f32) #0
 declare %v2f32 @llvm.exp.v2f32(%v2f32) #0
 declare %v2f32 @llvm.exp2.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log10.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log2.v2f32(%v2f32) #0
define %v4f32 @test_v4f32.sqrt(%v4f32 %a) {
   ; CHECK: fsqrt.4s
   ; GISEL: fsqrt.4s
   %1 = call %v4f32 @llvm.sqrt.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
 ; CHECK: test_v4f32.powi:
 define %v4f32 @test_v4f32.powi(%v4f32 %a, i32 %b) {
   ; CHECK: pow
-  %1 = call %v4f32 @llvm.powi.v4f32(%v4f32 %a, i32 %b)
+  %1 = call %v4f32 @llvm.powi.v4f32.i32(%v4f32 %a, i32 %b)
   ret %v4f32 %1
 }
 
 ; FALLBACK-NOT: remark{{.*}}test_v4f32.sin
 ; CHECK: test_v4f32.sin:
 define %v4f32 @test_v4f32.sin(%v4f32 %a) {
   ; CHECK: sin
   ; GISEL: sin

 define %v4f32 @test_v4f32.nearbyint(%v4f32 %a) {
   ; CHECK: frinti.4s
   ; GISEL: frinti.4s
   %1 = call %v4f32 @llvm.nearbyint.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
 
 declare %v4f32 @llvm.sqrt.v4f32(%v4f32) #0
-declare %v4f32 @llvm.powi.v4f32(%v4f32, i32) #0
+declare %v4f32 @llvm.powi.v4f32.i32(%v4f32, i32) #0
 declare %v4f32 @llvm.sin.v4f32(%v4f32) #0
 declare %v4f32 @llvm.cos.v4f32(%v4f32) #0
 declare %v4f32 @llvm.pow.v4f32(%v4f32, %v4f32) #0
 declare %v4f32 @llvm.exp.v4f32(%v4f32) #0
 declare %v4f32 @llvm.exp2.v4f32(%v4f32) #0
 declare %v4f32 @llvm.log.v4f32(%v4f32) #0
 declare %v4f32 @llvm.log10.v4f32(%v4f32) #0
 declare %v4f32 @llvm.log2.v4f32(%v4f32) #0
define %v2f64 @test_v2f64.sqrt(%v2f64 %a) {
   ; CHECK: fsqrt.2d
   ; GISEL: fsqrt.2d
   %1 = call %v2f64 @llvm.sqrt.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }
 ; CHECK: test_v2f64.powi:
 define %v2f64 @test_v2f64.powi(%v2f64 %a, i32 %b) {
   ; CHECK: pow
-  %1 = call %v2f64 @llvm.powi.v2f64(%v2f64 %a, i32 %b)
+  %1 = call %v2f64 @llvm.powi.v2f64.i32(%v2f64 %a, i32 %b)
   ret %v2f64 %1
 }
 
 ; FALLBACK-NOT: remark{{.*}}test_v2f64.sin
 ; CHECK: test_v2f64.sin:
 define %v2f64 @test_v2f64.sin(%v2f64 %a) {
   ; CHECK: sin
   ; GISEL: sin

 define %v2f64 @test_v2f64.nearbyint(%v2f64 %a) {
   ; CHECK: frinti.2d
   ; GISEL: frinti.2d
   %1 = call %v2f64 @llvm.nearbyint.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }
 
 declare %v2f64 @llvm.sqrt.v2f64(%v2f64) #0
-declare %v2f64 @llvm.powi.v2f64(%v2f64, i32) #0
+declare %v2f64 @llvm.powi.v2f64.i32(%v2f64, i32) #0
 declare %v2f64 @llvm.sin.v2f64(%v2f64) #0
 declare %v2f64 @llvm.cos.v2f64(%v2f64) #0
 declare %v2f64 @llvm.pow.v2f64(%v2f64, %v2f64) #0
 declare %v2f64 @llvm.exp.v2f64(%v2f64) #0
 declare %v2f64 @llvm.exp2.v2f64(%v2f64) #0
 declare %v2f64 @llvm.log.v2f64(%v2f64) #0
 declare %v2f64 @llvm.log10.v2f64(%v2f64) #0
 declare %v2f64 @llvm.log2.v2f64(%v2f64) #0

llvm/test/CodeGen/AArch64/f16-instructions.ll

 ; CHECK-COMMON-NEXT: ret
 define half @test_bitcast_i16tohalf(i16 %a) #0 {
   %r = bitcast i16 %a to half
   ret half %r
 }
 
 
 declare half @llvm.sqrt.f16(half %a) #0
-declare half @llvm.powi.f16(half %a, i32 %b) #0
+declare half @llvm.powi.f16.i32(half %a, i32 %b) #0
 declare half @llvm.sin.f16(half %a) #0
 declare half @llvm.cos.f16(half %a) #0
 declare half @llvm.pow.f16(half %a, half %b) #0
 declare half @llvm.exp.f16(half %a) #0
 declare half @llvm.exp2.f16(half %a) #0
 declare half @llvm.log.f16(half %a) #0
 declare half @llvm.log10.f16(half %a) #0
 declare half @llvm.log2.f16(half %a) #0

 ; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
 ; CHECK-COMMON-NEXT: mov  x29, sp
 ; CHECK-COMMON-NEXT: fcvt s0, h0
 ; CHECK-COMMON-NEXT: bl {{_?}}__powisf2
 ; CHECK-COMMON-NEXT: fcvt h0, s0
 ; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
 ; CHECK-COMMON-NEXT: ret
 define half @test_powi(half %a, i32 %b) #0 {
-  %r = call half @llvm.powi.f16(half %a, i32 %b)
+  %r = call half @llvm.powi.f16.i32(half %a, i32 %b)
   ret half %r
 }
 
 ; FALLBACK-NOT: remark:{{.*}}test_sin
 ; FALLBACK-FP16-NOT: remark:{{.*}}test_sin
 
 ; CHECK-COMMON-LABEL: test_sin:
 ; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!

llvm/test/CodeGen/AArch64/illegal-float-ops.ll

; CHECK: bl pow
 
    %powfp128 = call fp128 @llvm.pow.f128(fp128 %fp128, fp128 %fp128)
    store fp128 %powfp128, fp128* @varfp128
 ; CHECK: bl powl
 
   ret void
 }
 
-declare float @llvm.powi.f32(float, i32)
-declare double @llvm.powi.f64(double, i32)
-declare fp128 @llvm.powi.f128(fp128, i32)
+declare float @llvm.powi.f32.i32(float, i32)
+declare double @llvm.powi.f64.i32(double, i32)
+declare fp128 @llvm.powi.f128.i32(fp128, i32)
 
 define void @test_powi(float %float, double %double, i32 %exponent, fp128 %fp128) {
 ; CHECK-LABEL: test_powi:
 
-   %powifloat = call float @llvm.powi.f32(float %float, i32 %exponent)
+   %powifloat = call float @llvm.powi.f32.i32(float %float, i32 %exponent)
    store float %powifloat, float* @varfloat
 ; CHECK: bl __powisf2
 
-   %powidouble = call double @llvm.powi.f64(double %double, i32 %exponent)
+   %powidouble = call double @llvm.powi.f64.i32(double %double, i32 %exponent)
    store double %powidouble, double* @vardouble
 ; CHECK: bl __powidf2
 
-   %powifp128 = call fp128 @llvm.powi.f128(fp128 %fp128, i32 %exponent)
+   %powifp128 = call fp128 @llvm.powi.f128.i32(fp128 %fp128, i32 %exponent)
    store fp128 %powifp128, fp128* @varfp128
 ; CHECK: bl __powitf2
   ret void
 
 }
 
 define void @test_frem(float %float, double %double, fp128 %fp128) {
 ; CHECK-LABEL: test_frem:

llvm/test/CodeGen/AArch64/powi-windows.ll

 ; RUN: llc -mtriple aarch64-windows < %s | FileCheck %s
 
-declare double @llvm.powi.f64(double, i32)
-declare float @llvm.powi.f32(float, i32)
+declare double @llvm.powi.f64.i32(double, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define double @d(double %d, i32 %i) {
 entry:
-  %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   ret double %0
 }
 
 ; CHECK-LABEL: d:
 ; CHECK: scvtf d1, w0
 ; CHECK-NEXT: b pow
 
 define float @f(float %f, i32 %i) {
 entry:
-  %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   ret float %0
 }
 
 ; CHECK-LABEL: f:
 ; CHECK: scvtf s1, w0
 ; CHECK-NEXT: b powf
 
 define float @g(double %d, i32 %i) {
 entry:
-  %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   %conv = fptrunc double %0 to float
   ret float %conv
 }
 
 ; CHECK-LABEL: g:
 ; CHECK: scvtf d1, w0
 ; CHECK-NEXT: bl pow
 
 define double @h(float %f, i32 %i) {
 entry:
-  %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   %conv = fpext float %0 to double
   ret double %conv
 }
 
 ; CHECK-LABEL: h:
 ; CHECK: scvtf s1, w0
 ; CHECK-NEXT: bl powf

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll

 ; GFX8-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; GFX8-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX8-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GFX8-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GFX8-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX8-NEXT:    v_exp_f16_e32 v0, v0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
   %l.cast = bitcast i16 %l to half
-  %res = call half @llvm.powi.f16(half %l.cast, i32 %r)
+  %res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r)
   %res.cast = bitcast half %res to i16
   ret i16 %res.cast
 }
 
 define float @v_powi_f32(float %l, i32 %r) {
 ; GCN-LABEL: v_powi_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 %r)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 %r)
   ret float %res
 }
 
 define float @v_powi_0_f32(float %l) {
 ; GCN-LABEL: v_powi_0_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v0, 1.0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 0)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 0)
   ret float %res
 }
 
 define float @v_powi_1_f32(float %l) {
 ; GCN-LABEL: v_powi_1_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 1)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 1)
   ret float %res
 }
 
 define float @v_powi_neg1_f32(float %l) {
 ; GCN-LABEL: v_powi_neg1_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, -1
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 -1)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 -1)
   ret float %res
 }
 
 define float @v_powi_2_f32(float %l) {
 ; GCN-LABEL: v_powi_2_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_ubyte0_e32 v1, 2
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 2)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 2)
   ret float %res
 }
 
 define float @v_powi_neg2_f32(float %l) {
 ; GCN-LABEL: v_powi_neg2_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, -2
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 -2)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 -2)
   ret float %res
 }
 
 define float @v_powi_4_f32(float %l) {
 ; GCN-LABEL: v_powi_4_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_ubyte0_e32 v1, 4
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 4)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 4)
   ret float %res
 }
 
 define float @v_powi_8_f32(float %l) {
 ; GCN-LABEL: v_powi_8_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_ubyte0_e32 v1, 8
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 8)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 8)
   ret float %res
 }
 
 define float @v_powi_16_f32(float %l) {
 ; GCN-LABEL: v_powi_16_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_ubyte0_e32 v1, 16
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 16)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 16)
   ret float %res
 }
 
 define float @v_powi_128_f32(float %l) {
 ; GCN-LABEL: v_powi_128_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_ubyte0_e32 v1, 0x80
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 128)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 128)
   ret float %res
 }
 
 define float @v_powi_neg128_f32(float %l) {
 ; GCN-LABEL: v_powi_neg128_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, 0xffffff80
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v0, v1
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 -128)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 -128)
   ret float %res
 }
 
 ; FIXME: f64 broken
 ; define double @v_powi_f64(double %l, i32 %r) {
-;   %res = call double @llvm.powi.f64(double %l, i32 %r)
+;   %res = call double @llvm.powi.f64.i32(double %l, i32 %r)
 ;   ret double %res
 ; }
 
-declare half @llvm.powi.f16(half, i32) #0
-declare float @llvm.powi.f32(float, i32) #0
-declare double @llvm.powi.f64(double, i32) #0
+declare half @llvm.powi.f16.i32(half, i32) #0
+declare float @llvm.powi.f32.i32(float, i32) #0
+declare double @llvm.powi.f64.i32(double, i32) #0
 
 attributes #0 = { nounwind readnone speculatable willreturn }

llvm/test/CodeGen/AMDGPU/llvm.powi.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX7 %s
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
 
 define i16 @v_powi_f16(i16 %l, i32 %r) {
 ; GCN-LABEL: v_powi_f16:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v1, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %l.cast = bitcast i16 %l to half
-  %res = call half @llvm.powi.f16(half %l.cast, i32 %r)
+  %res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r)
   %res.cast = bitcast half %res to i16
   ret i16 %res.cast
 }
 
 define float @v_powi_f32(float %l, i32 %r) {
 ; GCN-LABEL: v_powi_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_log_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v1
 ; GCN-NEXT:    v_mul_legacy_f32_e32 v0, v1, v0
 ; GCN-NEXT:    v_exp_f32_e32 v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 %r)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 %r)
   ret float %res
 }
 
 define float @v_powi_0_f32(float %l) {
 ; GCN-LABEL: v_powi_0_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v0, 1.0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 0)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 0)
   ret float %res
 }
 
 define float @v_powi_1_f32(float %l) {
 ; GCN-LABEL: v_powi_1_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 1)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 1)
   ret float %res
 }
 
 define float @v_powi_neg1_f32(float %l) {
 ; GFX7-LABEL: v_powi_neg1_f32:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0

 ; GFX8-NEXT:    v_fma_f32 v3, v4, v3, v3
 ; GFX8-NEXT:    v_mul_f32_e32 v4, v2, v3
 ; GFX8-NEXT:    v_fma_f32 v5, -v1, v4, v2
 ; GFX8-NEXT:    v_fma_f32 v4, v5, v3, v4
 ; GFX8-NEXT:    v_fma_f32 v1, -v1, v4, v2
 ; GFX8-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
 ; GFX8-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 -1)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 -1)
   ret float %res
 }
 
 define float @v_powi_2_f32(float %l) {
 ; GCN-LABEL: v_powi_2_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 2)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 2)
   ret float %res
 }
 
 define float @v_powi_neg2_f32(float %l) {
 ; GFX7-LABEL: v_powi_neg2_f32:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0

 ; GFX8-NEXT:    v_fma_f32 v3, v4, v3, v3
 ; GFX8-NEXT:    v_mul_f32_e32 v4, v2, v3
 ; GFX8-NEXT:    v_fma_f32 v5, -v1, v4, v2
 ; GFX8-NEXT:    v_fma_f32 v4, v5, v3, v4
 ; GFX8-NEXT:    v_fma_f32 v1, -v1, v4, v2
 ; GFX8-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
 ; GFX8-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 -2)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 -2)
   ret float %res
 }
 
 define float @v_powi_4_f32(float %l) {
 ; GCN-LABEL: v_powi_4_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 4)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 4)
   ret float %res
 }
 
 define float @v_powi_8_f32(float %l) {
 ; GCN-LABEL: v_powi_8_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 8)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 8)
   ret float %res
 }
 
 define float @v_powi_16_f32(float %l) {
 ; GCN-LABEL: v_powi_16_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 16)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 16)
   ret float %res
 }
 
 define float @v_powi_128_f32(float %l) {
 ; GCN-LABEL: v_powi_128_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 128)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 128)
   ret float %res
 }
 
 define float @v_powi_neg128_f32(float %l) {
 ; GFX7-LABEL: v_powi_neg128_f32:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0

 ; GFX8-NEXT:    v_fma_f32 v3, v4, v3, v3
 ; GFX8-NEXT:    v_mul_f32_e32 v4, v2, v3
 ; GFX8-NEXT:    v_fma_f32 v5, -v1, v4, v2
 ; GFX8-NEXT:    v_fma_f32 v4, v5, v3, v4
 ; GFX8-NEXT:    v_fma_f32 v1, -v1, v4, v2
 ; GFX8-NEXT:    v_div_fmas_f32 v1, v1, v3, v4
 ; GFX8-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
-  %res = call float @llvm.powi.f32(float %l, i32 -128)
+  %res = call float @llvm.powi.f32.i32(float %l, i32 -128)
   ret float %res
 }
 
 ; FIXME: f64 broken
 ; define double @v_powi_f64(double %l, i32 %r) {
-;   %res = call double @llvm.powi.f64(double %l, i32 %r)
+;   %res = call double @llvm.powi.f64.i32(double %l, i32 %r)
 ;   ret double %res
 ; }
 
-declare half @llvm.powi.f16(half, i32) #0
-declare float @llvm.powi.f32(float, i32) #0
-declare double @llvm.powi.f64(double, i32) #0
+declare half @llvm.powi.f16.i32(half, i32) #0
+declare float @llvm.powi.f32.i32(float, i32) #0
+declare double @llvm.powi.f64.i32(double, i32) #0
 
 attributes #0 = { nounwind readnone speculatable willreturn }

llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll

 ; CHECK:       vld1.64 {{.*}}:128
 ; CHECK:       vmul.f32 {{.*}}
 
 ; CHECK:      vst1.64
 
 L.entry:
 
   %0 = load <4 x float>, <4 x float>* @A, align 16
-  %1 = call <4 x float> @llvm.powi.v4f32(<4 x float> %0, i32 2)
+  %1 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %0, i32 2)
 
   store <4 x float> %1, <4 x float>* %X, align 16
 
   ret void
 }
 
-declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
+declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32) nounwind readonly
 
 define void @test_sin(<4 x float>* %X) nounwind {
 
 ; CHECK-LABEL: test_sin:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
 ; CHECK:      vld1.64

llvm/test/CodeGen/ARM/Windows/powi.ll

 ; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s
 
-declare double @llvm.powi.f64(double, i32)
-declare float @llvm.powi.f32(float, i32)
+declare double @llvm.powi.f64.i32(double, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define arm_aapcs_vfpcc double @d(double %d, i32 %i) {
 entry:
-  %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   ret double %0
 }
 
 ; CHECK-LABEL: d:
 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
 ; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
 ; CHECK-NEXT: b pow
 ; CHECK-NOT: __powisf2
 
 define arm_aapcs_vfpcc float @f(float %f, i32 %i) {
 entry:
-  %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   ret float %0
 }
 
 ; CHECK-LABEL: f:
 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
 ; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
 ; CHECK-NEXT: b pow
 ; CHECK-NOT: __powisf2
 
 define arm_aapcs_vfpcc float @g(double %d, i32 %i) {
 entry:
-  %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   %conv = fptrunc double %0 to float
   ret float %conv
 }
 
 ; CHECK-LABEL: g:
 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
 ; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]]
 ; CHECK-NEXT: bl pow
 ; CHECK-NOT: bl __powidf2
 ; CHECK-NEXT: vcvt.f32.f64 s0, d0
 
 define arm_aapcs_vfpcc double @h(float %f, i32 %i) {
 entry:
-  %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   %conv = fpext float %0 to double
   ret double %conv
 }
 
 ; CHECK-LABEL: h:
 ; CHECK: vmov s[[REGISTER:[0-9]+]], r0
 ; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]]
 ; CHECK-NEXT: bl powf
 ; CHECK-NOT: bl __powisf2
 ; CHECK-NEXT: vcvt.f64.f32 d0, s0
 

llvm/test/CodeGen/ARM/fp16-fullfp16.ll

 ; CHECK-NEXT:    mov r4, r0
 ; CHECK-NEXT:    mov r0, r1
 ; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
 ; CHECK-NEXT:    bl __powisf2
 ; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
 ; CHECK-NEXT:    vstr.16 s0, [r4]
 ; CHECK-NEXT:    pop {r4, pc}
   %a = load half, half* %p, align 2
-  %r = call half @llvm.powi.f16(half %a, i32 %b)
+  %r = call half @llvm.powi.f16.i32(half %a, i32 %b)
   store half %r, half* %p
   ret void
 }
 
 define void @test_sin(half* %p) {
 ; CHECK-LABEL: test_sin:
 ; CHECK:         .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
; CHECK-NEXT:    bx lr
   %b = load half, half* %q, align 2
   %c = load half, half* %r, align 2
   %v = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
   store half %v, half* %p
   ret void
 }
 
 declare half @llvm.sqrt.f16(half %a)
-declare half @llvm.powi.f16(half %a, i32 %b)
+declare half @llvm.powi.f16.i32(half %a, i32 %b)
 declare half @llvm.sin.f16(half %a)
 declare half @llvm.cos.f16(half %a)
 declare half @llvm.pow.f16(half %a, half %b)
 declare half @llvm.exp.f16(half %a)
 declare half @llvm.exp2.f16(half %a)
 declare half @llvm.log.f16(half %a)
 declare half @llvm.log10.f16(half %a)
 declare half @llvm.log2.f16(half %a)

llvm/test/CodeGen/ARM/fp16-promote.ll

 ; CHECK-ALL-NEXT: bx lr
 define void @test_bitcast_i16tohalf(i16 %a, half* %p) #0 {
   %r = bitcast i16 %a to half
   store half %r, half* %p
   ret void
 }
 
 declare half @llvm.sqrt.f16(half %a) #0
-declare half @llvm.powi.f16(half %a, i32 %b) #0
+declare half @llvm.powi.f16.i32(half %a, i32 %b) #0
 declare half @llvm.sin.f16(half %a) #0
 declare half @llvm.cos.f16(half %a) #0
 declare half @llvm.pow.f16(half %a, half %b) #0
 declare half @llvm.exp.f16(half %a) #0
 declare half @llvm.exp2.f16(half %a) #0
 declare half @llvm.log.f16(half %a) #0
 declare half @llvm.log10.f16(half %a) #0
 declare half @llvm.log2.f16(half %a) #0

 ; CHECK-FP16: bl __powisf2
 ; CHECK-FP16: vcvtb.f16.f32
 ; CHECK-LIBCALL-LABEL: test_fpowi:
 ; CHECK-LIBCALL: bl __aeabi_h2f
 ; CHECK-LIBCALL: bl __powisf2
 ; CHECK-LIBCALL: bl __aeabi_f2h
 define void @test_fpowi(half* %p, i32 %b) #0 {
   %a = load half, half* %p, align 2
-  %r = call half @llvm.powi.f16(half %a, i32 %b)
+  %r = call half @llvm.powi.f16.i32(half %a, i32 %b)
   store half %r, half* %p
   ret void
 }
 
 ; CHECK-FP16-LABEL: test_sin:
 ; CHECK-FP16: vcvtb.f32.f16
 ; CHECK-FP16: bl sinf
 ; CHECK-FP16: vcvtb.f16.f32

llvm/test/CodeGen/ARM/fpowi.ll

 ; RUN: llc -mtriple arm-unknown-linux-gnueabi -filetype asm -o - %s | FileCheck %s
 ; PR1287
 
 ; ModuleID = '<stdin>'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "arm-unknown-linux-gnueabi"
 
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 
 define double @_ZSt3powdi(double %__x, i32 %__i) {
 entry:
-  %tmp3 = call double @llvm.powi.f64(double %__x, i32 %__i)
+  %tmp3 = call double @llvm.powi.f64.i32(double %__x, i32 %__i)
   ret double %tmp3
 }
 
 ; CHECK: bl __powidf2
 

llvm/test/CodeGen/ARM/vfloatintrinsics.ll

 ; RUN: llc -mcpu=swift < %s | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "arm-apple-ios6.1.0"
 
 ;;; Float vectors
 
 %v2f32 = type <2 x float>
 ; CHECK-LABEL: test_v2f32.sqrt:{{.*}}
 define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
   ; CHECK: sqrt
   %1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
 ; CHECK-LABEL: test_v2f32.powi:{{.*}}
 define %v2f32 @test_v2f32.powi(%v2f32 %a, i32 %b) {
   ; CHECK: pow
-  %1 = call %v2f32 @llvm.powi.v2f32(%v2f32 %a, i32 %b)
+  %1 = call %v2f32 @llvm.powi.v2f32.i32(%v2f32 %a, i32 %b)
   ret %v2f32 %1
 }
 ; CHECK-LABEL: test_v2f32.sin:{{.*}}
 define %v2f32 @test_v2f32.sin(%v2f32 %a) {
   ; CHECK: sin
   %1 = call %v2f32 @llvm.sin.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }

 ; CHECK-LABEL: test_v2f32.nearbyint:{{.*}}
 define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
   ; CHECK: nearbyint
   %1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
   ret %v2f32 %1
 }
 
 declare %v2f32 @llvm.sqrt.v2f32(%v2f32) #0
-declare %v2f32 @llvm.powi.v2f32(%v2f32, i32) #0
+declare %v2f32 @llvm.powi.v2f32.i32(%v2f32, i32) #0
 declare %v2f32 @llvm.sin.v2f32(%v2f32) #0
 declare %v2f32 @llvm.cos.v2f32(%v2f32) #0
 declare %v2f32 @llvm.pow.v2f32(%v2f32, %v2f32) #0
 declare %v2f32 @llvm.exp.v2f32(%v2f32) #0
 declare %v2f32 @llvm.exp2.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log10.v2f32(%v2f32) #0
 declare %v2f32 @llvm.log2.v2f32(%v2f32) #0

 define %v4f32 @test_v4f32.sqrt(%v4f32 %a) {
   ; CHECK: sqrt
   %1 = call %v4f32 @llvm.sqrt.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
 ; CHECK-LABEL: test_v4f32.powi:{{.*}}
 define %v4f32 @test_v4f32.powi(%v4f32 %a, i32 %b) {
   ; CHECK: pow
-  %1 = call %v4f32 @llvm.powi.v4f32(%v4f32 %a, i32 %b)
+  %1 = call %v4f32 @llvm.powi.v4f32.i32(%v4f32 %a, i32 %b)
   ret %v4f32 %1
 }
 ; CHECK-LABEL: test_v4f32.sin:{{.*}}
 define %v4f32 @test_v4f32.sin(%v4f32 %a) {
   ; CHECK: sin
   %1 = call %v4f32 @llvm.sin.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }

 ; CHECK-LABEL: test_v4f32.nearbyint:{{.*}}
 define %v4f32 @test_v4f32.nearbyint(%v4f32 %a) {
   ; CHECK: nearbyint
   %1 = call %v4f32 @llvm.nearbyint.v4f32(%v4f32 %a)
   ret %v4f32 %1
 }
 
 declare %v4f32 @llvm.sqrt.v4f32(%v4f32) #0
-declare %v4f32 @llvm.powi.v4f32(%v4f32, i32) #0
+declare %v4f32 @llvm.powi.v4f32.i32(%v4f32, i32) #0
 declare %v4f32 @llvm.sin.v4f32(%v4f32) #0
 declare %v4f32 @llvm.cos.v4f32(%v4f32) #0
 declare %v4f32 @llvm.pow.v4f32(%v4f32, %v4f32) #0
 declare %v4f32 @llvm.exp.v4f32(%v4f32) #0
 declare %v4f32 @llvm.exp2.v4f32(%v4f32) #0
 declare %v4f32 @llvm.log.v4f32(%v4f32) #0
 declare %v4f32 @llvm.log10.v4f32(%v4f32) #0
 declare %v4f32 @llvm.log2.v4f32(%v4f32) #0

 define %v2f64 @test_v2f64.sqrt(%v2f64 %a) {
   ; CHECK: sqrt
   %1 = call %v2f64 @llvm.sqrt.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }
 ; CHECK-LABEL: test_v2f64.powi:{{.*}}
 define %v2f64 @test_v2f64.powi(%v2f64 %a, i32 %b) {
   ; CHECK: pow
-  %1 = call %v2f64 @llvm.powi.v2f64(%v2f64 %a, i32 %b)
+  %1 = call %v2f64 @llvm.powi.v2f64.i32(%v2f64 %a, i32 %b)
   ret %v2f64 %1
 }
 ; CHECK-LABEL: test_v2f64.sin:{{.*}}
 define %v2f64 @test_v2f64.sin(%v2f64 %a) {
   ; CHECK: sin
   %1 = call %v2f64 @llvm.sin.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }

 ; CHECK-LABEL: test_v2f64.nearbyint:{{.*}}
 define %v2f64 @test_v2f64.nearbyint(%v2f64 %a) {
   ; CHECK: nearbyint
   %1 = call %v2f64 @llvm.nearbyint.v2f64(%v2f64 %a)
   ret %v2f64 %1
 }
 
 declare %v2f64 @llvm.sqrt.v2f64(%v2f64) #0
-declare %v2f64 @llvm.powi.v2f64(%v2f64, i32) #0
+declare %v2f64 @llvm.powi.v2f64.i32(%v2f64, i32) #0
 declare %v2f64 @llvm.sin.v2f64(%v2f64) #0
 declare %v2f64 @llvm.cos.v2f64(%v2f64) #0
 declare %v2f64 @llvm.pow.v2f64(%v2f64, %v2f64) #0
 declare %v2f64 @llvm.exp.v2f64(%v2f64) #0
 declare %v2f64 @llvm.exp2.v2f64(%v2f64) #0
 declare %v2f64 @llvm.log.v2f64(%v2f64) #0
 declare %v2f64 @llvm.log10.v2f64(%v2f64) #0
 declare %v2f64 @llvm.log2.v2f64(%v2f64) #0

llvm/test/CodeGen/Generic/fpowi-promote.ll

 ; RUN: llc < %s
 
 ; PR1239
 
 define float @test(float %tmp23302331, i32 %tmp23282329 ) {
 
-%tmp2339 = call float @llvm.powi.f32( float %tmp23302331, i32 %tmp23282329 )
+%tmp2339 = call float @llvm.powi.f32.i32( float %tmp23302331, i32 %tmp23282329 )
   ret float %tmp2339
 }
 
-declare float @llvm.powi.f32(float,i32)
+declare float @llvm.powi.f32.i32(float,i32)

llvm/test/CodeGen/Generic/replace-intrinsics-with-veclib.ll

 
 declare double @llvm.exp.f64(double) #0
 
 ; Check that the pass works with scalar operands on
 ; vector intrinsics. No vector library has a substitute for powi.
 define <4 x double> @powi_v4(<4 x double> %in){
 ; COMMON-LABEL: define {{[^@]+}}@powi_v4
 ; COMMON-SAME: (<4 x double> [[IN:%.*]]) {
-; COMMON-NEXT:    [[CALL:%.*]] = call <4 x double> @llvm.powi.v4f64(<4 x double> [[IN]], i32 3)
+; COMMON-NEXT:    [[CALL:%.*]] = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> [[IN]], i32 3)
 ; COMMON-NEXT:    ret <4 x double> [[CALL]]
 ;
-  %call = call <4 x double> @llvm.powi.v4f64(<4 x double> %in, i32 3)
+  %call = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> %in, i32 3)
   ret <4 x double> %call
 }
 
-declare <4 x double> @llvm.powi.v4f64(<4 x double>, i32) #0
+declare <4 x double> @llvm.powi.v4f64.i32(<4 x double>, i32) #0
 
 ; Replacement should not take place if the vector length
 ; does not match exactly.
 define <3 x double> @exp_v3(<3 x double> %in) {
 ; COMMON-LABEL: define {{[^@]+}}@exp_v3
 ; COMMON-SAME: (<3 x double> [[IN:%.*]]) {
 ; COMMON-NEXT:    [[CALL:%.*]] = call <3 x double> @llvm.exp.v3f64(<3 x double> [[IN]])
 ; COMMON-NEXT:    ret <3 x double> [[CALL]]
 ;
   %call = call <3 x double> @llvm.exp.v3f64(<3 x double> %in)
   ret <3 x double> %call
 }
 
 declare <3 x double> @llvm.exp.v3f64(<3 x double>) #0
 
 attributes #0 = {nounwind readnone}

llvm/test/CodeGen/Mips/mips64-f128.ll

 
 declare fp128 @rintl(fp128) #1
 
 ; ALL-LABEL: libcall_powil:
 ; ALL: ld $25, %call16(__powitf2)
 
 define fp128 @libcall_powil(fp128 %a, i32 %b) {
 entry:
-  %0 = tail call fp128 @llvm.powi.f128(fp128 %a, i32 %b)
+  %0 = tail call fp128 @llvm.powi.f128.i32(fp128 %a, i32 %b)
   ret fp128 %0
 }
 
-declare fp128 @llvm.powi.f128(fp128, i32) #3
+declare fp128 @llvm.powi.f128.i32(fp128, i32) #3
 
 ; ALL-LABEL:     libcall2_copysignl:
 ; NOT-R2R6-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
 ; NOT-R2R6-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 63
 ; ALL-DAG:      ld     $[[R0:[0-9]+]], %got_disp(gld1)
 ; ALL-DAG:      ld     $[[R1:[0-9]+]], 8($[[R0]])
 ; NOT-R2R6-DAG: and    $[[R4:[0-9]+]], $[[R1]], $[[R3]]
 ; ALL-DAG:      ld     $[[R5:[0-9]+]], %got_disp(gld0)

llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll

entry:
 
 
   %4 = zext i1 %fcmp to i16
   store i16 %4, i16* @i1, align 2
 
   ret void
 }
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define void @fpowi() {
 ; MIPS32-LABEL: fpowi:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    lui $2, %hi(_gp_disp)
 ; MIPS32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; MIPS32-NEXT:    addu $1, $2, $25
 ; MIPS32-NEXT:    lw $1, %got(g)($1)

 ; MIPS64-N64-NEXT:    copy_u.h $2, $w0[0]
 ; MIPS64-N64-NEXT:    jr $ra
 ; MIPS64-N64-NEXT:    sh $2, 0($1)
 entry:
   %0 = load i16, i16* @g, align 2
   %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
 
 
-  %powi = call float @llvm.powi.f32(float %1, i32 2)
+  %powi = call float @llvm.powi.f32.i32(float %1, i32 2)
 
 
   %2 = call i16 @llvm.convert.to.fp16.f32(float %powi)
 
 
   store i16 %2, i16* @g, align 2
   ret void
 }

 ; MIPS64-N64-NEXT:    ld $ra, 24($sp) # 8-byte Folded Reload
 ; MIPS64-N64-NEXT:    jr $ra
 ; MIPS64-N64-NEXT:    daddiu $sp, $sp, 32
 entry:
   %0 = load i16, i16* @g, align 2
   %1 = call float @llvm.convert.from.fp16.f32(i16 %0)
 
 
-  %powi = call float @llvm.powi.f32(float %1, i32 %var)
+  %powi = call float @llvm.powi.f32.i32(float %1, i32 %var)
 
 
   %2 = call i16 @llvm.convert.to.fp16.f32(float %powi)
 
 
   store i16 %2, i16* @g, align 2
   ret void
 }

llvm/test/CodeGen/Mips/powif64_16.ll

 ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s
 
-declare float     @llvm.powi.f32(float  %Val, i32 %power)
-declare double    @llvm.powi.f64(double %Val, i32 %power)
+declare float     @llvm.powi.f32.i32(float  %Val, i32 %power)
+declare double    @llvm.powi.f64.i32(double %Val, i32 %power)
 
 define float @foo_pow_f32(float %y, i32 %p)  {
-  %1 = tail call float @llvm.powi.f32(float %y, i32 %p)
+  %1 = tail call float @llvm.powi.f32.i32(float %y, i32 %p)
 ; CHECK-NOT: .ent __call_stub_fp_llvm.powi.f32
 ; CHECK-NOT: {{.*}} jal llvm.powi.f32
   ret float %1
 } 
 
 define double @foo_pow_f64(double %y, i32 %p)  {
-  %1 = tail call double @llvm.powi.f64(double %y, i32 %p)
+  %1 = tail call double @llvm.powi.f64.i32(double %y, i32 %p)
 ; CHECK-NOT: .ent __call_stub_fp_llvm.powi.f64
 ; CHECK-NOT: {{.*}} jal llvm.powi.f64 
   ret double %1
 } 
 
 attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
 attributes #1 = { nounwind readonly }
 
 !0 = !{!"double", !1}
 !1 = !{!"omnipotent char", !2}
 !2 = !{!"Simple C/C++ TBAA"}
 !3 = !{!"int", !1}

llvm/test/CodeGen/Mips/pr36061.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n64 | FileCheck %s --check-prefix=MIPSN64
 ; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -target-abi n32 | FileCheck %s --check-prefix=MIPSN32
 
 ; Test that powi has its integer argument sign extended on mips64.
 
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 
 define double @powi(double %value, i32 %power) {
 ; MIPSN64-LABEL: powi:
 ; MIPSN64:       # %bb.0:
 ; MIPSN64-NEXT:    daddiu $sp, $sp, -16
 ; MIPSN64-NEXT:    .cfi_def_cfa_offset 16
 ; MIPSN64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; MIPSN64-NEXT:    .cfi_offset 31, -8

 ; MIPSN32-NEXT:    .cfi_def_cfa_offset 16
 ; MIPSN32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; MIPSN32-NEXT:    .cfi_offset 31, -8
 ; MIPSN32-NEXT:    jal __powidf2
 ; MIPSN32-NEXT:    sll $5, $5, 0
 ; MIPSN32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; MIPSN32-NEXT:    jr $ra
 ; MIPSN32-NEXT:    addiu $sp, $sp, 16
-        %1 = tail call double @llvm.powi.f64(double %value, i32 %power)
+        %1 = tail call double @llvm.powi.f64.i32(double %value, i32 %power)
         ret double %1
 }
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define float @powfi(float %value, i32 %power) {
 ; MIPSN64-LABEL: powfi:
 ; MIPSN64:       # %bb.0:
 ; MIPSN64-NEXT:    daddiu $sp, $sp, -16
 ; MIPSN64-NEXT:    .cfi_def_cfa_offset 16
 ; MIPSN64-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; MIPSN64-NEXT:    .cfi_offset 31, -8

 ; MIPSN32-NEXT:    .cfi_def_cfa_offset 16
 ; MIPSN32-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; MIPSN32-NEXT:    .cfi_offset 31, -8
 ; MIPSN32-NEXT:    jal __powisf2
 ; MIPSN32-NEXT:    sll $5, $5, 0
 ; MIPSN32-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
 ; MIPSN32-NEXT:    jr $ra
 ; MIPSN32-NEXT:    addiu $sp, $sp, 16
-        %1 = tail call float @llvm.powi.f32(float %value, i32 %power)
+        %1 = tail call float @llvm.powi.f32.i32(float %value, i32 %power)
         ret float %1
 }

llvm/test/CodeGen/NVPTX/f16-instructions.ll

 ; CHECK:      ret;
 define half @test_bitcast_i16tohalf(i16 %a) #0 {
   %r = bitcast i16 %a to half
   ret half %r
 }
 
 
 declare half @llvm.sqrt.f16(half %a) #0
-declare half @llvm.powi.f16(half %a, i32 %b) #0
+declare half @llvm.powi.f16.i32(half %a, i32 %b) #0
 declare half @llvm.sin.f16(half %a) #0
 declare half @llvm.cos.f16(half %a) #0
 declare half @llvm.pow.f16(half %a, half %b) #0
 declare half @llvm.exp.f16(half %a) #0
 declare half @llvm.exp2.f16(half %a) #0
 declare half @llvm.log.f16(half %a) #0
 declare half @llvm.log10.f16(half %a) #0
 declare half @llvm.log2.f16(half %a) #0

 define half @test_sqrt(half %a) #0 {
   %r = call half @llvm.sqrt.f16(half %a)
   ret half %r
 }
 
 ;;; Can't do this yet: requires libcall.
 ; XCHECK-LABEL: test_powi(
 ;define half @test_powi(half %a, i32 %b) #0 {
-;  %r = call half @llvm.powi.f16(half %a, i32 %b)
+;  %r = call half @llvm.powi.f16.i32(half %a, i32 %b)
 ;  ret half %r
 ;}
 
 ; CHECK-LABEL: test_sin(
 ; CHECK:      ld.param.b16    [[A:%h[0-9]+]], [test_sin_param_0];
 ; CHECK-NOFTZ:      cvt.f32.f16     [[AF:%f[0-9]+]], [[A]];
 ; CHECK-F16-FTZ:      cvt.ftz.f32.f16     [[AF:%f[0-9]+]], [[A]];
 ; CHECK:      sin.approx.f32  [[RF:%f[0-9]+]], [[AF]];

llvm/test/CodeGen/NVPTX/f16x2-instructions.ll

 ; CHECK:      ret;
 define <2 x half> @test_bitcast_2xi16_to_2xhalf(<2 x i16> %a) #0 {
   %r = bitcast <2 x i16> %a to <2 x half>
   ret <2 x half> %r
 }
 
 
 declare <2 x half> @llvm.sqrt.f16(<2 x half> %a) #0
-declare <2 x half> @llvm.powi.f16(<2 x half> %a, <2 x i32> %b) #0
+declare <2 x half> @llvm.powi.f16.i32(<2 x half> %a, <2 x i32> %b) #0
 declare <2 x half> @llvm.sin.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.cos.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.pow.f16(<2 x half> %a, <2 x half> %b) #0
 declare <2 x half> @llvm.exp.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.exp2.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.log.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.log10.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.log2.f16(<2 x half> %a) #0

 define <2 x half> @test_sqrt(<2 x half> %a) #0 {
   %r = call <2 x half> @llvm.sqrt.f16(<2 x half> %a)
   ret <2 x half> %r
 }
 
 ;;; Can't do this yet: requires libcall.
 ; XCHECK-LABEL: test_powi(
 ;define <2 x half> @test_powi(<2 x half> %a, <2 x i32> %b) #0 {
-;  %r = call <2 x half> @llvm.powi.f16(<2 x half> %a, <2 x i32> %b)
+;  %r = call <2 x half> @llvm.powi.f16.i32(<2 x half> %a, <2 x i32> %b)
 ;  ret <2 x half> %r
 ;}
 
 ; CHECK-LABEL: test_sin(
 ; CHECK:      ld.param.b32    [[A:%hh[0-9]+]], [test_sin_param_0];
 ; CHECK:      mov.b32         {[[A0:%h[0-9]+]], [[A1:%h[0-9]+]]}, [[A]]
 ; CHECK-DAG:  cvt.f32.f16     [[AF0:%f[0-9]+]], [[A0]];
 ; CHECK-DAG:  cvt.f32.f16     [[AF1:%f[0-9]+]], [[A1]];

llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll

 ; RUN: not --crash llc < %s -march=nvptx 2>&1 | FileCheck %s
 ; used to seqfault and now fails with an "Undefined external symbol"
 
 ; CHECK: LLVM ERROR: Undefined external symbol "__powidf2"
 define double @powi(double, i32) {
-  %a = call double @llvm.powi.f64(double %0, i32 %1)
+  %a = call double @llvm.powi.f64.i32(double %0, i32 %1)
   ret double %a
 }
 
-declare double @llvm.powi.f64(double, i32) nounwind readnone
+declare double @llvm.powi.f64.i32(double, i32) nounwind readnone

llvm/test/CodeGen/PowerPC/f128-arith.ll

 ; CHECK-P8-NEXT:    ld r0, 16(r1)
 ; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; CHECK-P8-NEXT:    mtlr r0
 ; CHECK-P8-NEXT:    blr
                      fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load i32, i32* %b, align 8
-  %2 = tail call fp128 @llvm.powi.f128(fp128 %0, i32 %1)
+  %2 = tail call fp128 @llvm.powi.f128.i32(fp128 %0, i32 %1)
   store fp128 %2, fp128* %res, align 16
   ret void
 }
-declare fp128 @llvm.powi.f128(fp128 %Val, i32 %power)
+declare fp128 @llvm.powi.f128.i32(fp128 %Val, i32 %power)
 
 @a = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
 @b = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
 
 define fp128 @qp_frem() #0 {
 ; CHECK-LABEL: qp_frem:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0

llvm/test/CodeGen/RISCV/double-intrinsics.ll

 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fsqrt.d ft0, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 
 define double @powi_f64(double %a, i32 %b) nounwind {
 ; RV32IFD-LABEL: powi_f64:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call __powidf2@plt
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: powi_f64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi sp, sp, -16
 ; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFD-NEXT:    sext.w a1, a1
 ; RV64IFD-NEXT:    call __powidf2@plt
 ; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
-  %1 = call double @llvm.powi.f64(double %a, i32 %b)
+  %1 = call double @llvm.powi.f64.i32(double %a, i32 %b)
   ret double %1
 }
 
 declare double @llvm.sin.f64(double)
 
 define double @sin_f64(double %a) nounwind {
 ; RV32IFD-LABEL: sin_f64:
 ; RV32IFD:       # %bb.0:

llvm/test/CodeGen/RISCV/float-intrinsics.ll

 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fsqrt.s ft0, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define float @powi_f32(float %a, i32 %b) nounwind {
 ; RV32IF-LABEL: powi_f32:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call __powisf2@plt
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: powi_f32:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    sext.w a1, a1
 ; RV64IF-NEXT:    call __powisf2@plt
 ; RV64IF-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
-  %1 = call float @llvm.powi.f32(float %a, i32 %b)
+  %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
   ret float %1
 }
 
 declare float @llvm.sin.f32(float)
 
 define float @sin_f32(float %a) nounwind {
 ; RV32IF-LABEL: sin_f32:
 ; RV32IF:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll

 ; RV64I-NEXT:    call powf@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %1 = call float @llvm.pow.f32(float %a, float %b)
   ret float %1
 }
 
-declare float @llvm.powi.f32(float %Val, i32 %power)
+declare float @llvm.powi.f32.i32(float %Val, i32 %power)
 
 define float @fpowi_s(float %a, i32 %b) nounwind {
 ; RV64I-LABEL: fpowi_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    call __powisf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
-  %1 = call float @llvm.powi.f32(float %a, i32 %b)
+  %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
   ret float %1
 }
 
 define double @fp_ext(float %a) nounwind {
 ; RV64I-LABEL: fp_ext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill

llvm/test/CodeGen/SystemZ/fp-libcall.ll

 ; Test that library calls are emitted for LLVM IR intrinsics
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define float @f1(float %x, i32 %y) {
 ; CHECK-LABEL: f1:
 ; CHECK: brasl %r14, __powisf2@PLT
-  %tmp = call float @llvm.powi.f32(float %x, i32 %y)
+  %tmp = call float @llvm.powi.f32.i32(float %x, i32 %y)
   ret float %tmp
 }
 
 define double @f2(double %x, i32 %y) {
 ; CHECK-LABEL: f2:
 ; CHECK: brasl %r14, __powidf2@PLT
-  %tmp = call double @llvm.powi.f64(double %x, i32 %y)
+  %tmp = call double @llvm.powi.f64.i32(double %x, i32 %y)
   ret double %tmp
 }
 
 define fp128 @f3(fp128 %x, i32 %y) {
 ; CHECK-LABEL: f3:
 ; CHECK: brasl %r14, __powitf2@PLT
-  %tmp = call fp128 @llvm.powi.f128(fp128 %x, i32 %y)
+  %tmp = call fp128 @llvm.powi.f128.i32(fp128 %x, i32 %y)
   ret fp128 %tmp
 }
 
 define float @f4(float %x, float %y) {
 ; CHECK-LABEL: f4:
 ; CHECK: brasl %r14, powf@PLT
   %tmp = call float @llvm.pow.f32(float %x, float %y)
   ret float %tmp

 ; CHECK: cxbr
 ; CHECK: jh
 ; CHECK: lxr
 ; CHECK: br %r14
   %tmp = call nnan fp128 @llvm.maxnum.f128(fp128 %x, fp128 %y)
   ret fp128 %tmp
 }
 
-declare float @llvm.powi.f32(float, i32)
-declare double @llvm.powi.f64(double, i32)
-declare fp128 @llvm.powi.f128(fp128, i32)
+declare float @llvm.powi.f32.i32(float, i32)
+declare double @llvm.powi.f64.i32(double, i32)
+declare fp128 @llvm.powi.f128.i32(fp128, i32)
 declare float @llvm.pow.f32(float, float)
 declare double @llvm.pow.f64(double, double)
 declare fp128 @llvm.pow.f128(fp128, fp128)
 
 declare float @llvm.sin.f32(float)
 declare double @llvm.sin.f64(double)
 declare fp128 @llvm.sin.f128(fp128)
 declare float @llvm.cos.f32(float)

llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll

 ; RUN: llc < %s -mtriple=thumbv7-none-eabi   -mcpu=cortex-m3                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4                    | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP  -check-prefix=FP-ARMv8
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 -mattr=-fp64 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=SP
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7                    | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=VFP4
 ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a57                   | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON -check-prefix=FP-ARMv8
 
 declare double     @llvm.sqrt.f64(double %Val)
 define double @sqrt_d(double %a) {
 ; CHECK-LABEL: sqrt_d:
 ; SOFT: {{(bl|b)}} sqrt
 ; HARD: vsqrt.f64 d0, d0
   %1 = call double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
-declare double     @llvm.powi.f64(double %Val, i32 %power)
+declare double     @llvm.powi.f64.i32(double %Val, i32 %power)
 define double @powi_d(double %a, i32 %b) {
 ; CHECK-LABEL: powi_d:
 ; SOFT: {{(bl|b)}} __powidf2
 ; HARD: b __powidf2
-  %1 = call double @llvm.powi.f64(double %a, i32 %b)
+  %1 = call double @llvm.powi.f64.i32(double %a, i32 %b)
   ret double %1
 }
 
 declare double     @llvm.sin.f64(double %Val)
 define double @sin_d(double %a) {
 ; CHECK-LABEL: sin_d:
 ; SOFT: {{(bl|b)}} sin
 ; HARD: b sin

llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll

 define float @sqrt_f(float %a) {
 ; CHECK-LABEL: sqrt_f:
 ; SOFT: bl sqrtf
 ; HARD: vsqrt.f32 s0, s0
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
-declare float     @llvm.powi.f32(float %Val, i32 %power)
+declare float     @llvm.powi.f32.i32(float %Val, i32 %power)
 define float @powi_f(float %a, i32 %b) {
 ; CHECK-LABEL: powi_f:
 ; SOFT: bl __powisf2
 ; HARD: b __powisf2
-  %1 = call float @llvm.powi.f32(float %a, i32 %b)
+  %1 = call float @llvm.powi.f32.i32(float %a, i32 %b)
   ret float %1
 }
 
 declare float     @llvm.sin.f32(float %Val)
 define float @sin_f(float %a) {
 ; CHECK-LABEL: sin_f:
 ; SOFT: bl sinf
 ; HARD: b sinf

llvm/test/CodeGen/Thumb2/intrinsics-cc.ll

 ; RUN: llc -mtriple thumbv7-unknown-none-eabi -float-abi soft -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-eabi -float-abi hard -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-eabihf -float-abi soft -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-eabihf -float-abi hard -filetype asm -o - %s | FileCheck %s
 
 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabi -float-abi soft -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabi -float-abi hard -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabihf -float-abi soft -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-gnueabihf -float-abi hard -filetype asm -o - %s | FileCheck %s
 
 ; RUN: llc -mtriple thumbv7-unknown-none-musleabi -float-abi soft -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-musleabi -float-abi hard -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-musleabihf -float-abi soft -filetype asm -o - %s | FileCheck %s
 ; RUN: llc -mtriple thumbv7-unknown-none-musleabihf -float-abi hard -filetype asm -o - %s | FileCheck %s
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define float @powi_f32(float %f, i32 %i) {
 entry:
-  %0 = call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = call float @llvm.powi.f32.i32(float %f, i32 %i)
   ret float %0
 }
 
 ; CHECK: b __powisf2
 
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 
 define double @powi_f64(double %d, i32 %i) {
 entry:
-  %0 = call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = call double @llvm.powi.f64.i32(double %d, i32 %i)
   ret double %0
 }
 
 ; CHECK: b __powidf2
 
 declare float @llvm.floor.f32(float)
 
 define float @floor_f32(float %f) {

llvm/test/CodeGen/WebAssembly/libcalls.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s
 
 ; Test a subset of compiler-rt/libm libcalls expected to be emitted by the wasm backend
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare fp128 @llvm.sqrt.f128(fp128)
 declare fp128 @llvm.floor.f128(fp128)
 declare fp128 @llvm.trunc.f128(fp128)
 declare fp128 @llvm.nearbyint.f128(fp128)
 declare fp128 @llvm.pow.f128(fp128, fp128)
-declare fp128 @llvm.powi.f128(fp128, i32)
+declare fp128 @llvm.powi.f128.i32(fp128, i32)
 
 declare double @llvm.cos.f64(double)
 declare double @llvm.log10.f64(double)
 declare double @llvm.pow.f64(double, double)
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 declare double @llvm.log.f64(double)
 declare double @llvm.exp.f64(double)
 declare i32 @llvm.lround(double)
 
 
 
 ; CHECK-LABEL: fp128libcalls:
 define fp128 @fp128libcalls(fp128 %x, fp128 %y, i32 %z) {
   ; compiler-rt call
   ; CHECK: call __addtf3
   %a = fadd fp128 %x, %y
   ; CHECK: call __multf3
   %b = fmul fp128 %a, %y
   ; CHECK: call __divtf3
   %c = fdiv fp128 %b, %y
   ; libm calls
   ; CHECK: call sqrtl
   %d = call fp128 @llvm.sqrt.f128(fp128 %c)
   ; CHECK: call floorl
   %e = call fp128 @llvm.floor.f128(fp128 %d)
   ; CHECK: call powl
   %f = call fp128 @llvm.pow.f128(fp128 %e, fp128 %y)
   ; CHECK: call __powitf2
-  %g = call fp128 @llvm.powi.f128(fp128 %f, i32 %z)
+  %g = call fp128 @llvm.powi.f128.i32(fp128 %f, i32 %z)
   ; CHECK: call truncl
   %h = call fp128 @llvm.trunc.f128(fp128 %g)
   ; CHECK: call nearbyintl
   %i = call fp128 @llvm.nearbyint.f128(fp128 %h)
   ret fp128 %i
 }
 
 ; CHECK-LABEL: i128libcalls:

 define i32 @f64libcalls(double %x, double %y, i32 %z) {
  ; CHECK: call $push{{[0-9]}}=, cos
  %a = call double @llvm.cos.f64(double %x)
  ; CHECK: call $push{{[0-9]}}=, log10
  %b = call double @llvm.log10.f64(double %a)
  ; CHECK: call $push{{[0-9]}}=, pow
  %c = call double @llvm.pow.f64(double %b, double %y)
  ; CHECK: call $push{{[0-9]}}=, __powidf2
- %d = call double @llvm.powi.f64(double %c, i32 %z)
+ %d = call double @llvm.powi.f64.i32(double %c, i32 %z)
  ; CHECK: call $push{{[0-9]}}=, log
  %e = call double @llvm.log.f64(double %d)
  ; CHECK: call $push{{[0-9]}}=, exp
  %f = call double @llvm.exp.f64(double %e)
  ; CHECK: call $push{{[0-9]}}=, cbrt
  %g = call fast double @llvm.pow.f64(double %f, double 0x3FD5555555555555)
  ; CHECK: call $push{{[0-9]}}=, lround
  %h = call i32 @llvm.lround(double %g)

llvm/test/CodeGen/WebAssembly/simd-unsupported.ll

 declare <4 x float> @llvm.cos.v4f32(<4 x float>)
 define <4 x float> @cos_v4f32(<4 x float> %x) {
   %v = call <4 x float> @llvm.cos.v4f32(<4 x float> %x)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: powi_v4f32:
 ; CHECK: call $push[[L:[0-9]+]]=, __powisf2
-declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32)
+declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32)
 define <4 x float> @powi_v4f32(<4 x float> %x, i32 %y) {
-  %v = call <4 x float> @llvm.powi.v4f32(<4 x float> %x, i32 %y)
+  %v = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %x, i32 %y)
   ret <4 x float> %v
 }
 
 ; CHECK-LABEL: pow_v4f32:
 ; CHECK: call $push[[L:[0-9]+]]=, powf
 declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
 define <4 x float> @pow_v4f32(<4 x float> %x, <4 x float> %y) {
   %v = call <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> %y)

 declare <2 x double> @llvm.cos.v2f64(<2 x double>)
 define <2 x double> @cos_v2f64(<2 x double> %x) {
   %v = call <2 x double> @llvm.cos.v2f64(<2 x double> %x)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: powi_v2f64:
 ; CHECK: call $push[[L:[0-9]+]]=, __powidf2
-declare <2 x double> @llvm.powi.v2f64(<2 x double>, i32)
+declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32)
 define <2 x double> @powi_v2f64(<2 x double> %x, i32 %y) {
-  %v = call <2 x double> @llvm.powi.v2f64(<2 x double> %x, i32 %y)
+  %v = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> %x, i32 %y)
   ret <2 x double> %v
 }
 
 ; CHECK-LABEL: pow_v2f64:
 ; CHECK: call $push[[L:[0-9]+]]=, pow
 declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
 define <2 x double> @pow_v2f64(<2 x double> %x, <2 x double> %y) {
   %v = call <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> %y)

llvm/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll

 ; CHECK-NEXT: fsqrt
 ; CHECK-NEXT: ret
 }
 
 declare x86_fp80 @llvm.sqrt.f80(x86_fp80)
 
 define x86_fp80 @bar(x86_fp80 %x) nounwind {
 entry:
-  %tmp2 = call x86_fp80 @llvm.powi.f80( x86_fp80 %x, i32 3 )
+  %tmp2 = call x86_fp80 @llvm.powi.f80.i32( x86_fp80 %x, i32 3 )
   ret x86_fp80 %tmp2
 ; CHECK-LABEL: bar:
 ; CHECK: fldt 4(%esp)
 ; CHECK-NEXT: fld %st(0)
 ; CHECK-NEXT: fmul  %st(1)
 ; CHECK-NEXT: fmulp
 ; CHECK-NEXT: ret
 }
 
-declare x86_fp80 @llvm.powi.f80(x86_fp80, i32)
+declare x86_fp80 @llvm.powi.f80.i32(x86_fp80, i32)

llvm/test/CodeGen/X86/2010-05-07-ldconvert.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin11
 ; PR 7087 - used to crash
 
 define i32 @main() ssp {
 entry:
   %retval = alloca i32, align 4                   ; <i32*> [#uses=2]
   %r = alloca i32, align 4                        ; <i32*> [#uses=2]
   store i32 0, i32* %retval
-  %tmp = call x86_fp80 @llvm.powi.f80(x86_fp80 0xK3FFF8000000000000000, i32 -64) ; <x86_fp80> [#uses=1]
+  %tmp = call x86_fp80 @llvm.powi.f80.i32(x86_fp80 0xK3FFF8000000000000000, i32 -64) ; <x86_fp80> [#uses=1]
   %conv = fptosi x86_fp80 %tmp to i32             ; <i32> [#uses=1]
   store i32 %conv, i32* %r
   %tmp1 = load i32, i32* %r                            ; <i32> [#uses=1]
   %tobool = icmp ne i32 %tmp1, 0                  ; <i1> [#uses=1]
   br i1 %tobool, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @_Z1fv()
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   %0 = load i32, i32* %retval                          ; <i32> [#uses=1]
   ret i32 %0
 }
 
-declare x86_fp80 @llvm.powi.f80(x86_fp80, i32) nounwind readonly
+declare x86_fp80 @llvm.powi.f80.i32(x86_fp80, i32) nounwind readonly
 
 declare void @_Z1fv()

llvm/test/CodeGen/X86/powi-windows.ll

 ; RUN: llc -mtriple x86_64-windows < %s | FileCheck %s
 
-declare double @llvm.powi.f64(double, i32)
-declare float @llvm.powi.f32(float, i32)
+declare double @llvm.powi.f64.i32(double, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define double @d(double %d, i32 %i) {
 entry:
-  %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   ret double %0
 }
 
 ; CHECK-LABEL: d:
 ; CHECK: cvtsi2sd %edx, %xmm1
 ; CHECK-NEXT: jmp pow
 
 define float @f(float %f, i32 %i) {
 entry:
-  %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   ret float %0
 }
 
 ; CHECK-LABEL: f:
 ; CHECK: cvtsi2ss %edx, %xmm1
 ; CHECK-NEXT: jmp powf
 
 define float @g(double %d, i32 %i) {
 entry:
-  %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
+  %0 = tail call double @llvm.powi.f64.i32(double %d, i32 %i)
   %conv = fptrunc double %0 to float
   ret float %conv
 }
 
 ; CHECK-LABEL: g:
 ; CHECK: cvtsi2sd %edx, %xmm1
 ; CHECK-NEXT: callq pow
 
 define double @h(float %f, i32 %i) {
 entry:
-  %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
+  %0 = tail call float @llvm.powi.f32.i32(float %f, i32 %i)
   %conv = fpext float %0 to double
   ret double %conv
 }
 
 ; CHECK-LABEL: h:
 ; CHECK: cvtsi2ss %edx, %xmm1
 ; CHECK-NEXT: callq powf

llvm/test/CodeGen/X86/powi.ll

 ; X64-NEXT:    mulsd %xmm0, %xmm1
 ; X64-NEXT:    mulsd %xmm1, %xmm0
 ; X64-NEXT:    mulsd %xmm1, %xmm1
 ; X64-NEXT:    mulsd %xmm1, %xmm0
 ; X64-NEXT:    mulsd %xmm1, %xmm1
 ; X64-NEXT:    mulsd %xmm0, %xmm1
 ; X64-NEXT:    movapd %xmm1, %xmm0
 ; X64-NEXT:    retq
-  %ret = tail call double @llvm.powi.f64(double %a, i32 15) nounwind ; <double> [#uses=1]
+  %ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
   ret double %ret
 }
 
 define double @pow_wrapper_optsize(double %a) optsize {
 ; X86-X87-LABEL: pow_wrapper_optsize:
 ; X86-X87:       # %bb.0:
 ; X86-X87-NEXT:    subl $12, %esp
 ; X86-X87-NEXT:    .cfi_def_cfa_offset 16

 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; X64-LABEL: pow_wrapper_optsize:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl $15, %edi
 ; X64-NEXT:    jmp __powidf2@PLT # TAILCALL
-  %ret = tail call double @llvm.powi.f64(double %a, i32 15) nounwind ; <double> [#uses=1]
+  %ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
   ret double %ret
 }
 
 define double @pow_wrapper_pgso(double %a) !prof !14 {
 ; X86-X87-LABEL: pow_wrapper_pgso:
 ; X86-X87:       # %bb.0:
 ; X86-X87-NEXT:    subl $12, %esp
 ; X86-X87-NEXT:    .cfi_def_cfa_offset 16

 ; X86-SSE-NEXT:    addl $12, %esp
 ; X86-SSE-NEXT:    .cfi_def_cfa_offset 4
 ; X86-SSE-NEXT:    retl
 ;
 ; X64-LABEL: pow_wrapper_pgso:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl $15, %edi
 ; X64-NEXT:    jmp __powidf2@PLT # TAILCALL
-  %ret = tail call double @llvm.powi.f64(double %a, i32 15) nounwind ; <double> [#uses=1]
+  %ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
   ret double %ret
 }
 
 define double @pow_wrapper_minsize(double %a) minsize {
 ; X86-X87-LABEL: pow_wrapper_minsize:
 ; X86-X87:       # %bb.0:
 ; X86-X87-NEXT:    subl $12, %esp
 ; X86-X87-NEXT:    .cfi_def_cfa_offset 16

 ;
 ; X64-LABEL: pow_wrapper_minsize:
 ; X64:       # %bb.0:
 ; X64-NEXT:    pushq $15
 ; X64-NEXT:    .cfi_adjust_cfa_offset 8
 ; X64-NEXT:    popq %rdi
 ; X64-NEXT:    .cfi_adjust_cfa_offset -8
 ; X64-NEXT:    jmp __powidf2@PLT # TAILCALL
-  %ret = tail call double @llvm.powi.f64(double %a, i32 15) nounwind ; <double> [#uses=1]
+  %ret = tail call double @llvm.powi.f64.i32(double %a, i32 15) nounwind ; <double> [#uses=1]
   ret double %ret
 }
 
-declare double @llvm.powi.f64(double, i32) nounwind readonly
+declare double @llvm.powi.f64.i32(double, i32) nounwind readonly
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 1, !"ProfileSummary", !1}
 !1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
 !2 = !{!"ProfileFormat", !"InstrProf"}
 !3 = !{!"TotalCount", i64 10000}
 !4 = !{!"MaxCount", i64 10}
 !5 = !{!"MaxInternalCount", i64 1}

llvm/test/CodeGen/X86/tailcall-multiret.ll

 ; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core2 | FileCheck %s
 ; See PR19530
-declare double    @llvm.powi.f64(double %Val, i32 %power)
+declare double    @llvm.powi.f64.i32(double %Val, i32 %power)
 define <3 x double> @julia_foo17589(i32 %arg) {
-  %tmp1 = call double @llvm.powi.f64(double 1.000000e+00, i32 %arg)
+  %tmp1 = call double @llvm.powi.f64.i32(double 1.000000e+00, i32 %arg)
 ; CHECK: callq   __powidf2
   %tmp2 = insertelement <3 x double> undef, double %tmp1, i32 0
-  %tmp3 = call double @llvm.powi.f64(double 2.000000e+00, i32 %arg)
+  %tmp3 = call double @llvm.powi.f64.i32(double 2.000000e+00, i32 %arg)
 ; CHECK: callq   __powidf2
   %tmp4 = insertelement <3 x double> %tmp2, double %tmp3, i32 1
-  %tmp5 = call double @llvm.powi.f64(double 3.000000e+00, i32 %arg)
+  %tmp5 = call double @llvm.powi.f64.i32(double 3.000000e+00, i32 %arg)
 ; CHECK: callq   __powidf2
   %tmp6 = insertelement <3 x double> %tmp4, double %tmp5, i32 2
 ; CHECK-NOT: TAILCALL
   ret <3 x double> %tmp6
 }

llvm/test/CodeGen/X86/vector-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
 declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
 declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
-declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
+declare <4 x double> @llvm.powi.v4f64.i32(<4 x double> %p, i32)
 
 define <4 x double> @foo(<4 x double> %p)
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subq $56, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
 ; CHECK-NEXT:    movaps %xmm0, (%rsp) # 16-byte Spill

 ; CHECK-NEXT:    movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
 ; CHECK-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
 ; CHECK-NEXT:    addq $48, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
 {
-  %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
+  %t = call <4 x double> @llvm.powi.v4f64.i32(<4 x double> %p, i32 %q)
   ret <4 x double> %t
 }
 
 
 declare <9 x double> @llvm.exp.v9f64(<9 x double> %a)
 declare <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
-declare <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32)
+declare <9 x double> @llvm.powi.v9f64.i32(<9 x double> %a, i32)
 
 define void @a(<9 x double>* %p) nounwind {
 ; CHECK-LABEL: a:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    pushq %rbx
 ; CHECK-NEXT:    subq $96, %rsp
 ; CHECK-NEXT:    movq %rdi, %rbx
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero

 ; CHECK-NEXT:    movaps %xmm0, 32(%rbx)
 ; CHECK-NEXT:    movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
 ; CHECK-NEXT:    movaps %xmm0, 48(%rbx)
 ; CHECK-NEXT:    addq $104, %rsp
 ; CHECK-NEXT:    popq %rbx
 ; CHECK-NEXT:    popq %rbp
 ; CHECK-NEXT:    retq
   %a = load <9 x double>, <9 x double>* %p
-  %r = call <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32 %n)
+  %r = call <9 x double> @llvm.powi.v9f64.i32(<9 x double> %a, i32 %n)
   store <9 x double> %r, <9 x double>* %p
   ret void
 }

llvm/test/CodeGen/XCore/float-intrinsics.ll

 ; RUN: llc < %s -march=xcore | FileCheck %s
 declare double @llvm.cos.f64(double)
 declare double @llvm.exp.f64(double)
 declare double @llvm.exp2.f64(double)
 declare double @llvm.log.f64(double)
 declare double @llvm.log10.f64(double)
 declare double @llvm.log2.f64(double)
 declare double @llvm.pow.f64(double, double)
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 declare double @llvm.sin.f64(double)
 declare double @llvm.sqrt.f64(double)
 
 define double @cos(double %F) {
 ; CHECK-LABEL: cos:
 ; CHECK: bl cos
         %result = call double @llvm.cos.f64(double %F)
   ret double %result

 ; CHECK: bl powf
         %result = call float @llvm.pow.f32(float %F, float %power)
   ret float %result
 }
 
 define double @powi(double %F, i32 %power) {
 ; CHECK-LABEL: powi:
 ; CHECK: bl __powidf2
-        %result = call double @llvm.powi.f64(double %F, i32 %power)
+        %result = call double @llvm.powi.f64.i32(double %F, i32 %power)
   ret double %result
 }
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 
 define float @powif(float %F, i32 %power) {
 ; CHECK-LABEL: powif:
 ; CHECK: bl __powisf2
-        %result = call float @llvm.powi.f32(float %F, i32 %power)
+        %result = call float @llvm.powi.f32.i32(float %F, i32 %power)
   ret float %result
 }
 
 define double @sin(double %F) {
 ; CHECK-LABEL: sin:
 ; CHECK: bl sin
         %result = call double @llvm.sin.f64(double %F)
   ret double %result

llvm/test/Transforms/InstCombine/fdiv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
 declare float @llvm.fabs.f32(float) nounwind readnone
 declare float @llvm.pow.f32(float, float) nounwind readnone
 declare <2 x half> @llvm.pow.v2f16(<2 x half>, <2 x half>) nounwind readnone
 declare float @llvm.exp.f32(float) nounwind readnone
 declare <2 x half> @llvm.exp.v2f16(<2 x half>) nounwind readnone
 declare float @llvm.exp2.f32(float) nounwind readnone
 declare <2 x half> @llvm.exp2.v2f16(<2 x half>) nounwind readnone
-declare float @llvm.powi.f32(float, i32) nounwind readnone
-declare <2 x half> @llvm.powi.v2f16(<2 x half>, i32) nounwind readnone
+declare float @llvm.powi.f32.i32(float, i32) nounwind readnone
+declare <2 x half> @llvm.powi.v2f16.i32(<2 x half>, i32) nounwind readnone
 
 define float @exact_inverse(float %x) {
 ; CHECK-LABEL: @exact_inverse(
 ; CHECK-NEXT:    [[DIV:%.*]] = fmul float [[X:%.*]], 1.250000e-01
 ; CHECK-NEXT:    ret float [[DIV]]
 ;
   %div = fdiv float %x, 8.0
   ret float %div
;
   %p = call <2 x half> @llvm.exp2.v2f16(<2 x half> %y)
   %r = fdiv reassoc arcp ninf <2 x half> <half 1.0, half 1.0>, %p
   ret <2 x half> %r
 }
 
 define float @powi_divisor(float %x, i32 %y, float %z) {
 ; CHECK-LABEL: @powi_divisor(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = call reassoc ninf arcp float @llvm.powi.f32(float [[X:%.*]], i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call reassoc ninf arcp float @llvm.powi.f32.i32(float [[X:%.*]], i32 [[TMP1]])
 ; CHECK-NEXT:    [[R:%.*]] = fmul reassoc ninf arcp float [[TMP2]], [[Z:%.*]]
 ; CHECK-NEXT:    ret float [[R]]
 ;
-  %p = call float @llvm.powi.f32(float %x, i32 %y)
+  %p = call float @llvm.powi.f32.i32(float %x, i32 %y)
   %r = fdiv reassoc arcp ninf float %z, %p
   ret float %r
 }
 
 ; Negative test - don't create an extra pow
 
 define float @powi_divisor_extra_use(float %x, i32 %y, float %z) {
 ; CHECK-LABEL: @powi_divisor_extra_use(
-; CHECK-NEXT:    [[P:%.*]] = call float @llvm.powi.f32(float [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT:    [[P:%.*]] = call float @llvm.powi.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
 ; CHECK-NEXT:    call void @use_f32(float [[P]])
 ; CHECK-NEXT:    [[R:%.*]] = fdiv reassoc ninf arcp float [[Z:%.*]], [[P]]
 ; CHECK-NEXT:    ret float [[R]]
 ;
-  %p = call float @llvm.powi.f32(float %x, i32 %y)
+  %p = call float @llvm.powi.f32.i32(float %x, i32 %y)
   call void @use_f32(float %p)
   %r = fdiv reassoc arcp ninf float %z, %p
   ret float %r
 }
 
 ; Negative test - must have reassoc+arcp+ninf
 
 define float @powi_divisor_not_enough_fmf(float %x, i32 %y, float %z) {
 ; CHECK-LABEL: @powi_divisor_not_enough_fmf(
-; CHECK-NEXT:    [[P:%.*]] = call fast float @llvm.powi.f32(float [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT:    [[P:%.*]] = call fast float @llvm.powi.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
 ; CHECK-NEXT:    [[R:%.*]] = fdiv reassoc ninf float [[Z:%.*]], [[P]]
 ; CHECK-NEXT:    ret float [[R]]
 ;
-  %p = call fast float @llvm.powi.f32(float %x, i32 %y)
+  %p = call fast float @llvm.powi.f32.i32(float %x, i32 %y)
   %r = fdiv reassoc ninf float %z, %p
   ret float %r
 }
 
 ; Negative test - must have reassoc+arcp+ninf
 
 define float @powi_divisor_not_enough_fmf2(float %x, i32 %y, float %z) {
 ; CHECK-LABEL: @powi_divisor_not_enough_fmf2(
-; CHECK-NEXT:    [[P:%.*]] = call fast float @llvm.powi.f32(float [[X:%.*]], i32 [[Y:%.*]])
+; CHECK-NEXT:    [[P:%.*]] = call fast float @llvm.powi.f32.i32(float [[X:%.*]], i32 [[Y:%.*]])
 ; CHECK-NEXT:    [[R:%.*]] = fdiv ninf arcp float [[Z:%.*]], [[P]]
 ; CHECK-NEXT:    ret float [[R]]
 ;
-  %p = call fast float @llvm.powi.f32(float %x, i32 %y)
+  %p = call fast float @llvm.powi.f32.i32(float %x, i32 %y)
   %r = fdiv arcp ninf float %z, %p
   ret float %r
 }
 
 ; Special-case - reciprocal does not require extra fmul
 
 define <2 x half> @powi_recip(<2 x half> %x, i32 %y) {
 ; CHECK-LABEL: @powi_recip(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[Y:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = call reassoc nnan ninf arcp <2 x half> @llvm.powi.v2f16(<2 x half> [[X:%.*]], i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call reassoc nnan ninf arcp <2 x half> @llvm.powi.v2f16.i32(<2 x half> [[X:%.*]], i32 [[TMP1]])
 ; CHECK-NEXT:    ret <2 x half> [[TMP2]]
 ;
-  %p = call <2 x half> @llvm.powi.v2f16(<2 x half> %x, i32 %y)
+  %p = call <2 x half> @llvm.powi.v2f16.i32(<2 x half> %x, i32 %y)
   %r = fdiv reassoc arcp nnan ninf <2 x half> <half 1.0, half 1.0>, %p
   ret <2 x half> %r
 }

llvm/test/Transforms/InstCombine/intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function powi
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
-declare double @llvm.powi.f64(double, i32) nounwind readonly
+declare double @llvm.powi.f64.i16(double, i16) nounwind readonly
+declare double @llvm.powi.f64.i32(double, i32) nounwind readonly
 declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
 declare i1 @llvm.cttz.i1(i1, i1) nounwind readnone
 declare i1 @llvm.ctlz.i1(i1, i1) nounwind readnone
 declare i32 @llvm.ctpop.i32(i32) nounwind readnone
 declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone
 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
 declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
 declare <2 x i8> @llvm.ctlz.v2i8(<2 x i8>, i1) nounwind readnone
 declare double @llvm.cos.f64(double %Val) nounwind readonly
 declare double @llvm.sin.f64(double %Val) nounwind readonly
 declare double @llvm.floor.f64(double %Val) nounwind readonly
 declare double @llvm.ceil.f64(double %Val) nounwind readonly
 declare double @llvm.trunc.f64(double %Val) nounwind readonly
 declare double @llvm.rint.f64(double %Val) nounwind readonly
 declare double @llvm.nearbyint.f64(double %Val) nounwind readonly
 
 define void @powi(double %V, double *%P) {
 ; CHECK-LABEL: @powi(
 ; CHECK-NEXT:    [[A:%.*]] = fdiv fast double 1.000000e+00, [[V:%.*]]
 ; CHECK-NEXT:    store volatile double [[A]], double* [[P:%.*]], align 8
 ; CHECK-NEXT:    [[D:%.*]] = fmul nnan double [[V]], [[V]]
 ; CHECK-NEXT:    store volatile double [[D]], double* [[P]], align 8
+; CHECK-NEXT:    [[A2:%.*]] = fdiv fast double 1.000000e+00, [[V]]
+; CHECK-NEXT:    store volatile double [[A2]], double* [[P]], align 8
+; CHECK-NEXT:    [[D2:%.*]] = fmul nnan double [[V]], [[V]]
+; CHECK-NEXT:    store volatile double [[D2]], double* [[P]], align 8
 ; CHECK-NEXT:    ret void
 ;
-  %A = tail call fast double @llvm.powi.f64(double %V, i32 -1) nounwind
+  %A = tail call fast double @llvm.powi.f64.i32(double %V, i32 -1) nounwind
   store volatile double %A, double* %P
 
-  %D = tail call nnan double @llvm.powi.f64(double %V, i32 2) nounwind
+  %D = tail call nnan double @llvm.powi.f64.i32(double %V, i32 2) nounwind
   store volatile double %D, double* %P
+
+  %A2 = tail call fast double @llvm.powi.f64.i16(double %V, i16 -1) nounwind
+  store volatile double %A2, double* %P
+
+  %D2 = tail call nnan double @llvm.powi.f64.i16(double %V, i16 2) nounwind
+  store volatile double %D2, double* %P
   ret void
 }
 
 define i32 @cttz(i32 %a) {
 ; CHECK-LABEL: @cttz(
 ; CHECK-NEXT:    ret i32 3
 ;
   %or = or i32 %a, 8

llvm/test/Transforms/InstCombine/pow-4.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -instcombine -S < %s                        | FileCheck %s --check-prefixes=CHECK,SQRT
-; RUN: opt -instcombine -S < %s -disable-builtin sqrt  | FileCheck %s --check-prefixes=CHECK,NOSQRT
+; RUN: opt -instcombine -S < %s -mtriple unknown                        | FileCheck %s --check-prefixes=CHECK,CHECKI32,SQRT
+; RUN: opt -instcombine -S < %s -mtriple unknown -disable-builtin sqrt  | FileCheck %s --check-prefixes=CHECK,CHECKI32,NOSQRT
+; RUN: opt -instcombine -S < %s -mtriple msp430                        | FileCheck %s --check-prefixes=CHECK,CHECKI16,SQRT
+; RUN: opt -instcombine -S < %s -mtriple msp430 -disable-builtin sqrt  | FileCheck %s --check-prefixes=CHECK,CHECKI16,NOSQRT
+
 declare double @llvm.pow.f64(double, double)
 declare float @llvm.pow.f32(float, float)
 declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
 declare <2 x float> @llvm.pow.v2f32(<2 x float>, <2 x float>)
 declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
 declare double @pow(double, double)
 
 ; pow(x, 3.0)

 ; CHECK-NEXT:    ret float [[TMP4]]
 ;
   %1 = call fast float @llvm.pow.f32(float %x, float 3.200000e+01)
   ret float %1
 }
 
 ; pow(x, 33.0)
 define double @test_simplify_33(double %x) {
-; CHECK-LABEL: @test_simplify_33(
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64(double [[X:%.*]], i32 33)
-; CHECK-NEXT:    ret double [[TMP1]]
+; CHECKI32-LABEL: @test_simplify_33(
+; CHECKI32-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64.i32(double [[X:%.*]], i32 33)
+; CHECKI32-NEXT:    ret double [[TMP1]]
+;
+; CHECKI16-LABEL: @test_simplify_33(
+; CHECKI16-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64.i16(double [[X:%.*]], i16 33)
+; CHECKI16-NEXT:    ret double [[TMP1]]
 ;
   %1 = call fast double @llvm.pow.f64(double %x, double 3.300000e+01)
   ret double %1
 }
 
 ; pow(x, 16.5) with double
 define double @test_simplify_16_5(double %x) {
 ; CHECK-LABEL: @test_simplify_16_5(

 ; CHECK-NEXT:    ret <4 x float> [[TMP2]]
 ;
   %1 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 3.500000e+00, float 3.500000e+00, float 3.500000e+00, float 3.500000e+00>)
   ret <4 x float> %1
 }
 
 ; (float)pow((double)(float)x, 0.5)
 define float @shrink_pow_libcall_half(float %x) {
-; SQRT-LABEL: @shrink_pow_libcall_half(
-; SQRT-NEXT:    [[SQRTF:%.*]] = call fast float @sqrtf(float [[X]])
-; SQRT-NEXT:    ret float [[SQRTF]]
-;
-; NOSQRT-LABEL: @shrink_pow_libcall_half(
-; NOSQRT-NEXT:    [[SQRTF:%.*]] = call fast float @sqrtf(float [[X:%.*]])
-; NOSQRT-NEXT:    ret float [[SQRTF]]
+; CHECK-LABEL: @shrink_pow_libcall_half(
+; CHECK-NEXT:    [[SQRTF:%.*]] = call fast float @sqrtf(float [[X:%.*]])
+; CHECK-NEXT:    ret float [[SQRTF]]
 ;
   %dx = fpext float %x to double
   %call = call fast double @pow(double %dx, double 0.5)
   %fr = fptrunc double %call to float
   ret float %fr
 }
 
 ; Make sure that -0.0 exponent is always simplified.

llvm/test/Transforms/InstCombine/pow_fp_int.ll

-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -mtriple unknown -instcombine -S < %s | FileCheck %s
 
 ; PR42190
+; Can't generate test checks due to PR42740.
 
 define double @pow_sitofp_const_base_fast(i32 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32.i32(float 7.000000e+00, i32 [[X:%.*]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP1]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = sitofp i32 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_const_base_fast(i31 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i32(float 7.000000e+00, i32 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i31 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_sitofp_double_const_base_fast(i32 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_const_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64(double 7.000000e+00, i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64.i32(double 7.000000e+00, i32 [[X:%.*]])
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
   %subfp = sitofp i32 %x to double
   %pow = tail call afn double @llvm.pow.f64(double 7.000000e+00, double %subfp)
   ret double %pow
 }
 
 define double @pow_uitofp_double_const_base_fast(i31 %x) {
 ; CHECK-LABEL: @pow_uitofp_double_const_base_fast(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64(double 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64.i32(double 7.000000e+00, i32 [[TMP1]])
 ; CHECK-NEXT:    ret double [[TMP2]]
 ;
   %subfp = uitofp i31 %x to double
   %pow = tail call afn double @llvm.pow.f64(double 7.000000e+00, double %subfp)
   ret double %pow
 }
 
 define double @pow_sitofp_double_const_base_2_fast(i32 %x) {
;
   %subfp = uitofp i31 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_sitofp_float_base_fast(float %base, i32 %x) {
 ; CHECK-LABEL: @pow_sitofp_float_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32(float [[BASE:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32.i32(float [[BASE:%.*]], i32 [[X:%.*]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP1]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = sitofp i32 %x to float
   %pow = tail call afn float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_float_base_fast(float %base, i31 %x) {
 ; CHECK-LABEL: @pow_uitofp_float_base_fast(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float [[BASE:%.*]], i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i32(float [[BASE:%.*]], i32 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i31 %x to float
   %pow = tail call afn float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_sitofp_double_base_fast(double %base, i32 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64(double [[BASE:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64.i32(double [[BASE:%.*]], i32 [[X:%.*]])
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
   %subfp = sitofp i32 %x to double
   %res = tail call afn double @llvm.pow.f64(double %base, double %subfp)
   ret double %res
 }
 
 define double @pow_uitofp_double_base_fast(double %base, i31 %x) {
 ; CHECK-LABEL: @pow_uitofp_double_base_fast(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64(double [[BASE:%.*]], i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64.i32(double [[BASE:%.*]], i32 [[TMP1]])
 ; CHECK-NEXT:    ret double [[TMP2]]
 ;
   %subfp = uitofp i31 %x to double
   %res = tail call afn double @llvm.pow.f64(double %base, double %subfp)
   ret double %res
 }
 
 define double @pow_sitofp_const_base_fast_i8(i8 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast_i8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i32(float 7.000000e+00, i32 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = sitofp i8 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_sitofp_const_base_fast_i16(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast_i16(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i32(float 7.000000e+00, i32 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = sitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 
 define double @pow_uitofp_const_base_fast_i8(i8 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast_i8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i32(float 7.000000e+00, i32 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i8 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_const_base_fast_i16(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast_i16(
 ; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i32(float 7.000000e+00, i32 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @powf_exp_const_int_fast(double %base) {
 ; CHECK-LABEL: @powf_exp_const_int_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64(double [[BASE:%.*]], i32 40)
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64.i32(double [[BASE:%.*]], i32 40)
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
   %res = tail call fast double @llvm.pow.f64(double %base, double 4.000000e+01)
   ret double %res
 }
 
 define double @powf_exp_const2_int_fast(double %base) {
 ; CHECK-LABEL: @powf_exp_const2_int_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64(double [[BASE:%.*]], i32 -40)
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64.i32(double [[BASE:%.*]], i32 -40)
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
   %res = tail call fast double @llvm.pow.f64(double %base, double -4.000000e+01)
   ret double %res
 }
 
 ; Negative tests
 

llvm/test/Transforms/InstCombine/pow_fp_int16.ll

-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mtriple unknown -instcombine -S < %s | FileCheck %s
+; RUN: opt -mtriple msp430 -instcombine -S < %s | FileCheck %s
 
-; PR42190
+; Test case was copied from pow_fp_int.ll but adjusted for 16-bit int.
+; Assuming that we can't generate test checks for the same reason (PR42740).
 
-define double @pow_sitofp_const_base_fast(i32 %x) {
+define double @pow_sitofp_const_base_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32.i16(float 7.000000e+00, i16 [[X:%.*]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP1]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_fast(i31 %x) {
+define double @pow_uitofp_const_base_fast(i15 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i15 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i16(float 7.000000e+00, i16 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i31 %x to float
+  %subfp = uitofp i15 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_double_const_base_fast(i32 %x) {
+define double @pow_sitofp_double_const_base_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_const_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64(double 7.000000e+00, i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64.i16(double 7.000000e+00, i16 [[X:%.*]])
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
-  %subfp = sitofp i32 %x to double
+  %subfp = sitofp i16 %x to double
   %pow = tail call afn double @llvm.pow.f64(double 7.000000e+00, double %subfp)
   ret double %pow
 }
 
-define double @pow_uitofp_double_const_base_fast(i31 %x) {
+define double @pow_uitofp_double_const_base_fast(i15 %x) {
 ; CHECK-LABEL: @pow_uitofp_double_const_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64(double 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i15 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64.i16(double 7.000000e+00, i16 [[TMP1]])
 ; CHECK-NEXT:    ret double [[TMP2]]
 ;
-  %subfp = uitofp i31 %x to double
+  %subfp = uitofp i15 %x to double
   %pow = tail call afn double @llvm.pow.f64(double 7.000000e+00, double %subfp)
   ret double %pow
 }
 
-define double @pow_sitofp_double_const_base_2_fast(i32 %x) {
+define double @pow_sitofp_double_const_base_2_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_const_base_2_fast(
-; CHECK-NEXT:    [[LDEXPF:%.*]] = call afn float @ldexpf(float 1.000000e+00, i32 [[X:%.*]])
+; CHECK-NEXT:    [[LDEXPF:%.*]] = call afn float @ldexpf(float 1.000000e+00, i16 [[X:%.*]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[LDEXPF]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_double_const_base_power_of_2_fast(i32 %x) {
+define double @pow_sitofp_double_const_base_power_of_2_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_const_base_power_of_2_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul afn float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call afn float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_2_fast(i31 %x) {
+define double @pow_uitofp_const_base_2_fast(i15 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_2_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[LDEXPF:%.*]] = call afn float @ldexpf(float 1.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i15 [[X:%.*]] to i16
+; CHECK-NEXT:    [[LDEXPF:%.*]] = call afn float @ldexpf(float 1.000000e+00, i16 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[LDEXPF]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i31 %x to float
+  %subfp = uitofp i15 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_power_of_2_fast(i31 %x) {
+define double @pow_uitofp_const_base_power_of_2_fast(i15 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_power_of_2_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i31 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i15 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul afn float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call afn float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i31 %x to float
+  %subfp = uitofp i15 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_float_base_fast(float %base, i32 %x) {
+define double @pow_sitofp_float_base_fast(float %base, i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_float_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32(float [[BASE:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32.i16(float [[BASE:%.*]], i16 [[X:%.*]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP1]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_float_base_fast(float %base, i31 %x) {
+define double @pow_uitofp_float_base_fast(float %base, i15 %x) {
 ; CHECK-LABEL: @pow_uitofp_float_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float [[BASE:%.*]], i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i15 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i16(float [[BASE:%.*]], i16 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i31 %x to float
+  %subfp = uitofp i15 %x to float
   %pow = tail call afn float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_double_base_fast(double %base, i32 %x) {
+define double @pow_sitofp_double_base_fast(double %base, i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64(double [[BASE:%.*]], i32 [[X:%.*]])
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn double @llvm.powi.f64.i16(double [[BASE:%.*]], i16 [[X:%.*]])
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
-  %subfp = sitofp i32 %x to double
+  %subfp = sitofp i16 %x to double
   %res = tail call afn double @llvm.pow.f64(double %base, double %subfp)
   ret double %res
 }
 
-define double @pow_uitofp_double_base_fast(double %base, i31 %x) {
+define double @pow_uitofp_double_base_fast(double %base, i15 %x) {
 ; CHECK-LABEL: @pow_uitofp_double_base_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i31 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64(double [[BASE:%.*]], i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i15 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn double @llvm.powi.f64.i16(double [[BASE:%.*]], i16 [[TMP1]])
 ; CHECK-NEXT:    ret double [[TMP2]]
 ;
-  %subfp = uitofp i31 %x to double
+  %subfp = uitofp i15 %x to double
   %res = tail call afn double @llvm.pow.f64(double %base, double %subfp)
   ret double %res
 }
 
 define double @pow_sitofp_const_base_fast_i8(i8 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast_i8(
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i16(float 7.000000e+00, i16 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = sitofp i8 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_sitofp_const_base_fast_i16(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast_i16(
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
-; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
+; CHECK-NEXT:    [[TMP1:%.*]] = call afn float @llvm.powi.f32.i16(float 7.000000e+00, i16 [[X:%.*]])
+; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP1]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = sitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 
 define double @pow_uitofp_const_base_fast_i8(i8 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast_i8(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32.i16(float 7.000000e+00, i16 [[TMP1]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i8 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_const_base_fast_i16(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast_i16(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = call afn float @llvm.powi.f32(float 7.000000e+00, i32 [[TMP1]])
-; CHECK-NEXT:    [[RES:%.*]] = fpext float [[TMP2]] to double
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
+; CHECK-NEXT:    [[POW:%.*]] = tail call afn float @llvm.pow.f32(float 7.000000e+00, float [[SUBFP]])
+; CHECK-NEXT:    [[RES:%.*]] = fpext float [[POW]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i16 %x to float
   %pow = tail call afn float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @powf_exp_const_int_fast(double %base) {
 ; CHECK-LABEL: @powf_exp_const_int_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64(double [[BASE:%.*]], i32 40)
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64.i16(double [[BASE:%.*]], i16 40)
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
   %res = tail call fast double @llvm.pow.f64(double %base, double 4.000000e+01)
   ret double %res
 }
 
 define double @powf_exp_const2_int_fast(double %base) {
 ; CHECK-LABEL: @powf_exp_const2_int_fast(
-; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64(double [[BASE:%.*]], i32 -40)
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast double @llvm.powi.f64.i16(double [[BASE:%.*]], i16 -40)
 ; CHECK-NEXT:    ret double [[TMP1]]
 ;
   %res = tail call fast double @llvm.pow.f64(double %base, double -4.000000e+01)
   ret double %res
 }
 
 ; Negative tests
 
-define double @pow_uitofp_const_base_fast_i32(i32 %x) {
+define double @pow_uitofp_const_base_fast_i32(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast_i32(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x4006757{{.*}}
 ; CHECK-NEXT:    [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call fast float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_2_fast_i32(i32 %x) {
+define double @pow_uitofp_const_base_2_fast_i32(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_2_fast_i32(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call fast float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_power_of_2_fast_i32(i32 %x) {
+define double @pow_uitofp_const_base_power_of_2_fast_i32(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_power_of_2_fast_i32(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul fast float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call fast float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_float_base_fast_i32(float %base, i32 %x) {
+define double @pow_uitofp_float_base_fast_i32(float %base, i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_float_base_fast_i32(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[POW:%.*]] = tail call fast float @llvm.pow.f32(float [[BASE:%.*]], float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[POW]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call fast float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_double_base_fast_i32(double %base, i32 %x) {
+define double @pow_uitofp_double_base_fast_i32(double %base, i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_double_base_fast_i32(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to double
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to double
 ; CHECK-NEXT:    [[RES:%.*]] = tail call fast double @llvm.pow.f64(double [[BASE:%.*]], double [[SUBFP]])
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to double
+  %subfp = uitofp i16 %x to double
   %res = tail call fast double @llvm.pow.f64(double %base, double %subfp)
   ret double %res
 }
 
 define double @pow_sitofp_const_base_fast_i64(i64 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_fast_i64(
 ; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i64 [[X:%.*]] to float
-; Do not change 0x400675{{.*}} to the exact constant, see PR42740
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x400675{{.*}}
 ; CHECK-NEXT:    [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
+; Do not change 0x400675{{.*}} to the exact constant, see PR42740
   %subfp = sitofp i64 %x to float
   %pow = tail call fast float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
 define double @pow_uitofp_const_base_fast_i64(i64 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_fast_i64(
 ; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i64 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul fast float [[SUBFP]], 0x400675{{.*}}
 ; CHECK-NEXT:    [[EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
   %subfp = uitofp i64 %x to float
   %pow = tail call fast float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_const_base_no_fast(i32 %x) {
+define double @pow_sitofp_const_base_no_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[POW:%.*]] = tail call float @llvm.pow.f32(float 7.000000e+00, float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[POW]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_no_fast(i32 %x) {
+define double @pow_uitofp_const_base_no_fast(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[POW:%.*]] = tail call float @llvm.pow.f32(float 7.000000e+00, float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[POW]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float 7.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_const_base_2_no_fast(i32 %x) {
+define double @pow_sitofp_const_base_2_no_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_2_no_fast(
-; CHECK-NEXT:    [[LDEXPF:%.*]] = call float @ldexpf(float 1.000000e+00, i32 [[X:%.*]])
+; CHECK-NEXT:    [[LDEXPF:%.*]] = call float @ldexpf(float 1.000000e+00, i16 [[X:%.*]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[LDEXPF]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_const_base_power_of_2_no_fast(i32 %x) {
+define double @pow_sitofp_const_base_power_of_2_no_fast(i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_const_base_power_of_2_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_2_no_fast(i32 %x) {
+define double @pow_uitofp_const_base_2_no_fast(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_2_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[EXP2:%.*]] = call float @llvm.exp2.f32(float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float 2.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_const_base_power_of_2_no_fast(i32 %x) {
+define double @pow_uitofp_const_base_power_of_2_no_fast(i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_const_base_power_of_2_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul float [[SUBFP]], 4.000000e+00
 ; CHECK-NEXT:    [[EXP2:%.*]] = call float @llvm.exp2.f32(float [[MUL]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[EXP2]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float 16.000000e+00, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_float_base_no_fast(float %base, i32 %x) {
+define double @pow_sitofp_float_base_no_fast(float %base, i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_float_base_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[POW:%.*]] = tail call float @llvm.pow.f32(float [[BASE:%.*]], float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[POW]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = sitofp i32 %x to float
+  %subfp = sitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_uitofp_float_base_no_fast(float %base, i32 %x) {
+define double @pow_uitofp_float_base_no_fast(float %base, i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_float_base_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to float
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to float
 ; CHECK-NEXT:    [[POW:%.*]] = tail call float @llvm.pow.f32(float [[BASE:%.*]], float [[SUBFP]])
 ; CHECK-NEXT:    [[RES:%.*]] = fpext float [[POW]] to double
 ; CHECK-NEXT:    ret double [[RES]]
 ;
-  %subfp = uitofp i32 %x to float
+  %subfp = uitofp i16 %x to float
   %pow = tail call float @llvm.pow.f32(float %base, float %subfp)
   %res = fpext float %pow to double
   ret double %res
 }
 
-define double @pow_sitofp_double_base_no_fast(double %base, i32 %x) {
+define double @pow_sitofp_double_base_no_fast(double %base, i16 %x) {
 ; CHECK-LABEL: @pow_sitofp_double_base_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i32 [[X:%.*]] to double
+; CHECK-NEXT:    [[SUBFP:%.*]] = sitofp i16 [[X:%.*]] to double
 ; CHECK-NEXT:    [[POW:%.*]] = tail call double @llvm.pow.f64(double [[BASE:%.*]], double [[SUBFP]])
 ; CHECK-NEXT:    ret double [[POW]]
 ;
-  %subfp = sitofp i32 %x to double
+  %subfp = sitofp i16 %x to double
   %pow = tail call double @llvm.pow.f64(double %base, double %subfp)
   ret double %pow
 }
 
-define double @pow_uitofp_double_base_no_fast(double %base, i32 %x) {
+define double @pow_uitofp_double_base_no_fast(double %base, i16 %x) {
 ; CHECK-LABEL: @pow_uitofp_double_base_no_fast(
-; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i32 [[X:%.*]] to double
+; CHECK-NEXT:    [[SUBFP:%.*]] = uitofp i16 [[X:%.*]] to double
 ; CHECK-NEXT:    [[POW:%.*]] = tail call double @llvm.pow.f64(double [[BASE:%.*]], double [[SUBFP]])
 ; CHECK-NEXT:    ret double [[POW]]
 ;
-  %subfp = uitofp i32 %x to double
+  %subfp = uitofp i16 %x to double
   %pow = tail call double @llvm.pow.f64(double %base, double %subfp)
   ret double %pow
 }
 
 define double @powf_exp_const_int_no_fast(double %base) {
 ; CHECK-LABEL: @powf_exp_const_int_no_fast(
 ; CHECK-NEXT:    [[RES:%.*]] = tail call double @llvm.pow.f64(double [[BASE:%.*]], double 4.000000e+01)
 ; CHECK-NEXT:    ret double [[RES]]

llvm/test/Transforms/InstSimplify/ConstProp/math-2.ll

 define float @i_powf() {
 ; CHECK-LABEL: @i_powf(
 ; CHECK-NEXT:    ret float 1.000000e+00
 ;
   %res = tail call fast float @llvm.pow.f32(float 1.0, float 2.0)
   ret float %res
 }
 
-declare double @llvm.powi.f64(double, i32)
+declare double @llvm.powi.f64.i32(double, i32)
 define double @i_powi() {
 ; CHECK-LABEL: @i_powi(
 ; CHECK-NEXT:    ret double 1.000000e+00
 ;
-  %res = tail call fast double @llvm.powi.f64(double 1.0, i32 2)
+  %res = tail call fast double @llvm.powi.f64.i32(double 1.0, i32 2)
   ret double %res
 }
 
 attributes #0 = { nofree nounwind willreturn }

llvm/test/Transforms/InstSimplify/call.ll

;
   %masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %V, i32 4, <8 x i1> undef, <8 x i32> <i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0>)
   ret <8 x i32> %masked.load
 }
 
 declare noalias i8* @malloc(i64)
 
 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)
 
-declare double @llvm.powi.f64(double, i32)
-declare <2 x double> @llvm.powi.v2f64(<2 x double>, i32)
+declare double @llvm.powi.f64.i16(double, i16)
+declare <2 x double> @llvm.powi.v2f64.i16(<2 x double>, i16)
+declare double @llvm.powi.f64.i32(double, i32)
+declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32)
 
 define double @constant_fold_powi() {
 ; CHECK-LABEL: @constant_fold_powi(
 ; CHECK-NEXT:    ret double 9.000000e+00
 ;
-  %t0 = call double @llvm.powi.f64(double 3.00000e+00, i32 2)
+  %t0 = call double @llvm.powi.f64.i32(double 3.00000e+00, i32 2)
+  ret double %t0
+}
+
+define double @constant_fold_powi_i16() {
+; CHECK-LABEL: @constant_fold_powi_i16(
+; CHECK-NEXT:    ret double 9.000000e+00
+;
+  %t0 = call double @llvm.powi.f64.i16(double 3.00000e+00, i16 2)
   ret double %t0
 }
 
 define <2 x double> @constant_fold_powi_vec() {
 ; CHECK-LABEL: @constant_fold_powi_vec(
 ; CHECK-NEXT:    ret <2 x double> <double 9.000000e+00, double 2.500000e+01>
 ;
-  %t0 = call <2 x double> @llvm.powi.v2f64(<2 x double> <double 3.00000e+00, double 5.00000e+00>, i32 2)
+  %t0 = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> <double 3.00000e+00, double 5.00000e+00>, i32 2)
+  ret <2 x double> %t0
+}
+
+define <2 x double> @constant_fold_powi_vec_i16() {
+; CHECK-LABEL: @constant_fold_powi_vec_i16(
+; CHECK-NEXT:    ret <2 x double> <double 9.000000e+00, double 2.500000e+01>
+;
+  %t0 = call <2 x double> @llvm.powi.v2f64.i16(<2 x double> <double 3.00000e+00, double 5.00000e+00>, i16 2)
   ret <2 x double> %t0
 }
 
 declare i8 @llvm.fshl.i8(i8, i8, i8)
 declare i9 @llvm.fshr.i9(i9, i9, i9)
 declare <2 x i7> @llvm.fshl.v2i7(<2 x i7>, <2 x i7>, <2 x i7>)
 declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>)
 

llvm/test/Transforms/InstSimplify/floating-point-compare.ll

 
 declare half @llvm.fabs.f16(half)
 declare float @llvm.fabs.f32(float)
 declare double @llvm.fabs.f64(double)
 declare <2 x float> @llvm.fabs.v2f32(<2 x float>)
 declare <3 x float> @llvm.fabs.v3f32(<3 x float>)
 declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
 declare float @llvm.sqrt.f32(float)
-declare double @llvm.powi.f64(double,i32)
+declare double @llvm.powi.f64.i32(double,i32)
 declare float @llvm.exp.f32(float)
 declare float @llvm.minnum.f32(float, float)
 declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
 declare float @llvm.maxnum.f32(float, float)
 declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
 declare float @llvm.maximum.f32(float, float)
 declare double @llvm.exp2.f64(double)
 declare float @llvm.fma.f32(float,float,float)
;
   ret i1 %olt
 }
 
 define i1 @orderedLessZeroPowi(double,double) {
 ; CHECK-LABEL: @orderedLessZeroPowi(
 ; CHECK-NEXT:    ret i1 false
 ;
   ; Even constant exponent
-  %a = call double @llvm.powi.f64(double %0, i32 2)
+  %a = call double @llvm.powi.f64.i32(double %0, i32 2)
   %square = fmul double %1, %1
   ; Odd constant exponent with provably non-negative base
-  %b = call double @llvm.powi.f64(double %square, i32 3)
+  %b = call double @llvm.powi.f64.i32(double %square, i32 3)
   %c = fadd double %a, %b
   %olt = fcmp olt double %b, 0.000000e+00
   ret i1 %olt
 }
 
 define i1 @UIToFP_is_nan_or_positive_or_zero(i32 %x) {
 ; CHECK-LABEL: @UIToFP_is_nan_or_positive_or_zero(
 ; CHECK-NEXT:    ret i1 true

llvm/test/Transforms/InstSimplify/fold-intrinsics.ll

 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
-declare double @llvm.powi.f64(double, i32) nounwind readonly
+declare float @llvm.powi.f32.i16(float, i16) nounwind readonly
+declare double @llvm.powi.f64.i32(double, i32) nounwind readonly
 declare i32 @llvm.bswap.i32(i32)
 
 ; A
 define i32 @test_bswap(i32 %a) nounwind {
 ; CHECK-LABEL: @test_bswap(
 ; CHECK-NEXT:    ret i32 %a
 ;
   %tmp2 = tail call i32 @llvm.bswap.i32( i32 %a )
   %tmp4 = tail call i32 @llvm.bswap.i32( i32 %tmp2 )
   ret i32 %tmp4
 }
 
 define void @powi(double %V, double *%P) {
-  %B = tail call double @llvm.powi.f64(double %V, i32 0) nounwind
+  %B = tail call double @llvm.powi.f64.i32(double %V, i32 0) nounwind
   store volatile double %B, double* %P
 
-  %C = tail call double @llvm.powi.f64(double %V, i32 1) nounwind
+  %C = tail call double @llvm.powi.f64.i32(double %V, i32 1) nounwind
   store volatile double %C, double* %P
 
   ret void
 ; CHECK-LABEL: @powi(
 ; CHECK: store volatile double 1.0
 ; CHECK: store volatile double %V
 }
+
+define void @powi_i16(float %V, float *%P) {
+  %B = tail call float @llvm.powi.f32.i16(float %V, i16 0) nounwind
+  store volatile float %B, float* %P
+
+  %C = tail call float @llvm.powi.f32.i16(float %V, i16 1) nounwind
+  store volatile float %C, float* %P
+
+  ret void
+; CHECK-LABEL: @powi_i16(
+; CHECK: store volatile float 1.0
+; CHECK: store volatile float %V
+}

llvm/test/Transforms/LICM/hoist-round.ll

for.body:
   %tmp.5 = call float @llvm.round.f32(float %tmp.4)
   %tmp.6 = call float @llvm.trunc.f32(float %tmp.5)
   %tmp.7 = call float @llvm.fabs.f32(float %tmp.6)
   %tmp.8 = call float @llvm.copysign.f32(float %tmp.7, float %arg2)
   %tmp.9 = call float @llvm.minnum.f32(float %tmp.8, float %arg2)
   %tmp.10 = call float @llvm.maxnum.f32(float %tmp.9, float %arg2)
   %tmp.11 = call float @llvm.minimum.f32(float %tmp.10, float %arg2)
   %tmp.12 = call float @llvm.maximum.f32(float %tmp.11, float %arg2)
-  %tmp.13 = call float @llvm.powi.f32(float %tmp.12, i32 4)
+  %tmp.13 = call float @llvm.powi.f32.i32(float %tmp.12, i32 4)
   %tmp.14 = call float @llvm.roundeven.f32(float %tmp.13)
   call void @consume(float %tmp.14)
   %IND.new = add i32 %IND, 1
   br label %for.head
 
 exit:
   ret void
 }
 
 declare void @consume(float)
 
 declare float @llvm.ceil.f32(float)
 declare float @llvm.floor.f32(float)
 declare float @llvm.nearbyint.f32(float)
 declare float @llvm.rint.f32(float)
 declare float @llvm.round.f32(float)
 declare float @llvm.trunc.f32(float)
 declare float @llvm.fabs.f32(float)
 declare float @llvm.copysign.f32(float, float)
 declare float @llvm.minnum.f32(float, float)
 declare float @llvm.maxnum.f32(float, float)
 declare float @llvm.minimum.f32(float, float)
 declare float @llvm.maximum.f32(float, float)
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 declare float @llvm.roundeven.f32(float)

llvm/test/Transforms/LoopVectorize/intrinsic.ll

for.body:                                         ; preds = %entry, %for.body
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, 1024
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body
   ret void
 }
 
-declare double @llvm.powi.f64(double %Val, i32 %power) nounwind readnone
+declare double @llvm.powi.f64.i32(double %Val, i32 %power) nounwind readnone
 
 ;CHECK-LABEL: @powi_f64(
 ;CHECK: llvm.powi.v4f64
 ;CHECK: ret void
 define void @powi_f64(i32 %n, double* noalias %y, double* noalias %x, i32 %P) nounwind uwtable {
 entry:
   %cmp9 = icmp sgt i32 %n, 0
   br i1 %cmp9, label %for.body, label %for.end
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
   %0 = load double, double* %arrayidx, align 8
-  %call = tail call double @llvm.powi.f64(double %0, i32  %P) nounwind readnone
+  %call = tail call double @llvm.powi.f64.i32(double %0, i32  %P) nounwind readnone
   %arrayidx4 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, %n
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
 ;CHECK-LABEL: @powi_f64_neg(
 ;CHECK-NOT: llvm.powi.v4f64
 ;CHECK: ret void
 define void @powi_f64_neg(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
 entry:
   %cmp9 = icmp sgt i32 %n, 0
   br i1 %cmp9, label %for.body, label %for.end
 
 for.body:                                         ; preds = %entry, %for.body
   %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
   %arrayidx = getelementptr inbounds double, double* %y, i64 %indvars.iv
   %0 = load double, double* %arrayidx, align 8
   %1 = trunc i64 %indvars.iv to i32
-  %call = tail call double @llvm.powi.f64(double %0, i32  %1) nounwind readnone
+  %call = tail call double @llvm.powi.f64.i32(double %0, i32  %1) nounwind readnone
   %arrayidx4 = getelementptr inbounds double, double* %x, i64 %indvars.iv
   store double %call, double* %arrayidx4, align 8
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, %n
   br i1 %exitcond, label %for.end, label %for.body
 
 for.end:                                          ; preds = %for.body, %entry

llvm/test/Transforms/SLPVectorizer/X86/extract_in_tree_user.ll

entry:
   %add.ptr1 = getelementptr inbounds i64, i64* %0, i64 56
   %2 = ptrtoint i64* %add.ptr1 to i64
   %arrayidx2 = getelementptr inbounds i64, i64* %0, i64 12
   store i64 %2, i64* %arrayidx2, align 8
   ret i32 undef
 }
 
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 define void @fn2(i32* %a, i32* %b, float* %c) {
 ; CHECK-LABEL: @fn2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 1
 ; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i32 1
 ; CHECK-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 2
 ; CHECK-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 2
 ; CHECK-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 3
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i32* [[A]] to <4 x i32>*
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32* [[B]] to <4 x i32>*
 ; CHECK-NEXT:    [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = sitofp <4 x i32> [[TMP4]] to <4 x float>
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0
-; CHECK-NEXT:    [[TMP7:%.*]] = call <4 x float> @llvm.powi.v4f32(<4 x float> [[TMP5]], i32 [[TMP6]])
+; CHECK-NEXT:    [[TMP7:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[TMP5]], i32 [[TMP6]])
 ; CHECK-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[C:%.*]], i32 1
 ; CHECK-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[C]], i32 2
 ; CHECK-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[C]], i32 3
 ; CHECK-NEXT:    [[TMP8:%.*]] = bitcast float* [[C]] to <4 x float>*
 ; CHECK-NEXT:    store <4 x float> [[TMP7]], <4 x float>* [[TMP8]], align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %i0 = load i32, i32* %a, align 4
   %i1 = load i32, i32* %b, align 4
   %add1 = add i32 %i0, %i1
   %fp1 = sitofp i32 %add1 to float
-  %call1 = tail call float @llvm.powi.f32(float %fp1,i32 %add1) nounwind readnone
+  %call1 = tail call float @llvm.powi.f32.i32(float %fp1,i32 %add1) nounwind readnone
 
   %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1
   %i2 = load i32, i32* %arrayidx2, align 4
   %arrayidx3 = getelementptr inbounds i32, i32* %b, i32 1
   %i3 = load i32, i32* %arrayidx3, align 4
   %add2 = add i32 %i2, %i3
   %fp2 = sitofp i32 %add2 to float
-  %call2 = tail call float @llvm.powi.f32(float %fp2,i32 %add1) nounwind readnone
+  %call2 = tail call float @llvm.powi.f32.i32(float %fp2,i32 %add1) nounwind readnone
 
   %arrayidx4 = getelementptr inbounds i32, i32* %a, i32 2
   %i4 = load i32, i32* %arrayidx4, align 4
   %arrayidx5 = getelementptr inbounds i32, i32* %b, i32 2
   %i5 = load i32, i32* %arrayidx5, align 4
   %add3 = add i32 %i4, %i5
   %fp3 = sitofp i32 %add3 to float
-  %call3 = tail call float @llvm.powi.f32(float %fp3,i32 %add1) nounwind readnone
+  %call3 = tail call float @llvm.powi.f32.i32(float %fp3,i32 %add1) nounwind readnone
 
   %arrayidx6 = getelementptr inbounds i32, i32* %a, i32 3
   %i6 = load i32, i32* %arrayidx6, align 4
   %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 3
   %i7 = load i32, i32* %arrayidx7, align 4
   %add4 = add i32 %i6, %i7
   %fp4 = sitofp i32 %add4 to float
-  %call4 = tail call float @llvm.powi.f32(float %fp4,i32 %add1) nounwind readnone
+  %call4 = tail call float @llvm.powi.f32.i32(float %fp4,i32 %add1) nounwind readnone
 
   store float %call1, float* %c, align 4
   %arrayidx8 = getelementptr inbounds float, float* %c, i32 1
   store float %call2, float* %arrayidx8, align 4
   %arrayidx9 = getelementptr inbounds float, float* %c, i32 2
   store float %call3, float* %arrayidx9, align 4
   %arrayidx10 = getelementptr inbounds float, float* %c, i32 3
   store float %call4, float* %arrayidx10, align 4
   ret void
 
 }

llvm/test/Transforms/SLPVectorizer/X86/intrinsic.ll

entry:
   store i32 %call3, i32* %arrayidx9, align 4
   %arrayidx10 = getelementptr inbounds i32, i32* %c, i32 3
   store i32 %call4, i32* %arrayidx10, align 4
   ret void
 
 }
 
 
-declare float @llvm.powi.f32(float, i32)
+declare float @llvm.powi.f32.i32(float, i32)
 define void @vec_powi_f32(float* %a, float* %b, float* %c, i32 %P) {
 ; CHECK-LABEL: @vec_powi_f32(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast float* [[A:%.*]] to <4 x float>*
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
 ; CHECK-NEXT:    [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = fadd <4 x float> [[TMP1]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = call <4 x float> @llvm.powi.v4f32(<4 x float> [[TMP4]], i32 [[P:%.*]])
+; CHECK-NEXT:    [[TMP5:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[TMP4]], i32 [[P:%.*]])
 ; CHECK-NEXT:    [[TMP6:%.*]] = bitcast float* [[C:%.*]] to <4 x float>*
 ; CHECK-NEXT:    store <4 x float> [[TMP5]], <4 x float>* [[TMP6]], align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %i0 = load float, float* %a, align 4
   %i1 = load float, float* %b, align 4
   %add1 = fadd float %i0, %i1
-  %call1 = tail call float @llvm.powi.f32(float %add1,i32 %P) nounwind readnone
+  %call1 = tail call float @llvm.powi.f32.i32(float %add1,i32 %P) nounwind readnone
 
   %arrayidx2 = getelementptr inbounds float, float* %a, i32 1
   %i2 = load float, float* %arrayidx2, align 4
   %arrayidx3 = getelementptr inbounds float, float* %b, i32 1
   %i3 = load float, float* %arrayidx3, align 4
   %add2 = fadd float %i2, %i3
-  %call2 = tail call float @llvm.powi.f32(float %add2,i32 %P) nounwind readnone
+  %call2 = tail call float @llvm.powi.f32.i32(float %add2,i32 %P) nounwind readnone
 
   %arrayidx4 = getelementptr inbounds float, float* %a, i32 2
   %i4 = load float, float* %arrayidx4, align 4
   %arrayidx5 = getelementptr inbounds float, float* %b, i32 2
   %i5 = load float, float* %arrayidx5, align 4
   %add3 = fadd float %i4, %i5
-  %call3 = tail call float @llvm.powi.f32(float %add3,i32 %P) nounwind readnone
+  %call3 = tail call float @llvm.powi.f32.i32(float %add3,i32 %P) nounwind readnone
 
   %arrayidx6 = getelementptr inbounds float, float* %a, i32 3
   %i6 = load float, float* %arrayidx6, align 4
   %arrayidx7 = getelementptr inbounds float, float* %b, i32 3
   %i7 = load float, float* %arrayidx7, align 4
   %add4 = fadd float %i6, %i7
-  %call4 = tail call float @llvm.powi.f32(float %add4,i32 %P) nounwind readnone
+  %call4 = tail call float @llvm.powi.f32.i32(float %add4,i32 %P) nounwind readnone
 
   store float %call1, float* %c, align 4
   %arrayidx8 = getelementptr inbounds float, float* %c, i32 1
   store float %call2, float* %arrayidx8, align 4
   %arrayidx9 = getelementptr inbounds float, float* %c, i32 2
   store float %call3, float* %arrayidx9, align 4
   %arrayidx10 = getelementptr inbounds float, float* %c, i32 3
   store float %call4, float* %arrayidx10, align 4
   ret void
 
 }
 
 
 define void @vec_powi_f32_neg(float* %a, float* %b, float* %c, i32 %P, i32 %Q) {
 ; CHECK-LABEL: @vec_powi_f32_neg(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[I0:%.*]] = load float, float* [[A:%.*]], align 4
 ; CHECK-NEXT:    [[I1:%.*]] = load float, float* [[B:%.*]], align 4
 ; CHECK-NEXT:    [[ADD1:%.*]] = fadd float [[I0]], [[I1]]
-; CHECK-NEXT:    [[CALL1:%.*]] = tail call float @llvm.powi.f32(float [[ADD1]], i32 [[P:%.*]]) #3
+; CHECK-NEXT:    [[CALL1:%.*]] = tail call float @llvm.powi.f32.i32(float [[ADD1]], i32 [[P:%.*]]) #3
 ; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[A]], i32 1
 ; CHECK-NEXT:    [[I2:%.*]] = load float, float* [[ARRAYIDX2]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[B]], i32 1
 ; CHECK-NEXT:    [[I3:%.*]] = load float, float* [[ARRAYIDX3]], align 4
 ; CHECK-NEXT:    [[ADD2:%.*]] = fadd float [[I2]], [[I3]]
-; CHECK-NEXT:    [[CALL2:%.*]] = tail call float @llvm.powi.f32(float [[ADD2]], i32 [[Q:%.*]]) #3
+; CHECK-NEXT:    [[CALL2:%.*]] = tail call float @llvm.powi.f32.i32(float [[ADD2]], i32 [[Q:%.*]]) #3
 ; CHECK-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[A]], i32 2
 ; CHECK-NEXT:    [[I4:%.*]] = load float, float* [[ARRAYIDX4]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[B]], i32 2
 ; CHECK-NEXT:    [[I5:%.*]] = load float, float* [[ARRAYIDX5]], align 4
 ; CHECK-NEXT:    [[ADD3:%.*]] = fadd float [[I4]], [[I5]]
-; CHECK-NEXT:    [[CALL3:%.*]] = tail call float @llvm.powi.f32(float [[ADD3]], i32 [[P]]) #3
+; CHECK-NEXT:    [[CALL3:%.*]] = tail call float @llvm.powi.f32.i32(float [[ADD3]], i32 [[P]]) #3
 ; CHECK-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[A]], i32 3
 ; CHECK-NEXT:    [[I6:%.*]] = load float, float* [[ARRAYIDX6]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[B]], i32 3
 ; CHECK-NEXT:    [[I7:%.*]] = load float, float* [[ARRAYIDX7]], align 4
 ; CHECK-NEXT:    [[ADD4:%.*]] = fadd float [[I6]], [[I7]]
-; CHECK-NEXT:    [[CALL4:%.*]] = tail call float @llvm.powi.f32(float [[ADD4]], i32 [[Q]]) #3
+; CHECK-NEXT:    [[CALL4:%.*]] = tail call float @llvm.powi.f32.i32(float [[ADD4]], i32 [[Q]]) #3
 ; CHECK-NEXT:    store float [[CALL1]], float* [[C:%.*]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[C]], i32 1
 ; CHECK-NEXT:    store float [[CALL2]], float* [[ARRAYIDX8]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[C]], i32 2
 ; CHECK-NEXT:    store float [[CALL3]], float* [[ARRAYIDX9]], align 4
 ; CHECK-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[C]], i32 3
 ; CHECK-NEXT:    store float [[CALL4]], float* [[ARRAYIDX10]], align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %i0 = load float, float* %a, align 4
   %i1 = load float, float* %b, align 4
   %add1 = fadd float %i0, %i1
-  %call1 = tail call float @llvm.powi.f32(float %add1,i32 %P) nounwind readnone
+  %call1 = tail call float @llvm.powi.f32.i32(float %add1,i32 %P) nounwind readnone
 
   %arrayidx2 = getelementptr inbounds float, float* %a, i32 1
   %i2 = load float, float* %arrayidx2, align 4
   %arrayidx3 = getelementptr inbounds float, float* %b, i32 1
   %i3 = load float, float* %arrayidx3, align 4
   %add2 = fadd float %i2, %i3
-  %call2 = tail call float @llvm.powi.f32(float %add2,i32 %Q) nounwind readnone
+  %call2 = tail call float @llvm.powi.f32.i32(float %add2,i32 %Q) nounwind readnone
 
   %arrayidx4 = getelementptr inbounds float, float* %a, i32 2
   %i4 = load float, float* %arrayidx4, align 4
   %arrayidx5 = getelementptr inbounds float, float* %b, i32 2
   %i5 = load float, float* %arrayidx5, align 4
   %add3 = fadd float %i4, %i5
-  %call3 = tail call float @llvm.powi.f32(float %add3,i32 %P) nounwind readnone
+  %call3 = tail call float @llvm.powi.f32.i32(float %add3,i32 %P) nounwind readnone
 
   %arrayidx6 = getelementptr inbounds float, float* %a, i32 3
   %i6 = load float, float* %arrayidx6, align 4
   %arrayidx7 = getelementptr inbounds float, float* %b, i32 3
   %i7 = load float, float* %arrayidx7, align 4
   %add4 = fadd float %i6, %i7
-  %call4 = tail call float @llvm.powi.f32(float %add4,i32 %Q) nounwind readnone
+  %call4 = tail call float @llvm.powi.f32.i32(float %add4,i32 %Q) nounwind readnone
 
   store float %call1, float* %c, align 4
   %arrayidx8 = getelementptr inbounds float, float* %c, i32 1
   store float %call2, float* %arrayidx8, align 4
   %arrayidx9 = getelementptr inbounds float, float* %c, i32 2
   store float %call3, float* %arrayidx9, align 4
   %arrayidx10 = getelementptr inbounds float, float* %c, i32 3
   store float %call4, float* %arrayidx10, align 4
   ret void
 
 }

llvm/test/Transforms/Scalarizer/intrinsics.ll

 
 ; Unary int
 declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>)
 
 ; Unary int plus constant scalar operand
 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
 
 ; Unary fp plus any scalar operand
-declare <2 x float> @llvm.powi.v2f32(<2 x float>, i32)
+declare <2 x float> @llvm.powi.v2f32.i32(<2 x float>, i32)
 
 ; Binary int plus constant scalar operand
 declare <2 x i32> @llvm.smul.fix.sat.v2i32(<2 x i32>, <2 x i32>, i32)
 declare <2 x i32> @llvm.umul.fix.sat.v2i32(<2 x i32>, <2 x i32>, i32)
 
 
 ; CHECK-LABEL: @scalarize_sqrt_v2f32(
 ; CHECK: %sqrt.i0 = call float @llvm.sqrt.f32(float %x.i0)

 ; CHECK: %ctlz = insertelement <2 x i32> %ctlz.upto0, i32 %ctlz.i1, i32 1
 ; CHECK: ret <2 x i32> %ctlz
 define <2 x i32> @scalarize_ctlz_v2i32(<2 x i32> %x) #0 {
   %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
   ret <2 x i32> %ctlz
 }
 
 ; CHECK-LABEL: @scalarize_powi_v2f32(
-; CHECK: %powi.i0 = call float @llvm.powi.f32(float %x.i0, i32 %y)
-; CHECK: %powi.i1 = call float @llvm.powi.f32(float %x.i1, i32 %y)
+; CHECK: %powi.i0 = call float @llvm.powi.f32.i32(float %x.i0, i32 %y)
+; CHECK: %powi.i1 = call float @llvm.powi.f32.i32(float %x.i1, i32 %y)
 ; CHECK: %powi.upto0 = insertelement <2 x float> poison, float %powi.i0, i32 0
 ; CHECK: %powi = insertelement <2 x float> %powi.upto0, float %powi.i1, i32 1
 ; CHECK: ret <2 x float> %powi
 define <2 x float> @scalarize_powi_v2f32(<2 x float> %x, i32 %y) #0 {
-  %powi = call <2 x float> @llvm.powi.v2f32(<2 x float> %x, i32 %y)
+  %powi = call <2 x float> @llvm.powi.v2f32.i32(<2 x float> %x, i32 %y)
   ret <2 x float> %powi
 }
 
 ; CHECK-LABEL: @scalarize_smul_fix_sat_v2i32(
 ; CHECK: %smulfixsat.i0 = call i32 @llvm.smul.fix.sat.i32(i32 %x.i0, i32 5, i32 31)
 ; CHECK: %smulfixsat.i1 = call i32 @llvm.smul.fix.sat.i32(i32 %x.i1, i32 19, i32 31)
 ; CHECK: %smulfixsat.upto0 = insertelement <2 x i32> poison, i32 %smulfixsat.i0, i32 0
 ; CHECK: %smulfixsat = insertelement <2 x i32> %smulfixsat.upto0, i32 %smulfixsat.i1, i32 1