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asb
simoncook
Joe

Summary

Some instruction selection patterns required for ALU GPR instructions have already been automatically imported from existing TableGen descriptions - this patch simply adds testing for them. Logic for selecting constants and copies has been added.

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Repository: rG LLVM Github Monorepo

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lewis-revill created this revision.Mar 19 2020, 12:22 PM

Herald added a project: Restricted Project. · View Herald TranscriptMar 19 2020, 12:22 PM

Herald added subscribers: llvm-commits, evandro, luismarques and 26 others. · View Herald Transcript

Harbormaster failed remote builds in B49778: Diff 251435!Mar 19 2020, 1:09 PM

lewis-revill added parent revisions: D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions, D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.Apr 1 2020, 3:54 AM

Add tests for AND/OR/XOR.

Harbormaster failed remote builds in B52206: Diff 255758!Apr 7 2020, 1:04 PM

Use utils/update_mir_test_checks.py

Harbormaster failed remote builds in B52653: Diff 256533!Apr 10 2020, 3:12 AM

Add custom selection for copies and for constants. Significantly expand tests over more types.

Herald added a subscriber: hiraditya. · View Herald TranscriptApr 17 2020, 2:18 AM

Harbormaster failed remote builds in B53699: Diff 258267!Apr 17 2020, 2:40 AM

Bug fix - ensure selectConstant produces copies with fully constrained registers.

Harbormaster failed remote builds in B53860: Diff 258538!Apr 18 2020, 12:22 PM

Missing copy tests for all permutations of virtual and physical registers

llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
114–115	This can't early return, it still needs to constrain a virtual source

craig.topper mentioned this in D91931: [RISCV][GlobalISel] Select add i32, i32.Nov 22 2020, 11:09 AM

[WIP][RISCV][GlobalISel] Select ALU GPR instructions
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Diff 258538

llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir

[WIP][RISCV][GlobalISel] Select ALU GPR instructionsNeeds ReviewPublicActions

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Revision ContentsChangeset List

Diff 258538

llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir

llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir

[WIP][RISCV][GlobalISel] Select ALU GPR instructions
Needs ReviewPublic
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Revision Contents
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