Some instruction selection patterns required for ALU GPR instructions have already been automatically imported from existing TableGen descriptions - this patch simply adds testing for them. Logic for selecting constants and copies has been added, along with the first of the GIComplexPatternEquiv definitions required to select the shiftMaskXLen ComplexPattern.
Rebased. Added the first GIComplexPatternEquiv definition in order to handle the operands to shifts, which are now covered by a ComplexPattern in SelectionDAG. Updated the tests to match the output of the regbank selector.
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This function name is misleading. Can you restructure to use something more like getRegClassForTypeOnBank (which AArch64 has a FIXME to make a generic TargetRegisterInfo method)
Should sext_inreg be legal?
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What is this parameter?
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Why not just print the whole instruction?
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Should not construct one off MachineIRBuilders. The selector usually just directly uses BuildMI
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Didn't erase the instruction
This is what I'm stuck on right now. It really should to match the SelectionDAG code, at least for i32 -> i64. However there is no way to map G_SEXT_INREG to sext_inreg because sext_inreg uses a value type as a DAG operand, whereas G_SEXT_INREG uses a constant which indicates the size of the original type. So no patterns defined which use sext_inreg will work for GlobalISel. I think my only option left is to do custom selection code.
I assume we want to implement this TODO at higher optimization levels?
Do we plan on implementing this earlier in a future patch? Why do we want to canonicalize it earlier?
I think this should be slliw?
Why is this instruction emitted? This looks like a nop.
We may want to handle this in a later pass.
Do we want tests for and_i64, or_i64 and xor_i64? And immediate variants for these and add_i64, sub_i64?
The upper bits aren’t used by the sraiw so SLLI should be ok
The upper half immediate is 0 and we don’t have combines enabled.
I don’t think they provide any value. They would all be split instructions.