aemerson (Amara Emerson)
Asian George Costanza

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User Since
Sep 9 2013, 3:45 AM (219 w, 3 d)

Compilers at a fruit company

Recent Activity

Wed, Nov 8

aemerson added inline comments to D39267: [GISel]: Change Legalization from top down to bottom up + DCE.
Wed, Nov 8, 8:30 AM

Tue, Nov 7

aemerson added a comment to D39267: [GISel]: Change Legalization from top down to bottom up + DCE.

Hi Aditya,

Tue, Nov 7, 9:54 AM

Wed, Nov 1

aemerson added a comment to D39267: [GISel]: Change Legalization from top down to bottom up + DCE.

Hi Aditya,

Wed, Nov 1, 4:26 AM

Fri, Oct 27

aemerson added a comment to D39267: [GISel]: Change Legalization from top down to bottom up + DCE.

Hi Aditya,

Fri, Oct 27, 8:59 AM

Oct 15 2017

aemerson added a comment to D38682: [LoopInterchange] Fix phi node ordering miscompile..

Can you not pass the -loop-interchange-threshold option to force the cost model to always interchange? If this isn't possible with the current code then it seems like a major oversight.

Oct 15 2017, 7:32 AM
aemerson added a comment to D38676: [LV] Model masking in VPlan, introducing VPInstructions.

A minor nit but LGTM. I don't have an aversion to "dead code" if it's going to be used in the near future, so perhaps to make the patch smaller split it into an initial patch to add VPlanValue.h and then the VPlanBuilder.h as well as the changes to the documentation. Those pieces seem uncontroversial to me, before moving onto the vectorizer. @mkuper does this make sense?

Oct 15 2017, 7:25 AM

Oct 11 2017

aemerson added inline comments to D38734: [MachineCombiner] Fix initialisation of LastUpdate for incremental update..
Oct 11 2017, 7:44 AM
aemerson added inline comments to D38676: [LV] Model masking in VPlan, introducing VPInstructions.
Oct 11 2017, 3:39 AM

Oct 10 2017

aemerson added a comment to D36534: [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 use them..

Rebased to trunk. I'll fix the comments I've received shortly.

This patch now requires r315148 to be reverted. That patch changed
getPredCode() and getImmCode() to return StringRef's but this patch requires
that getPredCode() return a std::string. We could revert just the getPredCode()
portion of that patch if we want but I think it would be weird for the two
functions to require different usage.

I'm just curious, what's the issue with it returning a StringRef?

Oct 10 2017, 10:42 AM
aemerson added a comment to D38200: [GISel]: Process new insts to legalize in the order they were created.

I'm a bit confused by the above. Should we allow legalization to look at other instructions, or should we not?

I believe we shouldn't allow to look at other instructions. I am guessing we need to do that to perform combines at legalization time and I think we shouldn't go in that direction. I would rather have the combines be a separate pass. I.e., we are not taking the same approach as SelectionDAG here.

Aditya, is this really needed to perform legalization?

Oct 10 2017, 9:47 AM
aemerson added inline comments to D38734: [MachineCombiner] Fix initialisation of LastUpdate for incremental update..
Oct 10 2017, 9:18 AM
aemerson added a comment to D38417: [test-suite] Adding HACCKernels app.

I made the change that Hal mentioned to allow for the loop to vectorize.

Oct 10 2017, 4:25 AM

Oct 9 2017

aemerson added a reviewer for D38682: [LoopInterchange] Fix phi node ordering miscompile.: mcrosier.
Oct 9 2017, 9:11 AM
aemerson committed rL315205: [AArch64] Improve codegen for inverted overflow checking intrinsics.
[AArch64] Improve codegen for inverted overflow checking intrinsics
Oct 9 2017, 8:17 AM
aemerson closed D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics by committing rL315205: [AArch64] Improve codegen for inverted overflow checking intrinsics.
Oct 9 2017, 8:16 AM

Oct 8 2017

aemerson added a reviewer for D38676: [LV] Model masking in VPlan, introducing VPInstructions: aemerson.
Oct 8 2017, 3:02 PM
aemerson added a comment to D38676: [LV] Model masking in VPlan, introducing VPInstructions.

I haven't been keeping up with this area as much as I'd have liked, but have some comments. Overall the approach seems ok to me.

Oct 8 2017, 3:00 PM
aemerson committed rL315179: [AArch64][GlobalISel] Add a test case for G_PHI of p0 instruction selection..
[AArch64][GlobalISel] Add a test case for G_PHI of p0 instruction selection.
Oct 8 2017, 8:31 AM
aemerson committed rL315178: [AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection..
[AArch64][GlobalISel] Add a test case for G_PHI of p0 regbank selection.
Oct 8 2017, 8:31 AM
aemerson committed rL315177: [AArch64][GlobalISel] Make G_PHI of p0 types legal..
[AArch64][GlobalISel] Make G_PHI of p0 types legal.
Oct 8 2017, 8:31 AM
aemerson closed D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal by committing rL315177: [AArch64][GlobalISel] Make G_PHI of p0 types legal..
Oct 8 2017, 8:31 AM

Oct 6 2017

aemerson added a comment to D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction.

Thanks, I've put the idiom into a helper and committed. Let me know if it's not what you had in mind.

Oct 6 2017, 12:28 PM
aemerson committed rL315092: [GlobalISel] Fix legalizer trying to process a deleted instruction..
[GlobalISel] Fix legalizer trying to process a deleted instruction.
Oct 6 2017, 12:26 PM
aemerson closed D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction by committing rL315092: [GlobalISel] Fix legalizer trying to process a deleted instruction..
Oct 6 2017, 12:26 PM
aemerson added a comment to D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal.

Thanks, will do.

Oct 6 2017, 10:20 AM
aemerson added a reviewer for D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction: ab.
Oct 6 2017, 8:58 AM
aemerson updated the diff for D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics.

Rebased and updated diff to use a helper function for the overflow op result checks. I didn't put the type legal check into the helper because it's used to do an early exit rather than to continue onto the rest of the lower method.

Oct 6 2017, 7:15 AM
aemerson updated subscribers of D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction.

Forgot to add llvm-commits, pasting description again:

Oct 6 2017, 6:09 AM
aemerson added a comment to D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal.

Forgot to add llvm-commits.

Oct 6 2017, 6:08 AM
aemerson updated subscribers of D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal.
Oct 6 2017, 6:06 AM
aemerson added a dependent revision for D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction: D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal.
Oct 6 2017, 6:05 AM
aemerson added a dependency for D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal: D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction.
Oct 6 2017, 6:05 AM
aemerson created D38622: [GlobalISel] Fix legalizer trying to process a deleted instruction.
Oct 6 2017, 6:05 AM
aemerson created D38621: [AArch64][GlobalISel] Make G_PHI of p0 types legal.
Oct 6 2017, 6:01 AM

Oct 5 2017

aemerson added inline comments to D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics.
Oct 5 2017, 8:03 AM
aemerson added inline comments to D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics.
Oct 5 2017, 3:06 AM

Oct 4 2017

aemerson added a reviewer for D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics: kristof.beyls.
Oct 4 2017, 8:38 AM

Sep 30 2017

aemerson added a comment to D38161: [X86] Improve codegen for inverted overflow checking intrinsics.
Sep 30 2017, 1:02 PM

Sep 29 2017

aemerson added inline comments to D30529: [RFC][GlobalISel] Enable legalizing non-power-of-2 sized types..
Sep 29 2017, 7:39 AM
aemerson committed rL314514: [X86] Improve codegen for inverted overflow checking intrinsics..
[X86] Improve codegen for inverted overflow checking intrinsics.
Sep 29 2017, 6:55 AM
aemerson closed D38161: [X86] Improve codegen for inverted overflow checking intrinsics by committing rL314514: [X86] Improve codegen for inverted overflow checking intrinsics..
Sep 29 2017, 6:55 AM

Sep 28 2017

aemerson added a comment to D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics.

Ping.

Sep 28 2017, 8:03 AM
aemerson updated the diff for D38161: [X86] Improve codegen for inverted overflow checking intrinsics.

Committed test in r314416. Updated to show diff in behaviour.

Sep 28 2017, 7:09 AM
aemerson committed rL314416: [X86] Add overflow intrinsic test in preparation for D38161..
[X86] Add overflow intrinsic test in preparation for D38161.
Sep 28 2017, 6:45 AM
aemerson accepted D38338: [LV] Fix PR34743 - handle casts that sink after interleaved loads.

LGTM.

Sep 28 2017, 6:33 AM

Sep 27 2017

aemerson added a comment to D38161: [X86] Improve codegen for inverted overflow checking intrinsics.

You mean actually commit the current codegen's test output (with no code changes) and then resubmit this patch as a diff?

Sep 27 2017, 5:57 AM

Sep 25 2017

aemerson added inline comments to D38192: [TargetParser][AArch64] Add support for SPE feature in the target parser..
Sep 25 2017, 5:02 AM

Sep 21 2017

aemerson created D38161: [X86] Improve codegen for inverted overflow checking intrinsics.
Sep 21 2017, 5:19 PM
aemerson created D38160: [AArch64] Improve codegen for inverted overflow checking intrinsics.
Sep 21 2017, 5:11 PM

Sep 13 2017

aemerson resigned from D31724: [SelectionDAG] Remove special call to LHS computeKnownBits for ANDs with constant RHS..
Sep 13 2017, 11:49 AM

Aug 4 2017

aemerson committed rL310117: [SCEV] Preserve NSW information for sext(subtract)..
[SCEV] Preserve NSW information for sext(subtract).
Aug 4 2017, 1:20 PM
aemerson closed D35256: [SCEV] Try harder to preserve NSW information for sext(sub) expressions by committing rL310117: [SCEV] Preserve NSW information for sext(subtract)..
Aug 4 2017, 1:20 PM
aemerson resigned from D31239: [WIP] Add Caching of Known Bits in InstCombine.
Aug 4 2017, 9:48 AM
aemerson resigned from D35307: [AArch64] Initial SVE register definitions.
Aug 4 2017, 9:44 AM
aemerson closed D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.
Aug 4 2017, 9:43 AM
aemerson updated the diff for D35256: [SCEV] Try harder to preserve NSW information for sext(sub) expressions.

Added support for handling the nsw/nuw ssub.with.overflow intrinsic.

Aug 4 2017, 7:24 AM
aemerson added a comment to D36059: [memops] Add a new pass to inject fast-path code for specific library function calls..

IMO, there is no need for doing this in this place. If we're just leaving a marker here for the target to expand, we don't need to do anything. We already get a chance to custom expand the libcall in the target. Adding the versioning doesn't make that any simpler given that it still needs to introduce a loop.

The difference is that at the target codegen level we can't as easily do the predicate analysis as we can at the IR level.

If, for a particular target, it is worth emitting a versioned, carefully target-crafted loop or instruction sequence, I would expect them to not use this pass but to custom lower the calls in the backend much like x86 does for constant-size calls.

But in the patch description you say that one of the challenges is constructing *just* the right IR to get efficient codegen from the backend. I understand this is for x86 right now, but if you don't have plans to allow other targets to work well with it, why not put it into the Target/X86 directory and make it a backend-specific IR pass to avoid confusion?

Aug 4 2017, 2:45 AM

Aug 2 2017

aemerson added a comment to D35307: [AArch64] Initial SVE register definitions.

I'm resigning from SVE upstreaming related activities, so Graham will be taking over this patch and others from here.

Aug 2 2017, 6:24 AM

Aug 1 2017

aemerson added inline comments to D35256: [SCEV] Try harder to preserve NSW information for sext(sub) expressions.
Aug 1 2017, 5:38 AM
aemerson added a comment to D36059: [memops] Add a new pass to inject fast-path code for specific library function calls..

Instead of generating loop IR for the fast path, how about creating a versioned memcpy/memset with the constrained parameters guarded under the condition test? That way, in the back-end the exact preferred optimal code can be generated, allowing for unrolled loop bodies specific to individual targets.

Aug 1 2017, 2:01 AM

Jul 31 2017

aemerson updated the diff for D35256: [SCEV] Try harder to preserve NSW information for sext(sub) expressions.

Updated to use MatchBinaryOp.

Jul 31 2017, 4:05 AM

Jul 24 2017

aemerson accepted D35777: [LoopInterchange] Update code to use range-based for loops (NFC)..

LGTM.

Jul 24 2017, 3:20 AM

Jul 23 2017

aemerson added inline comments to D35777: [LoopInterchange] Update code to use range-based for loops (NFC)..
Jul 23 2017, 11:13 AM

Jul 17 2017

aemerson added a comment to D35256: [SCEV] Try harder to preserve NSW information for sext(sub) expressions.

Ping.

Jul 17 2017, 3:21 AM

Jul 13 2017

aemerson committed rL307919: [AArch64] Add support for handling the +sve target feature..
[AArch64] Add support for handling the +sve target feature.
Jul 13 2017, 8:36 AM
aemerson closed D35118: [AArch64] Add support for handling the +sve target feature by committing rL307919: [AArch64] Add support for handling the +sve target feature..
Jul 13 2017, 8:36 AM · Restricted Project
aemerson committed rL307917: [AArch64] Add an SVE target feature to the backend and TargetParser..
[AArch64] Add an SVE target feature to the backend and TargetParser.
Jul 13 2017, 8:20 AM
aemerson updated the diff for D35118: [AArch64] Add support for handling the +sve target feature.

The reason it's removed is because it's not actually used anywhere, just as a default value. I'm not going to debate it further though so I've put it back in.

Jul 13 2017, 3:44 AM · Restricted Project
aemerson added a comment to D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.

Ignore previous comment, was supposed to be added to D35118.

Jul 13 2017, 2:19 AM
aemerson added a comment to D35118: [AArch64] Add support for handling the +sve target feature.

@jmolloy Can you check this change, please?

Jul 13 2017, 2:19 AM · Restricted Project
aemerson added a comment to D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.
Jul 13 2017, 2:18 AM
aemerson added a comment to D35307: [AArch64] Initial SVE register definitions.

Hi Amara,

This seems a very raw change, without any further description, comments or proper usage, other than a few changes on random places.

Jul 13 2017, 2:11 AM

Jul 12 2017

aemerson updated the diff for D35307: [AArch64] Initial SVE register definitions.

Removing comment.

Jul 12 2017, 8:51 AM
aemerson created D35307: [AArch64] Initial SVE register definitions.
Jul 12 2017, 8:09 AM
aemerson abandoned D35264: [LICM] Teach LICM to hoist conditional loads.

This looks wrong.
In particular, it would break for something like:

a = *p;
free(p)
while (k) { // k is always false
 ... = *p;
}

We have llvm::isSafeToLoadUnconditionally() that does the domination check safely, but just checking that it's safe to load unconditionally in the pre-header may not be enough.

Consider something like:

a = *p;
while (k) {
  if (m) {
    free(p);
  }
  ... = *p;

}

Now, in those cases we shouldn't be hoisting regardless, because if p escapes, the value may not be loop-invariant.
But we need to make sure the patch doesn't break that, so additional tests may be needed.

Jul 12 2017, 1:25 AM

Jul 11 2017

aemerson updated the diff for D35264: [LICM] Teach LICM to hoist conditional loads.

Whitespace fixes.

Jul 11 2017, 9:19 AM
aemerson created D35264: [LICM] Teach LICM to hoist conditional loads.
Jul 11 2017, 9:15 AM
aemerson created D35256: [SCEV] Try harder to preserve NSW information for sext(sub) expressions.
Jul 11 2017, 7:00 AM
aemerson added a comment to D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.

Ping.

Jul 11 2017, 2:02 AM

Jul 7 2017

aemerson added inline comments to D35118: [AArch64] Add support for handling the +sve target feature.
Jul 7 2017, 5:16 AM · Restricted Project
aemerson added a comment to D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.

Sure, up for review at D35118.

Jul 7 2017, 4:30 AM
aemerson created D35118: [AArch64] Add support for handling the +sve target feature.
Jul 7 2017, 4:28 AM · Restricted Project
aemerson added a dependent revision for D35076: [AArch64] Add an SVE target feature to the backend and TargetParser: D35118: [AArch64] Add support for handling the +sve target feature.
Jul 7 2017, 4:28 AM

Jul 6 2017

aemerson added a comment to D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.

Hi Amara,

Thanks for the patch, looks trivial to me. I guess we don't have any targets with SVE by default, so we don't need most tests.

I'm guessing you have a Clang counterpart, too?

cheers,
--renato

Jul 6 2017, 3:05 PM
aemerson updated the summary of D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.
Jul 6 2017, 11:11 AM
aemerson created D35076: [AArch64] Add an SVE target feature to the backend and TargetParser.
Jul 6 2017, 11:11 AM
aemerson resigned from D12178: [TSAN/AArch64/Android] Changes for AArch64/Android.
Jul 6 2017, 11:04 AM
aemerson resigned from D12177: [TSAN/AArch64/Android] Set up initial structs for TSAN.
Jul 6 2017, 11:03 AM
aemerson removed a reviewer for D8492: Add support for AArch64 and ARM backends for v8.1 architecture extension.: aemerson.
Jul 6 2017, 11:03 AM
aemerson abandoned D2736: [ARM] Fix NEON being enabled with soft-float.
Jul 6 2017, 11:02 AM
aemerson removed a reviewer for D2736: [ARM] Fix NEON being enabled with soft-float: t.p.northover.
Jul 6 2017, 11:01 AM
aemerson abandoned D1900: [ARM] Fix FP ABI attributes with no VFP.
Jul 6 2017, 10:59 AM
aemerson removed a reviewer for D1900: [ARM] Fix FP ABI attributes with no VFP: richard.barton.arm.
Jul 6 2017, 10:58 AM
aemerson abandoned D2110: [AArch64] Remove NEON from "generic" CPU target.
Jul 6 2017, 10:58 AM
aemerson removed a reviewer for D2110: [AArch64] Remove NEON from "generic" CPU target: t.p.northover.
Jul 6 2017, 10:58 AM
aemerson abandoned D2586: [AArch64] Add -mgeneral_regs_only option.
Jul 6 2017, 10:57 AM
aemerson updated subscribers of D2586: [AArch64] Add -mgeneral_regs_only option.
Jul 6 2017, 10:57 AM
aemerson abandoned D4207: Fix crash in LICM due to unreachable uses after LCSSA.
Jul 6 2017, 10:55 AM · deleted
aemerson updated subscribers of D4207: Fix crash in LICM due to unreachable uses after LCSSA.
Jul 6 2017, 10:54 AM · deleted

Jun 26 2017

aemerson accepted D32730: LV: Don't insert runtime ptr checks on divergent targets.

LGTM.

Jun 26 2017, 3:13 AM