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aemerson (Amara Emerson)
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User Since
Sep 9 2013, 3:45 AM (406 w, 15 h)

The sea was angry that day, my friends - like an old man trying to send back soup in a deli.

Recent Activity

Thu, Jun 17

aemerson added a comment to D104245: [GlobalISel] Describe undefined values for G_SBFX/G_UBFX operands.

Shouldn't we also have verifier checks for these requirements in the statically known cases?

Thu, Jun 17, 2:42 PM · Restricted Project
aemerson added a comment to D103326: [GlobalISel] Add combine for PTR_ADD with regbanks.

+more GlobalISel reviewers.

What do you all think about this? It seems to be the first generic combine designed specifically to run post-regbankselect. Should we be going in this direction? Or modifying existing combines so they can work both pre- and post-regbankselect?

Assuming we do want this combine, is there a neater way of writing the "ugly manual regbank preservation" that Matt highlighted?

Thu, Jun 17, 2:29 PM · Restricted Project
aemerson added inline comments to D104355: [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions..
Thu, Jun 17, 1:48 PM · Restricted Project

Wed, Jun 16

aemerson added a comment to D104355: [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions..

Hi Amara,

I like this approach!
What is the impact on compile time?

Compile time seems to be noise, since this the new combine only runs in some cases where the unmerge combine fails, which is rare in most code. I would have liked to use it as the first-attempt combine for unmerge, but AMDGPU just wound up getting into a legalization loop (I think that's a problem with AMDGPU rather than the combine itself).

I am a little bit surprised by the long sequences that we generate now in certain case. What is the reason for that? (See inline comment for a highlight of what I am talking about.)

Cheers,
-Quentin

Wed, Jun 16, 2:01 PM · Restricted Project
aemerson updated the diff for D104355: [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions..

Remove commented out code.

Wed, Jun 16, 10:04 AM · Restricted Project
aemerson added inline comments to D104355: [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions..
Wed, Jun 16, 8:08 AM · Restricted Project

Tue, Jun 15

aemerson requested review of D104355: [GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions..
Tue, Jun 15, 11:17 PM · Restricted Project

Fri, Jun 11

aemerson added inline comments to D103498: [AArch64][GlobalISel] Use PackedVectorAllTypeList for G_SHUFFLE_VECTOR.
Fri, Jun 11, 4:00 PM · Restricted Project

Thu, Jun 10

aemerson added inline comments to D101819: [M68k][GloballSel] Adding initial GlobalISel infrastructure.
Thu, Jun 10, 6:36 PM · Restricted Project
aemerson committed rG670edf3ee004: [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. (authored by aemerson).
[AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes.
Thu, Jun 10, 5:00 PM
aemerson closed D104070: [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes..
Thu, Jun 10, 5:00 PM · Restricted Project
aemerson added inline comments to D101819: [M68k][GloballSel] Adding initial GlobalISel infrastructure.
Thu, Jun 10, 4:58 PM · Restricted Project
aemerson requested review of D104070: [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes..
Thu, Jun 10, 3:52 PM · Restricted Project

Mon, Jun 7

aemerson added inline comments to D101819: [M68k][GloballSel] Adding initial GlobalISel infrastructure.
Mon, Jun 7, 10:43 AM · Restricted Project

Fri, Jun 4

aemerson accepted D103582: [AArch64][GlobalISel] Handle multiple phis in fixupPHIOpBanks.

Ok, LGTM.

Fri, Jun 4, 9:21 AM · Restricted Project
aemerson added a comment to D101819: [M68k][GloballSel] Adding initial GlobalISel infrastructure.

Hi,

LLVM ERROR: unable to translate in big endian mode (in function: f)

You'll need to turn that into a warning, otherwise effectively, none of your GISel changes will be testable (as in running the generated code on an actual target) until the support is complete, which is not a realistic constraint to have when bringing up a new GISel backend.

Cheers,
-Quentin

Hi @qcolombet ,
When I do a git grep with that error message, I find that it comes from IRTranslator.cpp file and in the runOnMachineFunction() function where it checks for big endian and throws a reportTranslationError() which is where that error comes from. By removing the reportTranslationError() temporarily in order to test my implementation, that would cause errors in other targets. Can you please suggest me any other way to solve this issue?

Thanks,
Sushma

You can add a hook to TargetLoweringInfo so that only targets which want to use big-endian in GlobalISel can enable it (just M68k for now). Then check this hook, if it false then do the current fallback code.

Fri, Jun 4, 9:21 AM · Restricted Project

Thu, Jun 3

aemerson added inline comments to D103582: [AArch64][GlobalISel] Handle multiple phis in fixupPHIOpBanks.
Thu, Jun 3, 10:21 AM · Restricted Project

Tue, Jun 1

aemerson accepted D102869: CodeGen: Store LLT instead of uint64_t in MachineMemOperand.
Tue, Jun 1, 3:27 PM · Restricted Project

Fri, May 28

aemerson committed rG018a9641ff1a: [AArch64][GlobalISel] Fix a crash during selection of a G_ZEXT(s8 = G_LOAD) (authored by aemerson).
[AArch64][GlobalISel] Fix a crash during selection of a G_ZEXT(s8 = G_LOAD)
Fri, May 28, 4:35 PM
aemerson accepted D103291: [AArch64][GISel] and+or+shl => bfi.

LGTM with minor nits addressed, thanks.

Fri, May 28, 2:07 PM · Restricted Project
aemerson added a comment to D102869: CodeGen: Store LLT instead of uint64_t in MachineMemOperand.

Are we already testing the G_MEMCPY path with large (invalid) sizes?

Anyone else got any comments?

Fri, May 28, 11:21 AM · Restricted Project
aemerson accepted D102474: AArch64: support atomic load/store in GISel.
Fri, May 28, 10:59 AM · Restricted Project
aemerson committed rG59a4ee97288b: [AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources. (authored by aemerson).
[AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources.
Fri, May 28, 12:01 AM
aemerson closed D103227: [AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources..
Fri, May 28, 12:01 AM · Restricted Project

Thu, May 27

aemerson requested review of D103301: [AArch64][GlobalISel] Implement moreElements legalization for G_SHUFFLE_VECTOR..
Thu, May 27, 11:51 PM · Restricted Project
aemerson added inline comments to D103291: [AArch64][GISel] and+or+shl => bfi.
Thu, May 27, 4:43 PM · Restricted Project
aemerson committed rG9f39ba13b596: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR. (authored by aemerson).
[GlobalISel] Implement splitting of G_SHUFFLE_VECTOR.
Thu, May 27, 12:29 AM
aemerson closed D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
Thu, May 27, 12:29 AM · Restricted Project

Wed, May 26

aemerson requested review of D103227: [AArch64][GlobalISel] Legalize oversize G_EXTRACT_VECTOR_ELT sources..
Wed, May 26, 11:36 PM · Restricted Project
aemerson committed rG74edfb28053d: [AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE. (authored by aemerson).
[AArch64][GlobalISel] Legalize non-power-of-2 vector elements for G_STORE.
Wed, May 26, 5:01 PM
aemerson accepted D103128: [GlobalISel] Don't emit lost debug location remarks when legalizing tail calls.
Wed, May 26, 4:26 PM · Restricted Project

Tue, May 25

aemerson committed rGff30436dc5e5: [GlobalISel] Fix MachineIRBuilder not using the DstOp argument for… (authored by aemerson).
[GlobalISel] Fix MachineIRBuilder not using the DstOp argument for…
Tue, May 25, 12:43 AM

May 20 2021

aemerson added inline comments to D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
May 20 2021, 7:26 PM · Restricted Project
aemerson added inline comments to D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
May 20 2021, 4:01 PM · Restricted Project
aemerson added inline comments to D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
May 20 2021, 3:35 PM · Restricted Project
aemerson accepted D102738: GlobalISel: Do not change register types in lowerLoad.
May 20 2021, 10:50 AM · Restricted Project
aemerson added inline comments to D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
May 20 2021, 10:04 AM · Restricted Project
aemerson updated the diff for D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
May 20 2021, 12:40 AM · Restricted Project
aemerson requested review of D102828: [GlobalISel] Implement splitting of G_SHUFFLE_VECTOR..
May 20 2021, 12:39 AM · Restricted Project

May 19 2021

aemerson committed rG57ea5d4f4875: [GlobalISel] Fix div+rem -> divrem combine causing use-def violation. (authored by aemerson).
[GlobalISel] Fix div+rem -> divrem combine causing use-def violation.
May 19 2021, 11:14 PM
aemerson added a comment to D102690: [test-suite] [SingleSource] Add aarch64_neon_intrinsics reference output.

Until the bug is fixed, this test cannot be re-enabled as a flaky test is worse than no test at all.

Thanks for chiming in. What I see is that the test is not currently disabled, but instead it falls back to testing for a default reference output and then fails:

https://github.com/llvm/llvm-test-suite/blob/3af2314126514c028cc39cd56510cd8badaba4e9/Makefile.programs#L871-L877

Is that consistent with what you see?

This doesn’t seem to happen on Darwin, so it’s a surprise that it’s just being noticed now. Either way makes sense to disable it in a better way.

I don't propose to re-enable the test until it is fixed -- at the moment the test is actively failing for myself and colleagues when running 'lnt runtest nt --test-suite llvm-test-suite'. Is there some other way to inhibit the test?

If so, I propose to do that.

I also worry for a moment in time that there is a window of time where *all* of these generated 'basic correctness tests' are disabled. It seems to me those tests could usefully catch bugs. Can we do better by only inhibiting the failing ones?

Sure. I did report this to Arm on multiple occasions, and as maintainers of the ACLE implementation I think Arm’s proprietary tool chain team should be taking responsibility for this to fix the issue.

May 19 2021, 8:47 AM

May 18 2021

aemerson updated subscribers of D102690: [test-suite] [SingleSource] Add aarch64_neon_intrinsics reference output.

It was disabled here: https://github.com/llvm/llvm-test-suite/commit/87d67af9d8565d068b6706c081b7ae07addcb882

Is the underlying issue definitely fixed?

Thanks for raising that. I do not have any knowledge about the underlying issue at this time.

However, removing the output reference does not appear to inhibit the test, at least in my environment, it only causes lnt to use the default output which reads 'exit 0', hence the cryptic test failure message.

@aemerson are you able to comment, does the issue persist?

If it does persist, is there another way to inhibit or fix this exec test?

May 18 2021, 1:30 PM

May 17 2021

aemerson added inline comments to D102385: [GlobalISel][IRTranslator] Use preferred alignment when creating frame indices..
May 17 2021, 10:54 AM · Restricted Project

May 16 2021

aemerson updated the diff for D102385: [GlobalISel][IRTranslator] Use preferred alignment when creating frame indices..

Guard this with a TLI check. I think a separate pass to do this is overkill.

May 16 2021, 5:10 PM · Restricted Project

May 14 2021

aemerson added a comment to D101234: GlobalISel: Use DAG call lowering infrastructure in a more compatible way.

This seems to have broken the following code for AArch64, could you take a look?

target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64e-apple-ios14.0.0"

declare <3 x float> @bar(float)

define void @foo(float %a, float %b) {
entry:
  %call = call <3 x float> @bar(float undef)
  ret void
}
May 14 2021, 4:57 PM · Restricted Project
aemerson committed rG80c534a8f97f: [GlobalISel][CallLowering] Fix crash when handling a v3s32 type that's being… (authored by aemerson).
[GlobalISel][CallLowering] Fix crash when handling a v3s32 type that's being…
May 14 2021, 4:31 PM
aemerson added inline comments to D102474: AArch64: support atomic load/store in GISel.
May 14 2021, 2:24 PM · Restricted Project

May 13 2021

aemerson added a comment to D101234: GlobalISel: Use DAG call lowering infrastructure in a more compatible way.

This seems to have broken the following code for AArch64, could you take a look?

May 13 2021, 6:11 PM · Restricted Project
aemerson committed rGaf6eb1c710ca: [AArch64][GlobalISel] Fix a crash during unsuccessful G_CTPOP <2 x s64>… (authored by aemerson).
[AArch64][GlobalISel] Fix a crash during unsuccessful G_CTPOP <2 x s64>…
May 13 2021, 5:28 PM

May 12 2021

aemerson requested review of D102385: [GlobalISel][IRTranslator] Use preferred alignment when creating frame indices..
May 12 2021, 11:04 PM · Restricted Project
aemerson committed rGdc8d16c03f4f: [AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting. (authored by aemerson).
[AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting.
May 12 2021, 9:47 AM

May 11 2021

aemerson accepted D101947: GlobalISel: Split ValueHandler into assignment and emission classes.

@paquette See any issues with this?

May 11 2021, 12:50 PM · Restricted Project
aemerson accepted D101538: [GlobalISel][IRTranslator] Make translate() methods virtual..

Fair enough.

May 11 2021, 12:47 PM · Restricted Project
aemerson committed rG69069509b2d3: [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. (authored by aemerson).
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.
May 11 2021, 12:39 PM
aemerson added a comment to D101538: [GlobalISel][IRTranslator] Make translate() methods virtual..

Is this really necessary? Our preference is to use custom combines/lowering passes, or custom legalization, to do this.

Well, our usecase might not be that canonical, let me briefly explain. For example, translating a bitcast - default IRTranslator implementation turns it into a COPY when LLTs of src and dst are the same. In our target (SPIR-V) LLTs do not matter that much, the typeinfo is represented with some pseudo instructions, so we run into this situation quite often. And losing a bitcast in the translator doesn't work for us as it'd obviously be quite difficult to recover it.

May 11 2021, 12:24 PM · Restricted Project
aemerson committed rGae2b36e8bdfa: [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating… (authored by aemerson).
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating…
May 11 2021, 11:33 AM
aemerson closed D102204: [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs..
May 11 2021, 11:33 AM · Restricted Project
aemerson updated the diff for D102204: [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs..
May 11 2021, 10:35 AM · Restricted Project

May 10 2021

aemerson added inline comments to D102204: [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs..
May 10 2021, 8:10 PM · Restricted Project
aemerson requested review of D102204: [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs..
May 10 2021, 5:49 PM · Restricted Project
aemerson accepted D101782: [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps.

LGTM.

May 10 2021, 3:05 PM · Restricted Project
aemerson accepted D102198: [AArch64][GlobalISel] Enable memcpy family combines on minsize functions.

Wow, not running this at all for -Oz? LGTM.

May 10 2021, 3:04 PM · Restricted Project
aemerson committed rGdc7549999835: [GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges. (authored by aemerson).
[GlobalISel][IRTranslator] Fix bit-test lowering dropping phi edges.
May 10 2021, 11:59 AM

May 7 2021

aemerson committed rG5b158093e246: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0. (authored by aemerson).
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.
May 7 2021, 5:07 PM
aemerson closed D102038: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0..
May 7 2021, 5:07 PM · Restricted Project
aemerson committed rG808bc11d9e1a: [GlobalISel] Don't form zero/sign extending loads for atomics. (authored by aemerson).
[GlobalISel] Don't form zero/sign extending loads for atomics.
May 7 2021, 5:00 PM
aemerson closed D101932: [GlobalISel] Don't form zero/sign extending loads for atomics.
May 7 2021, 5:00 PM · Restricted Project
aemerson accepted D101946: GlobalISel: Move AArch64 AssignFnVarArg to base class.
May 7 2021, 4:52 PM · Restricted Project
aemerson added a comment to D101538: [GlobalISel][IRTranslator] Make translate() methods virtual..

Is this really necessary? Our preference is to use custom combines/lowering passes, or custom legalization, to do this.

May 7 2021, 4:51 PM · Restricted Project
aemerson updated the diff for D102038: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0..
May 7 2021, 4:40 PM · Restricted Project
aemerson updated the diff for D102038: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0..

Address comments. Factor out tryEmitBZero into the utils file.

May 7 2021, 4:22 PM · Restricted Project
aemerson added inline comments to D102038: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0..
May 7 2021, 4:20 PM · Restricted Project
aemerson updated the diff for D102038: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0..

Remove CSE from the combiner, this saves an additional 10% of the runtime in the pass, with no effect on code size.

May 7 2021, 11:33 AM · Restricted Project
aemerson committed rG1ccebb18ef9f: [GlobalISel] Micro-optimize the conditional branch optimization. (authored by aemerson).
[GlobalISel] Micro-optimize the conditional branch optimization.
May 7 2021, 12:24 AM

May 6 2021

aemerson requested review of D102038: [AArch64][GlobalISel] Create a new minimal combiner pass just for -O0..
May 6 2021, 5:52 PM · Restricted Project
aemerson updated the diff for D101932: [GlobalISel] Don't form zero/sign extending loads for atomics.

Hadn't rerun test since an update. Move check to before the LI check so that it runs unconditionally.

May 6 2021, 5:05 PM · Restricted Project

May 5 2021

aemerson added inline comments to D101782: [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps.
May 5 2021, 11:54 AM · Restricted Project
aemerson accepted D101234: GlobalISel: Use DAG call lowering infrastructure in a more compatible way.
May 5 2021, 11:41 AM · Restricted Project
aemerson requested review of D101932: [GlobalISel] Don't form zero/sign extending loads for atomics.
May 5 2021, 11:40 AM · Restricted Project

May 4 2021

aemerson added inline comments to D101234: GlobalISel: Use DAG call lowering infrastructure in a more compatible way.
May 4 2021, 11:30 AM · Restricted Project
aemerson added inline comments to D101234: GlobalISel: Use DAG call lowering infrastructure in a more compatible way.
May 4 2021, 10:57 AM · Restricted Project

Apr 30 2021

aemerson committed rG7d2562c2daad: [AArch64][GlobalISel] Use a single MachineIRBuilder for most of isel. NFC. (authored by aemerson).
[AArch64][GlobalISel] Use a single MachineIRBuilder for most of isel. NFC.
Apr 30 2021, 2:51 PM
aemerson closed D101590: [AArch64][GlobalISel] Use a single MachineIRBuilder for most of isel. NFC..
Apr 30 2021, 2:51 PM · Restricted Project

Apr 29 2021

aemerson requested review of D101590: [AArch64][GlobalISel] Use a single MachineIRBuilder for most of isel. NFC..
Apr 29 2021, 5:08 PM · Restricted Project
aemerson abandoned D101571: [GlobalISel] Use an empty LostDebugLocObserver when building with NDEBUG..

Actually this seems to be already disabled on release builds, but my sampling was catching the empty set checks in analyzeDebugLocations(). Not a big enough deal to worry about.

Apr 29 2021, 2:49 PM · Restricted Project
aemerson committed rGfa2340574c5b: [GlobalISel][Legalizer] Bump up a smallvector size that was found to be too… (authored by aemerson).
[GlobalISel][Legalizer] Bump up a smallvector size that was found to be too…
Apr 29 2021, 2:41 PM
aemerson requested review of D101571: [GlobalISel] Use an empty LostDebugLocObserver when building with NDEBUG..
Apr 29 2021, 2:32 PM · Restricted Project
aemerson committed rG96ec6d91e4da: [AArch64][GlobalISel] Simplify out of range rotate amount. (authored by aemerson).
[AArch64][GlobalISel] Simplify out of range rotate amount.
Apr 29 2021, 2:06 PM
aemerson closed D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..
Apr 29 2021, 2:06 PM · Restricted Project
aemerson added a comment to D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..

Looks fine to me. Could also do it for funnel shifts if you want.

Apr 29 2021, 1:37 PM · Restricted Project
aemerson committed rG2fa14d470051: Try to fix bots. We shouldn't be setting the entrybuilder's DL to a null one. (authored by aemerson).
Try to fix bots. We shouldn't be setting the entrybuilder's DL to a null one.
Apr 29 2021, 3:51 AM
aemerson committed rGd138e97c2a74: [GlobalISel] Bump CallLoweringInfo::OrigArgs initial size to 32. NFC. (authored by aemerson).
[GlobalISel] Bump CallLoweringInfo::OrigArgs initial size to 32. NFC.
Apr 29 2021, 1:02 AM

Apr 28 2021

aemerson committed rGaa0b9200e8c5: [GlobalISel][IRTranslator] Move line zero DebugLoc creation to constant… (authored by aemerson).
[GlobalISel][IRTranslator] Move line zero DebugLoc creation to constant…
Apr 28 2021, 11:55 PM
aemerson accepted D101478: [AArch64][GlobalISel] Don't match thread-local globals in matchFoldGlobalOffset.

Wow, that was a nasty one. Thanks for tracking it down. LGTM.

Apr 28 2021, 1:36 PM · Restricted Project

Apr 26 2021

aemerson updated the diff for D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..

Remove constant folding check.

Apr 26 2021, 2:47 PM · Restricted Project

Apr 23 2021

aemerson updated the diff for D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..

Only run this for AArch64.

Apr 23 2021, 11:34 AM · Restricted Project
aemerson added a comment to D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..

What's the point of this? Does it somehow end up generating better code?

It allows us to select immediate forms of rotate instructions for AArch64.

I would expect most targets to handle that during instruction selection by ignoring the high bits of the rotate amount, but perhaps there's some reason why it's awkward to do that for AArch64. Would it make sense for your new combine to be completely AArch64-specific? Currently you have added it to all_combines so it will be run on other targets too.

Apr 23 2021, 10:42 AM · Restricted Project

Apr 22 2021

aemerson updated the diff for D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..
  • Add more tests.
  • Factor out the APInt checking part of the constant folder to be used as a query.
  • Enable CSEInfo in the postlegalizer combiner so that we don't have to instantiate a constant-folding MIRBuilder.
Apr 22 2021, 2:16 PM · Restricted Project
aemerson added a comment to D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..

What's the point of this? Does it somehow end up generating better code?

If it is useful, you could also do the same for FSHL and FSHR.

Apr 22 2021, 10:57 AM · Restricted Project

Apr 21 2021

aemerson added inline comments to D101005: [AArch64][GlobalISel] Simplify out of range rotate amount..
Apr 21 2021, 6:06 PM · Restricted Project