aemerson (Amara Emerson)
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Sep 9 2013, 3:45 AM (253 w, 6 d)

Compilers at a fruit company

Recent Activity

Tue, Jul 3

aemerson committed rL336209: [AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to unselectable….
[AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to unselectable…
Tue, Jul 3, 9:04 AM

Mon, Jul 2

aemerson committed rL336120: [AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin..
[AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin.
Mon, Jul 2, 9:44 AM

Sun, Jun 24

aemerson requested changes to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.
Sun, Jun 24, 7:17 PM

Jun 20 2018

aemerson added a comment to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.

Hi Daniel, sorry for the delay.

Jun 20 2018, 10:39 PM

Jun 4 2018

aemerson committed rL333970: [MIRParser] Add parser support for 'true' and 'false' i1s..
[MIRParser] Add parser support for 'true' and 'false' i1s.
Jun 4 2018, 5:21 PM
aemerson closed D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 4 2018, 5:21 PM

Jun 2 2018

aemerson updated the diff for D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 2 2018, 4:13 AM
aemerson added inline comments to D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 2 2018, 3:40 AM

Jun 1 2018

aemerson updated the diff for D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 1 2018, 7:44 AM
aemerson committed rL333747: [AArch64][GlobalISel] Zero-extend s1 values when returning..
[AArch64][GlobalISel] Zero-extend s1 values when returning.
Jun 1 2018, 6:24 AM
aemerson closed D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
Jun 1 2018, 6:24 AM
aemerson added inline comments to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
Jun 1 2018, 6:24 AM

May 31 2018

aemerson accepted D47547: [GISel]: Some more pattern match opcodes.

LGTM.

May 31 2018, 8:34 AM
aemerson updated the diff for D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..

New patch now only zero-extends for stores, removing the use of getBooleanContents.

May 31 2018, 6:50 AM
aemerson added inline comments to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.
May 31 2018, 5:30 AM

May 29 2018

aemerson updated subscribers of D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..

I'll re-do this patch to unconditionally zero-extend for returns and also fix up the G_STORE legalisation to always zero-extend too. Given we don't have any target hooks that give us the information we need, let's go with just matching SelectionDAG behaviour?

May 29 2018, 4:37 PM
aemerson added inline comments to D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
May 29 2018, 4:34 PM
aemerson added inline comments to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
May 29 2018, 3:20 PM
aemerson added inline comments to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
May 29 2018, 3:00 PM
aemerson added a comment to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..

I got my branches mixed up, this patch is missing test updates. Will upload a new one soon.

May 29 2018, 10:47 AM
aemerson committed rL333427: Revert "[AArch64] added FP16 vcvth intrinsic support".
Revert "[AArch64] added FP16 vcvth intrinsic support"
May 29 2018, 8:38 AM

May 28 2018

aemerson accepted D46338: [GlobalISel][Legalizer] LegalizerInfo verifier: checking that legalization rules cover all type indices.

Overall I'm in favour of this change, so LGTM.

May 28 2018, 10:37 AM

May 27 2018

aemerson created D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
May 27 2018, 9:14 AM
aemerson created D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
May 27 2018, 9:08 AM

May 23 2018

aemerson added a comment to D46863: [X86] Use __builtin_convertvector to implement some of the packed integer to packed float conversion intrinsics..

Hi Craig,

May 23 2018, 12:54 PM

May 22 2018

aemerson added a comment to D46267: [test-suite] Enable MicroBenchmarks by default.

Looks like this change caused http://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-aarch64-O0-g/1944/ as well as others.

May 22 2018, 7:40 AM
aemerson committed rC332973: Revert "CodeGen, Driver: Start using direct split dwarf emission in clang.".
Revert "CodeGen, Driver: Start using direct split dwarf emission in clang."
May 22 2018, 4:23 AM
aemerson committed rL332973: Revert "CodeGen, Driver: Start using direct split dwarf emission in clang.".
Revert "CodeGen, Driver: Start using direct split dwarf emission in clang."
May 22 2018, 4:23 AM
aemerson committed rL332972: Revert "Fix another make_unique ambiguity.".
Revert "Fix another make_unique ambiguity."
May 22 2018, 4:23 AM
aemerson committed rC332972: Revert "Fix another make_unique ambiguity.".
Revert "Fix another make_unique ambiguity."
May 22 2018, 4:22 AM
aemerson committed rC332971: Revert "Add missing x86-registered-target.".
Revert "Add missing x86-registered-target."
May 22 2018, 4:22 AM
aemerson committed rL332971: Revert "Add missing x86-registered-target.".
Revert "Add missing x86-registered-target."
May 22 2018, 4:22 AM

May 18 2018

aemerson committed rL332755: Delete a test that was missed in the revert r332747..
Delete a test that was missed in the revert r332747.
May 18 2018, 12:25 PM
aemerson added a comment to D46889: [DWARF] Extract indexing code into a separate class hierarchy.

Thanks for jumping on this Amara — I just wanted to point out that we ususally don't revert lldb changes that only break the lldb-xcode bot if they pass on the lldb-cmake bot at the same time. When this happens it usually means that the lldb Xcode project must be updated and it's too much to ask from all open source contributors to get access to a machine running Xcode to do this. Instead one of the Apple LLDB developers usually goes in and updates the Xcode project for them.

  • adrian
May 18 2018, 11:25 AM
aemerson reopened D46889: [DWARF] Extract indexing code into a separate class hierarchy.

Hi Pavel,

May 18 2018, 9:04 AM
aemerson committed rL332730: Revert "[DWARF] Extract indexing code into a separate class hierarchy".
Revert "[DWARF] Extract indexing code into a separate class hierarchy"
May 18 2018, 9:03 AM
aemerson added a comment to D46889: [DWARF] Extract indexing code into a separate class hierarchy.

This caused a failure in green dragon: http://green.lab.llvm.org/green/job/lldb-xcode/6644

May 18 2018, 8:34 AM

May 16 2018

aemerson abandoned D40856: [X86][Darwin] Add Darwin stack probing functions.
May 16 2018, 3:50 AM
aemerson abandoned D40861: [X86] Add support for stack probing on x86_64 Darwin.
May 16 2018, 3:49 AM
aemerson abandoned D40857: [AArch64][Darwin] Add new ARM64 stack probing function for Darwin.
May 16 2018, 3:49 AM
aemerson abandoned D40863: [AArch64][Darwin] Implement stack probing for static and dynamic stack objects.
May 16 2018, 3:48 AM
aemerson abandoned D40858: [ASan][Darwin] Update ASAN tests to disable the new stack probing behaviour on Darwin..
May 16 2018, 3:47 AM
aemerson abandoned D40864: [Darwin] Add a new -mstack-probe option and enable by default.

Did this eventually go in?

May 16 2018, 3:39 AM
aemerson committed rL332449: [GlobalISel][IRTranslator] Split aggregates during IR translation..
[GlobalISel][IRTranslator] Split aggregates during IR translation.
May 16 2018, 3:36 AM
aemerson closed D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.
May 16 2018, 3:36 AM

May 15 2018

aemerson updated the diff for D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.

I think I've addressed most of the issues. I've tried to clean up the computeValueLLTs function a little bit, still perhaps not ideal. Dead code has been removed (I think an earlier revision of the patch required it for the tests to pass). Also added the tests you wrote, thanks.

May 15 2018, 3:29 PM

May 14 2018

aemerson added a comment to D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.

Some review comments not addressed yet, will add a test requested in a later revision.

May 14 2018, 3:36 PM
aemerson updated the diff for D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.

Thanks. -time-passes shows that IRTranslator is now using around 2MB. It's also taking most of the compile time vs other passes like your initial analysis showed, but we trade off the legalizer doing much less work.

May 14 2018, 3:34 PM
aemerson added a comment to D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.

I've made the changes to not generate copies for the insertvalue/extractvalue, but how did you measure the memory consumption of the individual passes? With the change it now produces 4k lines of assembly on your test case, vs 3.5k assembly. The MIR is much larger but that's because of the extra GEPs and G_CONSTANTs. Compile time is now comparable to without this change.

May 14 2018, 8:40 AM

May 10 2018

aemerson added a comment to D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.

Also, I looked briefly into https://bugs.llvm.org/show_bug.cgi?id=37397 recently, and I tried to apply this patch and see what it would do. It generated considerably more code (final assembly) comparing to itself and FastISel both (I'd eyeball the difference as 3x) and didn't seem to fix the issue with initializing upper bits of a boolean value.

Generally, I feel concerned about the quality (runtime performance) of generated code with this approach.

My thoughts were that we'd take a compile time hit with this, although in the end it was mostly neutral, but the code size would regress as you saw. The idea was to have a pre-legalizer combiner (Aditya had a prototype demo of one to show how the combiner API would work). Either that, or we have a clean up phase at the end of IRTranslator where we eliminate G_INSERT and G_EXTRACT pairs, perhaps with some caching of potentially redundant sets of these instructions due to pack/unpack regs as translation is happening, and then a quick pass to eliminate them without searching the whole function.

May 10 2018, 4:35 PM
aemerson added inline comments to D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.
May 10 2018, 1:23 PM

May 9 2018

aemerson committed rL331888: [DAGCombine] Change store merge candidates check cut off to 1024..
[DAGCombine] Change store merge candidates check cut off to 1024.
May 9 2018, 8:57 AM
aemerson closed D46581: [DAGCombine] Change store merge candidates check cut off to 1024.
May 9 2018, 8:57 AM

May 8 2018

aemerson added a comment to D46581: [DAGCombine] Change store merge candidates check cut off to 1024.

The actual problem here seems to be superlinear performance with this cutoff value. The 5x I mentioned was inappropriate as that was over a whole compile and compared to an old version of LLVM, before the store merging after legalisation patch for AArch64 was landed in December. The actual problem in my test case, which is admittedly a very large one, is that with the original value of 8192, I get around 330s runtime for my test case, at Max=2048 its 189s, Max=1024 its 34s, Max=512 21s, Max=256 20s. So somewhere between 512 and 1024 we start to see this superlinear compile time.

May 8 2018, 10:21 AM
aemerson added a comment to D45541: [globalisel] Update GlobalISel emitter to match new representation of extending loads.

Hi Amara,

I think we lost 0.5% on compile time on CTMark because of this. Is there any scope left here for performance improvements? With the addition of the combiner landing later, I expect a further CT hit so anything we can do here would be good.

Just a quick question: 0.5% loss on the entire compile time or only some part of the pipeline?

May 8 2018, 9:54 AM
aemerson added inline comments to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.
May 8 2018, 8:33 AM
aemerson added a comment to D45541: [globalisel] Update GlobalISel emitter to match new representation of extending loads.

I think we lost 0.5% on compile time on CTMark because of this. Is there any scope left here for performance improvements? With the addition of the combiner landing later, I expect a further CT hit so anything we can do here would be good.

May 8 2018, 8:04 AM
aemerson added a comment to D46581: [DAGCombine] Change store merge candidates check cut off to 1024.

I ran the test suite and SPEC2000/2006 benchmarks and didn't see any significant change with this.

May 8 2018, 7:37 AM
aemerson created D46581: [DAGCombine] Change store merge candidates check cut off to 1024.
May 8 2018, 7:35 AM
aemerson added inline comments to D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.
May 8 2018, 6:49 AM

May 7 2018

aemerson accepted D46310: [AArch64] Disallow vector operand if FPR128 Q register is required..

Thanks, LGTM.

May 7 2018, 3:09 AM

Apr 29 2018

aemerson added inline comments to D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.
Apr 29 2018, 2:33 PM

Apr 26 2018

aemerson accepted D46095: [GlobalISel] Reporting rules covered as part of the InstructionSelect's debug-only printing.
Apr 26 2018, 8:11 AM

Apr 25 2018

aemerson committed rL330831: [AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic..
[AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic.
Apr 25 2018, 7:47 AM

Apr 24 2018

aemerson updated the summary of D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.
Apr 24 2018, 9:00 AM
aemerson created D46018: [GlobalISel][IRTranslator] Split aggregates during IR translation.
Apr 24 2018, 8:55 AM

Apr 23 2018

aemerson accepted D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.

Maybe we could have all the tests in one file called prelegalize-combine-extloads.mir

I went with three files to match how we've been organizing the tests for the other passes but you raise a good point here. There's a good argument for the combiner being tested with one file per CombinerHelper::try*() function. I think that's probably a better organization.

I'm assuming this is in Target/AArch64 because other targets haven't been updated to use the new opcodes yet? We do eventually want to use these representations for every target though right?

That's right. As you say, we'll want to support it in every target that supports the extending loads (which is most if not all of the in-tree targets). However, until the new opcodes are legal for those targets, there's not much point in combining them only to revert them back to load+extend in the legalizer.

One other thing to mention is that we don't have a target-independent combiner in GlobalISel at the moment. Each target implements its own combiner(s) and makes use of code in CombinerHelper (where appropriate) to share code. I expect these combines to be used by multiple targets so I've put the bulk of the code in CombinerHelper but each target will need to add a pass and call to it.

Apr 23 2018, 8:34 AM

Apr 19 2018

aemerson committed rL330384: Move a dump() implementation out of line..
Move a dump() implementation out of line.
Apr 19 2018, 5:48 PM

Apr 18 2018

aemerson added a comment to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.

I'm assuming this is in Target/AArch64 because other targets haven't been updated to use the new opcodes yet? We do eventually want to use these representations for every target though right?

Apr 18 2018, 5:38 PM
aemerson accepted D45540: [globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them.

LGTM, with addition of -verify-machineinstrs to the tests.

Apr 18 2018, 5:30 PM
aemerson accepted D45466: [globalisel][legalizerinfo] Add support for legalization based on the MachineMemOperand.

LGTM.

Apr 18 2018, 5:14 PM
aemerson committed rL330276: [AArch64] Add isel pattern for v8i8->v2f32 NVCASTs..
[AArch64] Add isel pattern for v8i8->v2f32 NVCASTs.
Apr 18 2018, 10:14 AM

Apr 11 2018

aemerson abandoned D45023: [GlobalOpt] Implement static evaluation of memcpy intrinsics for const i8 arrays..

The motivating use case for this was actually fixed in clang, r325478. Although this may be useful in future for other front-ends/clients of LLVM, this can be revived if needed later.

Apr 11 2018, 8:37 AM

Apr 10 2018

aemerson committed rL329743: [AArch64] Fix isel failure when BUILD_PAIR nodes are left over..
[AArch64] Fix isel failure when BUILD_PAIR nodes are left over.
Apr 10 2018, 12:05 PM

Apr 9 2018

aemerson accepted D45067: [GISel] Refactor MachineIRBuilder so we can optionally do constant folding/other transformations during building.

LGTM, thanks.

Apr 9 2018, 3:09 AM
aemerson accepted D45366: Support generic expansion of ordered vector reduction (PR36732).
Apr 9 2018, 2:41 AM

Apr 6 2018

aemerson added a comment to D45336: Apply accumulator to fadd/fmul experimental vector reductions (PR36734).

The other issue is that while these intrinsics were experimental (it was on my todo list for later this year to change that), AArch64 has been using them with their original intended semantics for a while now. If we change that, IR generated from a released compiler will be miscompiled since it now becomes legal to fold away undef accumulator reductions to undef, unless we do some IR auto-upgrading based on the bitcode version.

If they are flagged as experimental surely we can't be held resposible for changes in behaviour?

AArch64 was the test guinea pig for this new representation, and it's proved to be a smooth transition. If you change the semantics now, even if the intrinsics are still experimental in name, IR from LLVM 6.0 may be silently miscompiled if someone implements a valid optimization based on your new proposal. That's a fact, and I don't think this patch review is the right place to discuss that if you want to do this, I suggest you send a new RFC or revive the old one.

Apr 6 2018, 1:27 PM
aemerson added a comment to D45336: Apply accumulator to fadd/fmul experimental vector reductions (PR36734).

Simon asked this on the PR, let's continue the discussion in one place:

Do we really want to completely ignore an intrinsic argument depending on the fast flags? There might be valid reasons to want to include an accumulation value.

The raison d'être for the argument is for ordered reductions, and the intrinsics were designed to allow the expression of the reduction idiom only, in light of newer vector architectures where the previous representation was inadequate. The use of an accumulator argument for fast reductions wasn't necessary, so the semantics were supposed to be defined in the most minimal form. The accumulator can easily be expressed as a extractelement->op->insertelement sequence. The question here I think becomes our good old friend: what should the canonical form be?

Apr 6 2018, 11:29 AM
aemerson added a comment to D45336: Apply accumulator to fadd/fmul experimental vector reductions (PR36734).

@aemerson

I think I missed out a detail when I wrote the langref, original motivation of the scalar accumulator argument was for the use in strictly ordered FP reductions only. I.e. when the intrinsic call has no FMF flags attached then the accumulator argument is used, otherwise if there are no FMF flags then the argument is meant to be ignored.

Why do we need the accumulator for this case? That is, why can't we just do:

result = vector[0];
for i in [1, vector.len) {
    result = binary_op(result, vector[i]);
}
return result;

I also wonder whether requiring fast-math to allow tree reductions is overkill. Tree reductions can be implemented reasonably efficiently in many architectures, while linearly ordered reduction appear to me to be more of a niche. Therefore, I wonder if it wouldn't make more sense to add llvm.experimental.vector.reduce.tree.{add,mul} that perform tree reductions without requiring fast math, and to just call those from here if fast-math is enabled.

Apr 6 2018, 9:08 AM
aemerson added inline comments to D45336: Apply accumulator to fadd/fmul experimental vector reductions (PR36734).
Apr 6 2018, 7:11 AM

Mar 29 2018

aemerson created D45023: [GlobalOpt] Implement static evaluation of memcpy intrinsics for const i8 arrays..
Mar 29 2018, 6:13 AM

Mar 26 2018

aemerson added a comment to D43962: [GlobalISel][utils] Adding the init version of Instruction Select Testgen.

Hi Roman,

Mar 26 2018, 4:04 PM

Mar 23 2018

aemerson committed rL328311: [GlobalISel] Fix legalizer combine to not use illegal input G_EXTRACT..
[GlobalISel] Fix legalizer combine to not use illegal input G_EXTRACT.
Mar 23 2018, 5:51 AM

Mar 22 2018

aemerson accepted D44762: [GISel]: Fix incorrect IRTranslation while translating null pointer types.

LGTM.

Mar 22 2018, 10:17 AM

Mar 19 2018

aemerson accepted D44291: [ARM,AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes.
Mar 19 2018, 11:08 AM

Mar 16 2018

aemerson added inline comments to D44291: [ARM,AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes.
Mar 16 2018, 7:19 AM

Mar 15 2018

aemerson added inline comments to D44291: [ARM,AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes.
Mar 15 2018, 6:17 AM

Mar 13 2018

aemerson added a comment to D42512: [X86] When using Win64 ABI, exit with error if SSE is disabled for varargs.
In D42512#1026016, @rnk wrote:

This doesn't fix the crash, though. We just assert later now.

Mar 13 2018, 10:44 AM

Mar 8 2018

aemerson accepted D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

LGTM, can you also make the test name a little more specific, e.g. 'vecreduce-propagate-sd-flags.ll'?

Mar 8 2018, 2:32 PM
aemerson added a comment to D44245: Propagate flags to SDValue in SplitVecOp_VECREDUCE.

Please add a test.

Mar 8 2018, 8:23 AM

Mar 1 2018

aemerson added a comment to D43108: Support for the mno-stack-arg-probe flag.

By default, stack probes are enabled (i.e., -mstack-arg-probe is the default behavior) and have the size of 4K in x86.

This part what I wanted to clarify, -mstack-probe-arg is enabling stack probes if the ABI requires it only, not for other reasons like security.

Mar 1 2018, 3:39 AM

Feb 28 2018

aemerson added a comment to D43108: Support for the mno-stack-arg-probe flag.

Can we clarify the meaning of this option a bit. The doc you've added here is saying that -mno-stack-arg-probe disables stack probes. Then what does -mstack-arg-probe mean specifically? Does it mean that only stack probes for ABI required reasons are enabled, or probes are done even in cases where the ABI doesn't require them? Either way, the doc needs to be clearer on the exact purpose.

Feb 28 2018, 4:17 PM

Feb 27 2018

aemerson accepted D43796: [GISel]: Print useful remarks when GISelAbort = 1 .

Seems reasonable.

Feb 27 2018, 5:33 AM

Feb 26 2018

aemerson updated the diff for D42512: [X86] When using Win64 ABI, exit with error if SSE is disabled for varargs.

Changed to use errorUnsupported() so we get some diagnostics first.

Feb 26 2018, 8:08 AM

Feb 21 2018

aemerson added inline comments to D43444: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
Feb 21 2018, 11:00 PM
aemerson closed D43444: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.

r325550.

Feb 21 2018, 4:02 AM

Feb 19 2018

aemerson committed rL325550: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to….
[AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to…
Feb 19 2018, 9:16 PM
aemerson accepted D43444: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.

As stated in PR36345 I'm committing this now to get it into 6.0.

Feb 19 2018, 8:25 PM

Feb 18 2018

aemerson created D43444: [AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.
Feb 18 2018, 9:36 AM
aemerson committed rL325464: Fix unused assertion variable warning..
Fix unused assertion variable warning.
Feb 18 2018, 9:30 AM