aemerson (Amara Emerson)
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User Since
Sep 9 2013, 3:45 AM (263 w, 21 h)

Compilers at a fruit company

Recent Activity

Thu, Sep 20

aemerson requested review of D51953: [GlobalISel] Add a new IR canonicalization pass.
Thu, Sep 20, 5:58 AM
aemerson updated the diff for D51953: [GlobalISel] Add a new IR canonicalization pass.

@aditya_nandakumar I've added a target hook that defaults to enabling this.

Thu, Sep 20, 5:58 AM
aemerson accepted D48575: [GISel]; Add a helper legalization rule for legalizing addressspacecast if no-op.

This seems like something that most targets would want done by default. I wonder if we should have a standard set of legalizer actions that targets can use. LGTM anyway.

Thu, Sep 20, 5:52 AM

Mon, Sep 17

aemerson added a comment to D51953: [GlobalISel] Add a new IR canonicalization pass.

Hi Amara - would it be possible to add this as part of AArch64 pass pipeline? Adding this to all targets would result in needless burning of compile time for targets that don't need this.

Mon, Sep 17, 3:53 PM
aemerson added a comment to D51953: [GlobalISel] Add a new IR canonicalization pass.

This isn't really ideal because of how trivial it is currently. The issue is that if we added the capability to InstSimplify (which is where it would fit most naturally), we'd still end up with the problem of running the whole of InstSimplify in the GlobalISel pipeline. It's reasonable for now I think so I'll commit with the changes requested.

Mon, Sep 17, 9:24 AM
aemerson added a comment to D52131: [GISel][NFC]: Make MachineIRBuilder fully stateless.

Looks ok, if a bit cumbersome with the additional state (do we need to hold references to it?). I'd like to see how this state is used with the CSE builder first though.

Mon, Sep 17, 9:18 AM
aemerson committed rL342397: Revert "Revert r342183 "[DAGCombine] Fix crash when store merging created an….
Revert "Revert r342183 "[DAGCombine] Fix crash when store merging created an…
Mon, Sep 17, 7:43 AM

Thu, Sep 13

aemerson committed rL342183: [DAGCombine] Fix crash when store merging created an extract_subvector with….
[DAGCombine] Fix crash when store merging created an extract_subvector with…
Thu, Sep 13, 2:30 PM
aemerson closed D51831: [DAGCombine] Fix crash when store merging created an extract_subvector with invalid index.
Thu, Sep 13, 2:30 PM
aemerson added a comment to D51831: [DAGCombine] Fix crash when store merging created an extract_subvector with invalid index.

Ok, I'm surprised that would be a realistic scenario but I'll make the change. Thanks.

Thu, Sep 13, 11:02 AM

Wed, Sep 12

aemerson updated the diff for D51831: [DAGCombine] Fix crash when store merging created an extract_subvector with invalid index.

You're right, that's a simplified expression.

Wed, Sep 12, 3:38 PM
aemerson added a comment to D51831: [DAGCombine] Fix crash when store merging created an extract_subvector with invalid index.

Ping.

Wed, Sep 12, 7:13 AM
aemerson added a comment to D51953: [GlobalISel] Add a new IR canonicalization pass.

Hi Quentin,

Wed, Sep 12, 4:14 AM

Tue, Sep 11

aemerson created D51953: [GlobalISel] Add a new IR canonicalization pass.
Tue, Sep 11, 3:02 PM

Sat, Sep 8

aemerson created D51831: [DAGCombine] Fix crash when store merging created an extract_subvector with invalid index.
Sat, Sep 8, 6:32 AM

Wed, Sep 5

aemerson added a comment to D51145: Guard FMF context by excluding some FP operators from FPMathOperator.

I added one more non fmf instruction and there is room to add others if needed.

There's also discussion about the definition of FPMathOperator and the relation to FMF here:
https://bugs.llvm.org/show_bug.cgi?id=38086
D51646

Wed, Sep 5, 5:11 PM
aemerson added inline comments to D51646: DAG: Preserve FMF when creating fminnum/fmaxnum.
Wed, Sep 5, 5:08 PM

Tue, Sep 4

aemerson added a comment to D51145: Guard FMF context by excluding some FP operators from FPMathOperator.

Ok, to me it seems like instructions for which fast math flags can't apply shouldn't be classed as FPMathOperators. insertelement/extractelement are just moving raw bits. If we disallowed those instruction types in the FPMathOperator classof() then this problem should go away, and we don't incorrectly relax FP semantics like in the case I pointed out.

Tue, Sep 4, 6:22 AM

Fri, Aug 31

aemerson added a comment to D51145: Guard FMF context by excluding some FP operators from FPMathOperator.

I’m not seeing how FP instructions can not carry flags. The IR semantics are defined to be strict FP unless explicitly relaxed.

Fri, Aug 31, 12:35 PM
aemerson updated subscribers of D51145: Guard FMF context by excluding some FP operators from FPMathOperator.
Fri, Aug 31, 12:17 PM
aemerson added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

It can't do that all the time, with these G_ICMPs for example it also has to swap the predicate (not that we even have imported patterns that could possibly match for AArch64).

Why not?
I understand G_ICMPs are special, but we could come up with whatever complicated logic in TableGen.

Fri, Aug 31, 12:00 PM
aemerson added a comment to D51145: Guard FMF context by excluding some FP operators from FPMathOperator.

Hit submit too early:
So with the above code B will not have the flag cleared? If that's the case it doesn't seem right to me.

Fri, Aug 31, 11:45 AM
aemerson added a comment to D51145: Guard FMF context by excluding some FP operators from FPMathOperator.

So with this change, if you have:

Fri, Aug 31, 11:39 AM

Thu, Aug 30

aemerson added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

So overall I think we should have some form of IR canonicalization before translation for the majority of cases to be handled for -O0.

Thu, Aug 30, 10:21 AM
aemerson added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

Going back to a higher-level description for all that stuff, I wonder if ISel could already handle this.

Indeed, it seems easy, at least conceptually, to teach tablegen to check for the commuted patterns to get the immediate version whenever possible before trying the non-immediate variant.

It can't do that all the time, with these G_ICMPs for example it also has to swap the predicate (not that we even have imported patterns that could possibly match for AArch64).

Thu, Aug 30, 10:16 AM

Wed, Aug 29

aemerson added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

I'm not against a separate IR canonicalization stage, even though it's a bit overkill for this particular case. At the moment it looks like InstCombine is doing the canonicalizaton for this case, so re-running that is out of the question. A new pass looks to be on the cards. Anyone else have opinions on this?

Does that mean that something after the last InstCombine produces icmp's with the non-canonical operand order? If so maybe that something needs to be chased down and fixed instead.

Wed, Aug 29, 3:49 PM
aemerson added reviewers for D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last: bogner, aditya_nandakumar, volkan.

I'm not against a separate IR canonicalization stage, even though it's a bit overkill for this particular case. At the moment it looks like InstCombine is doing the canonicalizaton for this case, so re-running that is out of the question. A new pass looks to be on the cards. Anyone else have opinions on this?

Wed, Aug 29, 3:08 PM
aemerson added a comment to D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.

Hi Amara,

That patch worries me, because I feel that we are going to pull all the LLVM IR code that does canonicalization.
The way I see it, is the input IR should already be in a canonical form and thus we don't have to do that.

If that's not the case, I would argue that bad output code is fine (garbage in, garbage out).

What do you think?

Cheers,
-Quentin

Wed, Aug 29, 2:29 AM

Tue, Aug 28

aemerson added inline comments to D44704: [GlobalISel][X86][ARM] Relaxing type constraints on G_SHL and friends.
Tue, Aug 28, 4:58 PM
aemerson accepted D44704: [GlobalISel][X86][ARM] Relaxing type constraints on G_SHL and friends.

I'd like to get this in. LGTM but needs one issue addressed.

Tue, Aug 28, 4:56 PM
aemerson accepted D51197: [GISel]: Add missing opcodes for overflow intrinsics.

x86 is still using UADDE, and it's generated only by IRTranslator, so if you do this then x86 will lose support for compiling llvm.uadd.with.overflow intrinsics. @igorb what do you think?

Which is exposing a hole in our general GISel testing, where individual changes in passes can result in overall support for some input IR to be lost.

Hi,
I think currently X86 use G_UADDE generated by Legalizer to support 64bit add on 32bit architecture.

Regards,
Igor

Tue, Aug 28, 9:01 AM
aemerson created D51362: [GlobalISel][IRTranslator] Canonicalize G_ICMP to have constant operands last.
Tue, Aug 28, 8:34 AM
aemerson added a comment to D51197: [GISel]: Add missing opcodes for overflow intrinsics.

x86 is still using UADDE, and it's generated only by IRTranslator, so if you do this then x86 will lose support for compiling llvm.uadd.with.overflow intrinsics. @igorb what do you think?

Tue, Aug 28, 2:55 AM

Aug 21 2018

aemerson accepted D51005: [aarch64][mc] Don't lookup symbols when there is no symbol lookup callback.

Looks like Lang added the original code, but LGTM anyway. I even think we did this exact change downstream a few years ago at ARM...

Aug 21 2018, 8:05 AM

Aug 15 2018

aemerson committed rL339796: [InstCombine] Fix IC trying to create a xor of pointer types..
[InstCombine] Fix IC trying to create a xor of pointer types.
Aug 15 2018, 10:47 AM
aemerson closed D50775: [InstCombine] Fix IC trying to create a xor of pointer types.
Aug 15 2018, 10:47 AM
aemerson updated the diff for D50775: [InstCombine] Fix IC trying to create a xor of pointer types.

Sure, done.

Aug 15 2018, 10:36 AM
aemerson created D50775: [InstCombine] Fix IC trying to create a xor of pointer types.
Aug 15 2018, 6:39 AM

Aug 14 2018

aemerson committed rL339674: [GlobalISel][IRTranslator] Fix a bug in handling repeating struct types during….
[GlobalISel][IRTranslator] Fix a bug in handling repeating struct types during…
Aug 14 2018, 5:05 AM
This revision was not accepted when it landed; it landed in state Needs Revision.
Aug 14 2018, 5:05 AM
aemerson added inline comments to D50401: [GISel]: Add Opcodes for a few Libm Intrinsics.
Aug 14 2018, 4:59 AM
aemerson commandeered D49442: [GlobalISel] Fix offsets to valueIsSplit.

I'll take over and fix this in the way I suggested. Thanks for reporting this!

Aug 14 2018, 4:56 AM

Aug 10 2018

aemerson added a comment to D50401: [GISel]: Add Opcodes for a few Libm Intrinsics.

I'm a little uneasy about specifying libm in the names of the intrinsics. The langref mentions libm in the description, but the semantics don't exactly match due to ignoring errno. That said, I don't really have a suggestion for a better name, so the only thing I can ask is that we make it a bit more explicit in the documentation what we mean by "LIBM" here.

Aug 10 2018, 8:54 AM

Aug 8 2018

aemerson removed a reviewer for D49442: [GlobalISel] Fix offsets to valueIsSplit: llvm-commits.
Aug 8 2018, 8:23 AM

Aug 7 2018

aemerson added a comment to D49442: [GlobalISel] Fix offsets to valueIsSplit.

Thinking about this more, I can't think of any reason why we'd ever want to add offsets to an existing offset list. It would probably be better if valueIsSpit cleared the vector (and the doc comment made this clear).

Aug 7 2018, 12:36 PM
aemerson requested changes to D49442: [GlobalISel] Fix offsets to valueIsSplit.
Aug 7 2018, 12:31 PM
aemerson accepted D49442: [GlobalISel] Fix offsets to valueIsSplit.

Could you upload with more context please, and a test case?

Aug 7 2018, 12:30 PM

Jul 31 2018

aemerson committed rL338476: [GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate..
[GlobalISel][IRTranslator] Use RPO traversal when visiting blocks to translate.
Jul 31 2018, 7:18 PM

Jul 30 2018

aemerson committed rL338337: [AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR..
[AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR.
Jul 30 2018, 5:09 PM
aemerson committed rL338336: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal..
[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
Jul 30 2018, 5:09 PM
This revision was not accepted when it landed; it landed in state Needs Review.
Jul 30 2018, 5:09 PM
aemerson closed D49902: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
Jul 30 2018, 5:09 PM
aemerson committed rL338335: [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants..
[GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants.
Jul 30 2018, 5:09 PM
aemerson closed D49900: [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants..
Jul 30 2018, 5:09 PM
aemerson added inline comments to D49900: [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants..
Jul 30 2018, 11:14 AM
aemerson added inline comments to D48600: [GISel]:Add Opcodes for CTLZ/CTTZ/CTPOP.
Jul 30 2018, 5:46 AM

Jul 29 2018

aemerson added a comment to D49660: [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value.

Thanks for taking this on. I think some x86 tests would also be good here as there evidently isn't much coverage at the moment.

Jul 29 2018, 11:51 AM

Jul 26 2018

aemerson added a dependency for D49902: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal: D49900: [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants..
Jul 26 2018, 7:23 PM
aemerson added a dependent revision for D49900: [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants.: D49902: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
Jul 26 2018, 7:23 PM
aemerson added a dependent revision for D49902: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal: D49903: [AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR.
Jul 26 2018, 7:23 PM
aemerson added a dependency for D49903: [AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR: D49902: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
Jul 26 2018, 7:23 PM
aemerson created D49903: [AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR.
Jul 26 2018, 7:22 PM
aemerson created D49902: [AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
Jul 26 2018, 7:20 PM
aemerson created D49900: [GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants..
Jul 26 2018, 7:17 PM

Jul 25 2018

aemerson committed rL337994: [GlobalISel] Fall back to SDISel for swifterror/swiftself attributes..
[GlobalISel] Fall back to SDISel for swifterror/swiftself attributes.
Jul 25 2018, 6:26 PM

Jul 3 2018

aemerson committed rL336209: [AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to unselectable….
[AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to unselectable…
Jul 3 2018, 9:04 AM

Jul 2 2018

aemerson committed rL336120: [AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin..
[AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin.
Jul 2 2018, 9:44 AM

Jun 24 2018

aemerson requested changes to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.
Jun 24 2018, 7:17 PM

Jun 20 2018

aemerson added a comment to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.

Hi Daniel, sorry for the delay.

Jun 20 2018, 10:39 PM

Jun 4 2018

aemerson committed rL333970: [MIRParser] Add parser support for 'true' and 'false' i1s..
[MIRParser] Add parser support for 'true' and 'false' i1s.
Jun 4 2018, 5:21 PM
aemerson closed D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 4 2018, 5:21 PM

Jun 2 2018

aemerson updated the diff for D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 2 2018, 4:13 AM
aemerson added inline comments to D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 2 2018, 3:40 AM

Jun 1 2018

aemerson updated the diff for D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
Jun 1 2018, 7:44 AM
aemerson committed rL333747: [AArch64][GlobalISel] Zero-extend s1 values when returning..
[AArch64][GlobalISel] Zero-extend s1 values when returning.
Jun 1 2018, 6:24 AM
aemerson closed D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
Jun 1 2018, 6:24 AM
aemerson added inline comments to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
Jun 1 2018, 6:24 AM

May 31 2018

aemerson accepted D47547: [GISel]: Some more pattern match opcodes.

LGTM.

May 31 2018, 8:34 AM
aemerson updated the diff for D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..

New patch now only zero-extends for stores, removing the use of getBooleanContents.

May 31 2018, 6:50 AM
aemerson added inline comments to D45543: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64.
May 31 2018, 5:30 AM

May 29 2018

aemerson updated subscribers of D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..

I'll re-do this patch to unconditionally zero-extend for returns and also fix up the G_STORE legalisation to always zero-extend too. Given we don't have any target hooks that give us the information we need, let's go with just matching SelectionDAG behaviour?

May 29 2018, 4:37 PM
aemerson added inline comments to D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
May 29 2018, 4:34 PM
aemerson added inline comments to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
May 29 2018, 3:20 PM
aemerson added inline comments to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
May 29 2018, 3:00 PM
aemerson added a comment to D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..

I got my branches mixed up, this patch is missing test updates. Will upload a new one soon.

May 29 2018, 10:47 AM
aemerson committed rL333427: Revert "[AArch64] added FP16 vcvth intrinsic support".
Revert "[AArch64] added FP16 vcvth intrinsic support"
May 29 2018, 8:38 AM

May 28 2018

aemerson accepted D46338: [GlobalISel][Legalizer] LegalizerInfo verifier: checking that legalization rules cover all type indices.

Overall I'm in favour of this change, so LGTM.

May 28 2018, 10:37 AM

May 27 2018

aemerson created D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning..
May 27 2018, 9:14 AM
aemerson created D47424: [MIRParser] Add parser support for 'true' and 'false' i1s..
May 27 2018, 9:08 AM

May 23 2018

aemerson added a comment to D46863: [X86] Use __builtin_convertvector to implement some of the packed integer to packed float conversion intrinsics..

Hi Craig,

May 23 2018, 12:54 PM

May 22 2018

aemerson added a comment to D46267: [test-suite] Enable MicroBenchmarks by default.

Looks like this change caused http://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-aarch64-O0-g/1944/ as well as others.

May 22 2018, 7:40 AM
aemerson committed rC332973: Revert "CodeGen, Driver: Start using direct split dwarf emission in clang.".
Revert "CodeGen, Driver: Start using direct split dwarf emission in clang."
May 22 2018, 4:23 AM
aemerson committed rL332973: Revert "CodeGen, Driver: Start using direct split dwarf emission in clang.".
Revert "CodeGen, Driver: Start using direct split dwarf emission in clang."
May 22 2018, 4:23 AM
aemerson committed rL332972: Revert "Fix another make_unique ambiguity.".
Revert "Fix another make_unique ambiguity."
May 22 2018, 4:23 AM
aemerson committed rC332972: Revert "Fix another make_unique ambiguity.".
Revert "Fix another make_unique ambiguity."
May 22 2018, 4:22 AM
aemerson committed rC332971: Revert "Add missing x86-registered-target.".
Revert "Add missing x86-registered-target."
May 22 2018, 4:22 AM
aemerson committed rL332971: Revert "Add missing x86-registered-target.".
Revert "Add missing x86-registered-target."
May 22 2018, 4:22 AM

May 18 2018

aemerson committed rL332755: Delete a test that was missed in the revert r332747..
Delete a test that was missed in the revert r332747.
May 18 2018, 12:25 PM
aemerson added a comment to D46889: [DWARF] Extract indexing code into a separate class hierarchy.

Thanks for jumping on this Amara — I just wanted to point out that we ususally don't revert lldb changes that only break the lldb-xcode bot if they pass on the lldb-cmake bot at the same time. When this happens it usually means that the lldb Xcode project must be updated and it's too much to ask from all open source contributors to get access to a machine running Xcode to do this. Instead one of the Apple LLDB developers usually goes in and updates the Xcode project for them.

  • adrian
May 18 2018, 11:25 AM
aemerson reopened D46889: [DWARF] Extract indexing code into a separate class hierarchy.

Hi Pavel,

May 18 2018, 9:04 AM