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aemerson (Amara Emerson)
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User Since
Sep 9 2013, 3:45 AM (342 w, 1 d)

The sea was angry that day, my friends - like an old man trying to send back soup in a deli.

Recent Activity

Today

aemerson committed rG7f1ea924c695: Add a new -fglobal-isel option and make -fexperimental-isel an alias for it. (authored by aemerson).
Add a new -fglobal-isel option and make -fexperimental-isel an alias for it.
Tue, Mar 31, 12:35 PM
aemerson closed D77103: Add a new -fglobal-isel option and make -fexperimental-isel an alias for it..
Tue, Mar 31, 12:35 PM · Restricted Project, Restricted Project

Yesterday

aemerson added a comment to D77103: Add a new -fglobal-isel option and make -fexperimental-isel an alias for it..

Sorry, forgot to add cfe-commits to the original diff.

Mon, Mar 30, 4:24 PM · Restricted Project, Restricted Project
aemerson created D77103: Add a new -fglobal-isel option and make -fexperimental-isel an alias for it..
Mon, Mar 30, 4:24 PM · Restricted Project, Restricted Project
aemerson accepted D74738: Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types".

LGTM.

Mon, Mar 30, 4:24 PM · Restricted Project
aemerson added a comment to D76640: [GlobalISel] Combine (x op 0) -> x for operations with a right identity of 0.

LGTM too. One day I'm going to change all MOPs to MOp when you're not looking anyway.

Mon, Mar 30, 2:11 PM · Restricted Project

Tue, Mar 24

aemerson resigned from D76640: [GlobalISel] Combine (x op 0) -> x for operations with a right identity of 0.

Changed my mind again, I won't be a part of this.

Tue, Mar 24, 2:34 PM · Restricted Project
aemerson committed rG472d282046d0: [AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin. (authored by aemerson).
[AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin.
Tue, Mar 24, 2:01 PM
aemerson closed D76652: [AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin..
Tue, Mar 24, 2:01 PM · Restricted Project
aemerson requested changes to D76640: [GlobalISel] Combine (x op 0) -> x for operations with a right identity of 0.

I'm back in.

Tue, Mar 24, 12:53 PM · Restricted Project

Mon, Mar 23

aemerson updated subscribers of D76652: [AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin..
Mon, Mar 23, 11:57 PM · Restricted Project
aemerson created D76652: [AArch64][GlobalISel] Don't localize TLS G_GLOBAL_VALUEs on Darwin..
Mon, Mar 23, 5:26 PM · Restricted Project
aemerson added a comment to D76523: [GlobalISel] Combine G_SELECTs of the form (cond ? x : x) into x.

(after Matt's points).

Mon, Mar 23, 4:21 PM · Restricted Project
aemerson accepted D76523: [GlobalISel] Combine G_SELECTs of the form (cond ? x : x) into x.

LGTM.

Mon, Mar 23, 4:21 PM · Restricted Project
aemerson removed a reviewer for D76640: [GlobalISel] Combine (x op 0) -> x for operations with a right identity of 0: aemerson.
Mon, Mar 23, 3:48 PM · Restricted Project

Thu, Mar 19

aemerson accepted D76382: [GlobalISel] Port some basic shufflevector undef combines from the DAGCombiner.

LGTM.

Thu, Mar 19, 10:52 AM · Restricted Project

Mon, Mar 16

aemerson added a comment to D74738: Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types".

Could you fix up the ARM64 selection code as I mentioned earlier so we don't generate different instructions?

Mon, Mar 16, 12:01 PM · Restricted Project

Fri, Mar 6

aemerson committed rGc1a97e992da6: Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of… (authored by aemerson).
Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of…
Fri, Mar 6, 10:00 PM
aemerson added a reverting change for rG5583c2f2fba5: Revert "[GlobalISel][Localizer] Enable intra-block localization of already…: rGc1a97e992da6: Revert "Revert "[GlobalISel][Localizer] Enable intra-block localization of….
Fri, Mar 6, 10:00 PM
aemerson closed D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..
Fri, Mar 6, 9:59 PM · Restricted Project, Restricted Project

Thu, Mar 5

aemerson updated the diff for D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..

@omjavaid can you look over the lldb changes? I don't have the hardware to be able to actually run this test but I've tried to relax the checks.

Thu, Mar 5, 12:07 PM · Restricted Project, Restricted Project
aemerson added a comment to D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..

Hi @aemerson this change caused a regression in lldb testsuite on AArch64/Linux. Apparently stepping gets affected by your change. Kindly revisit.

I have temporarily reverted this change.

http://lab.llvm.org:8011/builders/lldb-aarch64-ubuntu/builds/2182

Thu, Mar 5, 11:31 AM · Restricted Project, Restricted Project

Wed, Mar 4

aemerson added a comment to D71217: Fix incorrect logic in maintaining the side-effect of compiler generated outliner functions.

Hi, I just tried out this patch locally and I'm seeing failures running the tests:

Failing Tests (3):
    LLVM :: CodeGen/AArch64/machine-outliner-cfi.mir
    LLVM :: CodeGen/AArch64/machine-outliner-noreturn-save-lr.mir
    LLVM :: CodeGen/AArch64/machine-outliner-side-effect.mir
Wed, Mar 4, 11:47 AM · Restricted Project

Tue, Mar 3

aemerson committed rGe91e1df6ab74: [GlobalISel][Localizer] Enable intra-block localization of already-local uses. (authored by aemerson).
[GlobalISel][Localizer] Enable intra-block localization of already-local uses.
Tue, Mar 3, 6:31 PM
aemerson closed D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..
Tue, Mar 3, 6:30 PM · Restricted Project, Restricted Project
aemerson added a comment to D74738: Revert "[GISel]: Fix incorrect IRTranslation while translating null pointer types".

Which part of the langref are you referring to?

Tue, Mar 3, 3:02 PM · Restricted Project
aemerson accepted D66916: GlobalISel: Set alignment on function argument stack load/store.

LGTM.

Tue, Mar 3, 3:00 PM · Restricted Project
aemerson updated the diff for D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..

Now with test updates.

Tue, Mar 3, 2:24 PM · Restricted Project, Restricted Project
aemerson added a comment to D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..

Actually this is missing a bunch of test updates....

Tue, Mar 3, 11:59 AM · Restricted Project, Restricted Project
aemerson created D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses..
Tue, Mar 3, 11:57 AM · Restricted Project, Restricted Project
aemerson added a reviewer for D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses.: arsenm.
Tue, Mar 3, 11:57 AM · Restricted Project, Restricted Project

Feb 28 2020

aemerson accepted D75207: GlobalISel: Move Localizer::shouldLocalize(..) to TargetLowering.

The change itself is ok but is there any way to have more granular overriding of this behavior, instead of overriding the whole shouldLocalize()?

We can have two functions (one for checking the opcode and another one for the cost), but this doesn't allow targets to localize target specific instruction. That's why I decided move the whole thing to TargetLowering. Do you think having two targets hooks would be better?

Feb 28 2020, 1:33 PM · Restricted Project

Feb 27 2020

aemerson added a comment to D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..

I understand that cross copies are bad, but what I don't understand is why don't we form an extended load? That would apply nicely to your example.

I see what you mean. Essentially we would take the code size/perf hit with the specific MIR example I used, but instead try harder to form the extending load ops and ensure those are assigned to gpr banks. There might be other issues with G_EXTRACT but we'll see.

Feb 27 2020, 10:31 AM · Restricted Project

Feb 26 2020

aemerson added a comment to D75207: GlobalISel: Move Localizer::shouldLocalize(..) to TargetLowering.

The change itself is ok but is there any way to have more granular overriding of this behavior, instead of overriding the whole shouldLocalize()?

Feb 26 2020, 3:42 PM · Restricted Project
aemerson added a comment to D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..

I committed before I saw your message.

Feb 26 2020, 3:33 PM · Restricted Project
aemerson committed rG65f99b5383ff: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before… (authored by aemerson).
[AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before…
Feb 26 2020, 2:12 PM
aemerson closed D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..
Feb 26 2020, 2:11 PM · Restricted Project
aemerson added a comment to D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..

s16 operations, if legal, just get selected to gpr32 regclass instructions. E.g.

%ld:gpr(s16) = G_LOAD ...
=>
%ld:gpr32 = LDR_16 ...

That's interesting, because that means you have inreg extension where you would have regular extension in the IR.
E.g.,

s16 = G_LOAD
s32 = G_ZEXT s16

=>

gpr32 = LDR_16
gpr32 = G_ZEXT gpr32

I would have expected that instead we would have combined loads with the related extension to from an extended load.

Yes, on AArch64 all sub-32bit loads give a free ZEXT. We catch this case in the selector if for some reason we have a redundant ZEXT.

Anyway, I guess this ship has sailed.

LGTM.

Feb 26 2020, 1:07 PM · Restricted Project
aemerson added a comment to D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..

Thanks for the clarification Amara.

Now a follow-up question:

If this happens, the PHI operand with a GPR RegBank gets the gpr32 regclass assigned to it (we don't have anything smaller to represent types like s16 on GPR on AArch64).

How do you represent s16 values into gpr32?

s16 operations, if legal, just get selected to gpr32 regclass instructions. E.g.

%ld:gpr(s16) = G_LOAD ...
=>
%ld:gpr32 = LDR_16 ...

For things like G_ADD we legalize to s32, but s16 itself as a type isn't illegal.

I would have expected that if you have to widen the size when assigning the actual register class, then legalization should have actually widen the value. Otherwise, that means we have to manually deal with "dangling" bits everywhere else.

Feb 26 2020, 10:54 AM · Restricted Project
aemerson added a comment to D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..

Forgot to answer your first question:

Feb 26 2020, 10:13 AM · Restricted Project
aemerson added a comment to D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..

I would expect G_PHI to be selected to PHI (i.e., just a opcode change) and then the phi elimination pass will insert the cross copies for you.

Where is this going wrong?

Thanks for taking a look. Yes the G_PHI gets selected to PHI. This is normally ok even in the case where we have operands with different regbanks. However on AArch64 this doesn't work when the type size is less than 32 bits. If this happens, the PHI operand with a GPR RegBank gets the gpr32 regclass assigned to it (we don't have anything smaller to represent types like s16 on GPR on AArch64). Then the FPR bank operand gets the appropriately sized FPR16 regclass assigned. These two registers have different sizes, and copyPhysReg doesn't know how to deal with copies between a gpr32 and an fpr16 or vice versa. I thought about maybe teaching copyPhysReg to deal with that, but the fact that we have to deal with subregisters (because of the differing sizes) makes me nervous and didn't seem like the best place to fix it.

Feb 26 2020, 9:50 AM · Restricted Project

Feb 24 2020

aemerson accepted D73968: GlobalISel: Reimplement fewerElementsVectorBasic.

Looks reasonable.

Feb 24 2020, 3:42 PM · Restricted Project
aemerson created D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection..
Feb 24 2020, 3:06 PM · Restricted Project

Feb 21 2020

aemerson added inline comments to D74943: [GISel][KnownBits]{NFC} Add a cache mechanism to speed compile time.
Feb 21 2020, 12:36 PM · Restricted Project

Feb 18 2020

aemerson accepted D74504: [AArch64][GlobalISel] Try to use existing reg classes in getRegClassesForCopy.

LGTM.

Feb 18 2020, 10:16 AM · Restricted Project
aemerson accepted D74508: [AArch64][GlobalISel] Don't always use all reg class in subreg class selection.

LGTM.

Feb 18 2020, 10:16 AM · Restricted Project

Feb 11 2020

aemerson accepted D74427: [AArch64][GlobalISel] Properly implement widening for TB(N)Z.

LGTM with nits.

Feb 11 2020, 3:08 PM · Restricted Project

Feb 10 2020

aemerson committed rG067dd9c6b12a: [GlobalISel][CallLowering] Use stripPointerCasts(). (authored by aemerson).
[GlobalISel][CallLowering] Use stripPointerCasts().
Feb 10 2020, 3:45 PM

Feb 9 2020

aemerson committed rG21c9d9ad43f0: [GlobalISel][CallLowering] Tighten constantexpr check for callee. (authored by aemerson).
[GlobalISel][CallLowering] Tighten constantexpr check for callee.
Feb 9 2020, 11:02 PM

Feb 7 2020

aemerson committed rG35c63d66aaae: [GlobalISel][CallLowering] Look through bitcasts from constant function… (authored by aemerson).
[GlobalISel][CallLowering] Look through bitcasts from constant function…
Feb 7 2020, 3:38 PM
aemerson closed D74241: [GlobalISel][CallLowering] Look through bitcasts from constant function pointers.
Feb 7 2020, 3:38 PM · Restricted Project
aemerson created D74241: [GlobalISel][CallLowering] Look through bitcasts from constant function pointers.
Feb 7 2020, 10:45 AM · Restricted Project
aemerson committed rG28d22c2c9c31: [GlobalISel][IRTranslator] Add special case support for ~memory inline asm… (authored by aemerson).
[GlobalISel][IRTranslator] Add special case support for ~memory inline asm…
Feb 7 2020, 9:04 AM
aemerson closed D74201: [GlobalISel][IRTranslator] Add special case support for ~memory inline asm clobber.
Feb 7 2020, 9:04 AM · Restricted Project
aemerson created D74201: [GlobalISel][IRTranslator] Add special case support for ~memory inline asm clobber.
Feb 7 2020, 1:15 AM · Restricted Project

Feb 6 2020

aemerson committed rGac8a12c874cc: [GlobalISel] Use G_ZEXTLOAD instead of an anyextending load for non-pow-2… (authored by aemerson).
[GlobalISel] Use G_ZEXTLOAD instead of an anyextending load for non-pow-2…
Feb 6 2020, 2:44 PM
aemerson added a comment to D74149: [AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1.

LGTM.

Feb 6 2020, 11:46 AM · Restricted Project
aemerson accepted D74149: [AArch64][GlobalISel] Emit TBZ for SGT cond branches against -1.
Feb 6 2020, 11:46 AM · Restricted Project

Feb 5 2020

aemerson accepted D73991: GlobalISel: Remove check for illegal MIR.
Feb 5 2020, 3:04 PM · Restricted Project
aemerson accepted D74077: [AArch64][GlobalISel] Fold G_LSHR into test bit calculation.

LGTM.

Feb 5 2020, 3:04 PM · Restricted Project
aemerson accepted D74090: [AArch64][GlobalISel] Emit TBNZ with G_BRCOND where the condition is SLT.

LGTM.

Feb 5 2020, 2:45 PM · Restricted Project
aemerson accepted D74080: [AArch64][GlobalISel][NFC] Factor out TB(N)Z emission code into its own function.

LGTM.

Feb 5 2020, 2:25 PM · Restricted Project
aemerson accepted D73933: [AArch64][GlobalISel] Fold G_ASHR into TB(N)Z bit calculation.

LGTM with nit.

Feb 5 2020, 9:55 AM · Restricted Project
aemerson accepted D74002: [AArch64][GlobalISel] Fix one use check in getTestBitReg.

LGTM.

Feb 5 2020, 9:55 AM · Restricted Project

Feb 4 2020

aemerson added a comment to D73030: GlobalISel: Assume G_INTRINSIC* are convergent.

If this change is made then CPU targets will need to create the new G_INTRINSIC_(DIVERGENT?) opcodes anyway, since not having sinkable intrinsics (like many vector ops, and some exotic scalar ones) won't be acceptable for optimization purposes. So I think we will need the two extra opcodes anyway. Unless we have a different mechanism to communicate this property, like an MI flag? Actually, the issue we had with "tail" attributes on the memcpy intrinsics might also benefit from finding a better solution to this properties issues.

Eventually, but none of these are problems I want to work on solving right now. My goal is to avoid subtle problems in the future, so I still think we should just go with this for now.

Feb 4 2020, 2:51 PM · Restricted Project
aemerson added a comment to D73030: GlobalISel: Assume G_INTRINSIC* are convergent.

I'm not 100% sure on what the convergent attribute means here, but assuming that it means it's not allowed to sink instructions into control flow etc, I don't think we should be marking these generic intrinsic ops with it. On arm64 we can use G_INTRINSIC to represent user-written intrinsic instructions which have no problem with being made control dependent.

The intrinsic opcodes need to conservatively assume it could call an intrinsic with any property. These can be used to call an intrinsic or call site marked as convergent, so they have to be convergent to be conservatively correct. Since nothing in the globalisel pipeline currently does any control flow sinking or anything, it's not worth the hassle of optimizing this by adding an additional 2 G_INTRINSIC* variants. Until that comes up, I'd rather leave this in the safe state so somebody doesn't silently break convergent handling at some point in the future.

The localizer is one pass that can sink instructions, although it currently doesn't do intrinsics yet.

Feb 4 2020, 1:18 PM · Restricted Project
aemerson added a comment to D73030: GlobalISel: Assume G_INTRINSIC* are convergent.

I'm not 100% sure on what the convergent attribute means here, but assuming that it means it's not allowed to sink instructions into control flow etc, I don't think we should be marking these generic intrinsic ops with it. On arm64 we can use G_INTRINSIC to represent user-written intrinsic instructions which have no problem with being made control dependent.

Feb 4 2020, 12:42 PM · Restricted Project

Feb 3 2020

aemerson accepted D73929: [AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation.

Can we have one extra test checking for a chain of G_XORs?

Feb 3 2020, 3:14 PM · Restricted Project
aemerson added inline comments to D73805: [AArch64] Provide Darwin variants of most calling conventions.
Feb 3 2020, 3:14 PM · Restricted Project
aemerson accepted D73924: [AArch64][GlobalISel] Fold G_SHL into TB(N)Z bit calculation.
Feb 3 2020, 2:22 PM · Restricted Project
aemerson committed rGb911b99052e9: [AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd(). (authored by aemerson).
[AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd().
Feb 3 2020, 11:58 AM
aemerson closed D73910: [AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd().
Feb 3 2020, 11:57 AM · Restricted Project
aemerson accepted D73790: [AArch64][GlobalISel] Walk through G_AND in TB(N)Z bit calculation.

LGTM.

Feb 3 2020, 11:19 AM · Restricted Project
aemerson created D73910: [AArch64][GlobalISel] Don't reconvert to p0 in convertPtrAddToAdd().
Feb 3 2020, 11:00 AM · Restricted Project
aemerson added inline comments to D73805: [AArch64] Provide Darwin variants of most calling conventions.
Feb 3 2020, 10:11 AM · Restricted Project
aemerson accepted D72610: GlobalISel: Implement fewerElementsVector for G_SEXT_INREG.

It's a real struggle for me to review AMDGPU legalizer changes sometimes. I wish we had smaller, more obvious for the change being made.

Feb 3 2020, 10:02 AM · Restricted Project

Jan 31 2020

aemerson accepted D73748: [AArch64][GlobalISel] Walk through G_TRUNC in getTestBitReg.

LGTM.

Jan 31 2020, 10:26 AM · Restricted Project
aemerson accepted D72842: [GlobalISel] Tweak lowering of G_SMULO/G_UMULO.

Didn't mean to reject.

Jan 31 2020, 10:08 AM · Restricted Project
aemerson requested changes to D72842: [GlobalISel] Tweak lowering of G_SMULO/G_UMULO.
Jan 31 2020, 10:08 AM · Restricted Project
aemerson accepted D72842: [GlobalISel] Tweak lowering of G_SMULO/G_UMULO.

LGTM.

Jan 31 2020, 10:08 AM · Restricted Project
aemerson added inline comments to D73790: [AArch64][GlobalISel] Walk through G_AND in TB(N)Z bit calculation.
Jan 31 2020, 9:49 AM · Restricted Project

Jan 30 2020

aemerson committed rG84bd85110858: [GlobalISel][IRTranslator] When translating vector geps, splat the base pointer… (authored by aemerson).
[GlobalISel][IRTranslator] When translating vector geps, splat the base pointer…
Jan 30 2020, 4:32 PM
aemerson added a comment to D73403: GlobalISel: Translate vector GEPs.

This is causing an assertion error in consumer-typeset for AArch64 at -O3.

llvm-test-suite/MultiSource/Benchmarks/MiBench/consumer-typeset/z29.c

Assertion failed: (Res.getLLTTy(*getMRI()).isScalar() == Op.getLLTTy(*getMRI()).isScalar()), function buildExtOrTrunc, file /Users/gruyere/llvm-project/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp, line 460.

Any thoughts?

What does the failing GEP look like?

Jan 30 2020, 4:32 PM · Restricted Project
aemerson committed rG6170272ab9ae: [AArch64][GlobalISel] Disallow vectors in convertPtrAddToAdd. (authored by aemerson).
[AArch64][GlobalISel] Disallow vectors in convertPtrAddToAdd.
Jan 30 2020, 2:56 PM
aemerson accepted D73673: [AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z.

LGTM.

Jan 30 2020, 1:50 PM · Restricted Project
aemerson added inline comments to D73673: [AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z.
Jan 30 2020, 11:14 AM · Restricted Project
aemerson added inline comments to D72842: [GlobalISel] Tweak lowering of G_SMULO/G_UMULO.
Jan 30 2020, 8:32 AM · Restricted Project
aemerson closed D73663: [AArch64][GlobalISel] During ISel try to convert G_PTR_ADD to G_ADD.

Committed in 610f1d22f149 but with wrong phab link in commit msg.

Jan 30 2020, 8:23 AM · Restricted Project
aemerson added a comment to D73673: [AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z.

Could you re-upload your patch so it can be reviewed?

Jan 30 2020, 12:08 AM · Restricted Project
aemerson reopened D73673: [AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z.

Oops, linked to the wrong review in the commit message and ended up auto-closing this by mistake.

Jan 30 2020, 12:01 AM · Restricted Project

Jan 29 2020

aemerson committed rG610f1d22f149: [AArch64][GlobalISel] During ISel try to convert G_PTR_ADD to G_ADD. (authored by aemerson).
[AArch64][GlobalISel] During ISel try to convert G_PTR_ADD to G_ADD.
Jan 29 2020, 11:31 PM
aemerson closed D73673: [AArch64][GlobalISel] Fold in G_ANYEXT/G_ZEXT into TB(N)Z.
Jan 29 2020, 11:31 PM · Restricted Project
aemerson created D73663: [AArch64][GlobalISel] During ISel try to convert G_PTR_ADD to G_ADD.
Jan 29 2020, 1:59 PM · Restricted Project
aemerson committed rGc12f046eb96f: [GlobalISel] Add new combine to convert scalar G_MUL to G_SHL. (authored by aemerson).
[GlobalISel] Add new combine to convert scalar G_MUL to G_SHL.
Jan 29 2020, 1:40 PM
aemerson closed D73659: [GlobalISel] Add new combine to convert G_MUL to G_SHL..
Jan 29 2020, 1:40 PM · Restricted Project
aemerson updated the diff for D73659: [GlobalISel] Add new combine to convert G_MUL to G_SHL..

Forgot to rename test file.

Jan 29 2020, 1:31 PM · Restricted Project
aemerson updated the diff for D73659: [GlobalISel] Add new combine to convert G_MUL to G_SHL..

I've made the test XFAIL for now. Address other comments.

Jan 29 2020, 1:31 PM · Restricted Project
aemerson accepted D73660: [AArch64][GlobalISel] Fix TBNZ/TBZ opcode selection.

LGTM.

Jan 29 2020, 1:03 PM · Restricted Project
aemerson added a comment to D73659: [GlobalISel] Add new combine to convert G_MUL to G_SHL..

@arsenm Matt when I run the update_llc_test_checks script on the llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll test, it crashes with a backtrace like this:

Assertion failed: (Opcode < NumOpcodes && "Invalid opcode!"), function get, file /Users/aemerson/work/oss/co1/src/llvm/include/llvm/MC/MCInstrInfo.h, line 4
frame #4: 0x00000001000bdef3 llc`llvm::MCInstrInfo::get(this=0x0000000110010248, Opcode=4294967295) const at MCInstrInfo.h:45:5
frame #5: 0x000000010083b8d7 llc`llvm::SIInstrInfo::getMCOpcodeFromPseudo(this=0x0000000110010240, Opcode=3758) const at SIInstrInfo.h:939:12
frame #6: 0x00000001008277e3 llc`llvm::SIInstrInfo::getInstSizeInBytes(this=0x0000000110010240, MI=0x000000010f879b28) const at SIInstrInfo.cpp:6067:29
frame #7: 0x0000000101f9bf44 llc`(anonymous namespace)::BranchRelaxation::computeBlockSize(this=0x000000010f03fb60, MBB=0x000000010f8bbf28) const at BranchRelaxation.cpp:168:18
frame #8: 0x0000000101f9b7be llc`(anonymous namespace)::BranchRelaxation::scanFunction(this=0x000000010f03fb60) at BranchRelaxation.cpp:158:39
frame #9: 0x0000000101f9b264 llc`(anonymous namespace)::BranchRelaxation::runOnMachineFunction(this=0x000000010f03fb60, mf=0x000000010f0566f0) at BranchRelaxation.cpp:555:3

I'm replacing a G_MUL with an equivalent G_SHL here, is there an issue with doing this for AMDGPU?

Jan 29 2020, 12:54 PM · Restricted Project
aemerson created D73659: [GlobalISel] Add new combine to convert G_MUL to G_SHL..
Jan 29 2020, 12:53 PM · Restricted Project