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simoncook (Simon Cook)
Compiler Engineer, Embecosm

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User Since
Mar 11 2015, 2:39 PM (289 w, 3 d)

Recent Activity

Aug 20 2020

simoncook updated the diff for D62732: [RISCV] Add SystemV ABI.

Rebase

Aug 20 2020, 2:21 AM · Restricted Project

Aug 4 2020

simoncook added a comment to D62732: [RISCV] Add SystemV ABI.

Thanks for looking at this @luismarques We had planned to put more effort into this patch, but time got in the way for quite a lot, but I'm glad it's working; thanks for the rebase I'll update this to match shortly. And it's good that it looks like it's mostly working. I'm curious about your backtrace showing one frame, is that something without debug information, since the example I was using when writing this did show a backtrace back to main? It would be good to understand why that disn't produce the expected output.

Aug 4 2020, 9:42 AM · Restricted Project

Jul 16 2020

simoncook added a comment to D80802: [RISCV] Upgrade RVV MC to v0.9..

The modification is put in D81213.

Jul 16 2020, 11:33 AM · Restricted Project, Restricted Project
simoncook added a comment to D80802: [RISCV] Upgrade RVV MC to v0.9..

Since this patch replaces 0.8 support with 0.9, it should include an update to the version check in clang/lib/Driver/ToolChains/Arch/RISCV.cpp to match.

Jul 16 2020, 4:30 AM · Restricted Project, Restricted Project

Jul 15 2020

simoncook added a comment to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

It's a shame this just missed the creation of the llvm 11.0 branch, do we think it's worth trying to get this backported since it only just missed?

Jul 15 2020, 9:26 AM · Restricted Project
simoncook committed rGde7bf722c23a: [RISCV] Add error checking for extensions missing separating underscores (authored by simoncook).
[RISCV] Add error checking for extensions missing separating underscores
Jul 15 2020, 1:25 AM
simoncook closed D83819: [RISCV] Add error checking for extensions missing separating underscores.
Jul 15 2020, 1:25 AM · Restricted Project
simoncook added a comment to D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.

I'm not familiar with the vector extension, but given the title of the patch, I have an integration question: It looks like this is enabled by use of the vector target feature, but the name 'Zvlsseg' suggests it's something optional/extra. If the intent to have this enabled unconditionally with 'v', or does it make sense to add features like what was done for bitmanip, where each 'Zb*' part can be enabled/disabled indepenently?

Jul 15 2020, 12:56 AM · Restricted Project

Jul 14 2020

Herald added a project to D83819: [RISCV] Add error checking for extensions missing separating underscores: Restricted Project.
Jul 14 2020, 2:55 PM · Restricted Project

Jun 18 2020

simoncook added a comment to D81946: [WIP][RISCV] Enable multilib support even without a detected GCC install.

Thanks for this Ed. I've tried building a toolchain with it and noticed a couple of things:

Jun 18 2020, 2:41 AM · Restricted Project

May 21 2020

simoncook added a comment to D80367: [RISCV][MC] Print absolute targets of branch instructions.

Why does RISC-V need PrintRequiresAddr?

May 21 2020, 9:41 AM · Restricted Project
simoncook created D80367: [RISCV][MC] Print absolute targets of branch instructions.
May 21 2020, 1:04 AM · Restricted Project

Apr 30 2020

simoncook added a comment to D78702: [RFC][RISCV][MC/Objdump] Extend llvm-objdump output to support more instruction patterns.

Simon can you please rebase, it seems D78776 got merged and now conflicts. Thank you.

Apr 30 2020, 3:01 AM · Restricted Project

Apr 23 2020

simoncook created D78702: [RFC][RISCV][MC/Objdump] Extend llvm-objdump output to support more instruction patterns.
Apr 23 2020, 4:49 AM · Restricted Project

Apr 21 2020

simoncook added a reviewer for D69987: [RISCV] Assemble/Disassemble v-ext instructions.: simoncook.

This is looking good, overall the patch is nicely laid out which has made it easy to compare against the spec.

Apr 21 2020, 2:39 AM · Restricted Project, Restricted Project

Apr 14 2020

simoncook added inline comments to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..
Apr 14 2020, 10:10 AM · Restricted Project

Apr 13 2020

simoncook added inline comments to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..
Apr 13 2020, 8:01 AM · Restricted Project
simoncook added a comment to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Looking at the structure this is looking good, it's probably worth renaming the codegen tests to match what I did with the MC patch before commiting ('Z'->'z') but other than a few formatting changes, this seems good. I haven't yet read through all the patterns, I'll add more comments as I go through it.

Apr 13 2020, 3:44 AM · Restricted Project

Apr 10 2020

simoncook committed rG562bc307c03d: [Driver] Improve help message for -ffixed-xX flags (authored by simoncook).
[Driver] Improve help message for -ffixed-xX flags
Apr 10 2020, 3:44 AM

Apr 9 2020

simoncook committed rG61ff29637501: [RISCV] Add Clang frontend support for Bitmanip extension (authored by s.egerton).
[RISCV] Add Clang frontend support for Bitmanip extension
Apr 9 2020, 1:14 PM
simoncook closed D71553: [RISCV] Add Clang frontend support for Bitmanip extension.
Apr 9 2020, 1:14 PM · Restricted Project
simoncook committed rGdd1ee6dc076f: [RISCV] Support experimental/unratified extensions (authored by simoncook).
[RISCV] Support experimental/unratified extensions
Apr 9 2020, 1:13 PM
simoncook closed D73891: [RISCV] Support experimental/unratified extensions.
Apr 9 2020, 1:13 PM · Restricted Project
simoncook committed rGfae40bd5a1d4: [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0. (authored by PaoloS).
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.
Apr 9 2020, 1:13 PM
simoncook closed D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
Apr 9 2020, 1:13 PM · Restricted Project
simoncook committed rG2df6a02fd75f: [RISCV] Implement evaluateBranch (authored by simoncook).
[RISCV] Implement evaluateBranch
Apr 9 2020, 7:35 AM
simoncook closed D77567: [RISCV] Implement evaluateBranch.
Apr 9 2020, 7:35 AM · Restricted Project
simoncook added a comment to D76767: [RISCV] Support negative constants in CompressInstEmitter.

To clarify, we were not missing in compressed instructions before, this change is for the future compressed instructions to be added, confirmed? Otherwise I need to check why we missed it with the fuzzer.

Apr 9 2020, 2:08 AM · Restricted Project
simoncook added a comment to D77567: [RISCV] Implement evaluateBranch.

Thanks, Simon for pushing this patch, it does help when debugging code and removes the dependence on binutils.

In the future patch for other instructionsm are you including lui/addi combo and addi with gp?

Apr 9 2020, 2:08 AM · Restricted Project

Apr 7 2020

simoncook updated the summary of D77567: [RISCV] Implement evaluateBranch.
Apr 7 2020, 2:40 AM · Restricted Project

Apr 6 2020

simoncook updated the diff for D77567: [RISCV] Implement evaluateBranch.

Resolve issue found by clang-tidy

Apr 6 2020, 10:51 AM · Restricted Project
simoncook created D77567: [RISCV] Implement evaluateBranch.
Apr 6 2020, 9:44 AM · Restricted Project

Apr 1 2020

simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Rebase on updated MC patch

Apr 1 2020, 9:00 AM · Restricted Project

Mar 26 2020

simoncook committed rG1e303962232d: [RISCV] Support negative constants in CompressInstEmitter (authored by simoncook).
[RISCV] Support negative constants in CompressInstEmitter
Mar 26 2020, 8:39 AM
simoncook closed D76767: [RISCV] Support negative constants in CompressInstEmitter.
Mar 26 2020, 8:39 AM · Restricted Project
simoncook added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
In D65649#1943742, @asb wrote:

I'm reviewing this with an eye to merging it, but one big thing that comes to mind is the compressed instructions. The draft bitmanip spec describes these under "Future compressed instructions" and says "It presumably would make sense for a future revision of the “C” extension to include compressed opcodes for those instructions." My reading is that this is more of a sketch of potential encodings and a less firm proposal than the 32-bit encodings described elsewhere in the spec. Do you disagree with that assessment?

Mar 26 2020, 8:38 AM · Restricted Project
simoncook updated the summary of D76767: [RISCV] Support negative constants in CompressInstEmitter.
Mar 26 2020, 7:00 AM · Restricted Project
simoncook updated the diff for D76767: [RISCV] Support negative constants in CompressInstEmitter.

Actually solve the underlying problem.

Mar 26 2020, 7:00 AM · Restricted Project

Mar 25 2020

simoncook added a comment to D76767: [RISCV] Support negative constants in CompressInstEmitter.

Context for this patch: it's needed for CompressPats for bitmanip - since one of the compressed instructions should match against -1

Mar 25 2020, 5:23 AM · Restricted Project
simoncook created D76767: [RISCV] Support negative constants in CompressInstEmitter.
Mar 25 2020, 5:22 AM · Restricted Project

Mar 19 2020

simoncook added inline comments to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..
Mar 19 2020, 4:49 AM · Restricted Project
simoncook added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

This is starting to look good. I've checked all the encodings, and other than c.zext.w having the wrong value all the encodings are right.

Mar 19 2020, 4:49 AM · Restricted Project

Mar 18 2020

simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

Address own feedback on RISCV.td and cpp files

Mar 18 2020, 1:04 AM · Restricted Project

Mar 17 2020

simoncook updated the diff for D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

Address feedback

Mar 17 2020, 12:57 PM · Restricted Project
simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

Address review comments and clang-format changes

Mar 17 2020, 12:56 PM · Restricted Project
simoncook updated the diff for D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

Rebase on new dependencies

Mar 17 2020, 7:57 AM · Restricted Project
simoncook updated the diff for D73891: [RISCV] Support experimental/unratified extensions.
  • Update to match latest dependencies
  • Handle adding "experimental-" to SubtargetFeatures for experimental features
Mar 17 2020, 7:57 AM · Restricted Project
simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Rebase on updated D65649

Mar 17 2020, 7:57 AM · Restricted Project
simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
  • Update patch now AssemblerPredicate update has landed
  • Add "experimental-" to all bitmanip SubtargetFeatures
Mar 17 2020, 7:57 AM · Restricted Project

Mar 13 2020

simoncook added inline comments to D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.
Mar 13 2020, 4:13 PM · Restricted Project
simoncook accepted D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Patch makes sense, and looking at the newly generated XRegisterBank.inc files, all LGTM

Mar 13 2020, 3:40 PM · Restricted Project
simoncook committed rGa26bd4ec1652: [TableGen] Support combining AssemblerPredicates with ORs (authored by simoncook).
[TableGen] Support combining AssemblerPredicates with ORs
Mar 13 2020, 10:45 AM
simoncook closed D74338: [TableGen] Support combining AssemblerPredicates with ORs.
Mar 13 2020, 10:45 AM · Restricted Project
simoncook retitled D74338: [TableGen] Support combining AssemblerPredicates with ORs from [RFC][TableGen] Support combining AssemblerPredicates with ORs to [TableGen] Support combining AssemblerPredicates with ORs.
Mar 13 2020, 8:33 AM · Restricted Project
simoncook added a comment to D74338: [TableGen] Support combining AssemblerPredicates with ORs.

It'd be nice if a single predicate wouldn't need all_of, but I don't feel strongly about it.

Mar 13 2020, 5:46 AM · Restricted Project

Feb 28 2020

simoncook committed rGca950a6bb197: [RISCV] Compress instructions based on function features (authored by simoncook).
[RISCV] Compress instructions based on function features
Feb 28 2020, 4:13 AM
simoncook closed D73339: [RISCV] Compress instructions based on function features.
Feb 28 2020, 4:13 AM · Restricted Project
simoncook added inline comments to D73339: [RISCV] Compress instructions based on function features.
Feb 28 2020, 2:08 AM · Restricted Project

Feb 27 2020

simoncook added reviewers for D74338: [TableGen] Support combining AssemblerPredicates with ORs: ostannard, nhaehnle.
Feb 27 2020, 8:53 AM · Restricted Project

Feb 24 2020

simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Following feedback from @nhaehnle (http://lists.llvm.org/pipermail/llvm-dev/2020-February/139186.html) I have re-designed this to look more TableGen like (i.e. using DAGs instead of strings to describe the predicate). I have declared two operators any_of and all_of which I think read better than and and or in these cases when just looking at the target files.

Feb 24 2020, 3:24 AM · Restricted Project

Feb 13 2020

simoncook added a comment to D74338: [TableGen] Support combining AssemblerPredicates with ORs.

It's a logical addition to the semantics of features. Though at the moment RV is probably the only user of this addition, the eventual patch implementing it should not include the RV specific changes, which would be better in a separate patch.

Feb 13 2020, 1:11 PM · Restricted Project
simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Add test for RISCV Instruction Compression, so now all uses of AssemblerCondString are covered by this patch.

Feb 13 2020, 9:47 AM · Restricted Project
simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Add AsmWriter test

Feb 13 2020, 7:56 AM · Restricted Project
simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Incorporate feedback, add test of disassembler and assembly matching test (asmwriter test is WIP)

Feb 13 2020, 5:50 AM · Restricted Project
simoncook updated the diff for D73339: [RISCV] Compress instructions based on function features.

Add floating point test, combine compress tests into single test file.

Feb 13 2020, 4:15 AM · Restricted Project
simoncook added a comment to D73339: [RISCV] Compress instructions based on function features.

It may be a bit of a hacky solution, but how about this? You keep one test file, add the attribute group references to the test functions, but don't add the attribute group definition to the source. Then in the RUN lines you cat the test source together with either an empty attribute group (the original tests) or the one with the target features.

Feb 13 2020, 2:49 AM · Restricted Project

Feb 12 2020

simoncook added a comment to D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Thanks for the feedback @luismarques and @lewis-revill.

Feb 12 2020, 9:10 AM · Restricted Project

Feb 11 2020

simoncook added a comment to D73339: [RISCV] Compress instructions based on function features.

Copying the the STI isn't quite trivial, and we're only using a small subset of what it provides, in compressInst. Can't this be done more tightly?

compressInst calls RISCVValidateMCOperand, which checks things like STI.getTargetTriple().isArch64Bit(). You said that "under LTO it is common to not specify the architecture". If that includes not properly initializing the STI target triple then those checks will fail in some circumstances. Please check also the status of the other members of the STI, in case the validation ends up using them in the future.

Feb 11 2020, 2:44 AM · Restricted Project

Feb 10 2020

simoncook created D74338: [TableGen] Support combining AssemblerPredicates with ORs.
Feb 10 2020, 9:10 AM · Restricted Project
simoncook updated the diff for D73891: [RISCV] Support experimental/unratified extensions.

Rebase, incorporate changes suggested by Lewis

Feb 10 2020, 3:32 AM · Restricted Project

Feb 7 2020

simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Update to keep in sync with feature names in D65649

Feb 7 2020, 5:26 PM · Restricted Project
simoncook added inline comments to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
Feb 7 2020, 5:26 PM · Restricted Project
simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

(Actually update patch rather than rebase of previous version)

Feb 7 2020, 5:26 PM · Restricted Project
simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

Update Target Features to be of form zb<x> rather than just b<x>.

Feb 7 2020, 5:17 PM · Restricted Project
simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Update Target Features to be of form zb<x> rather than just b<x>.

Feb 7 2020, 5:17 PM · Restricted Project
simoncook updated the diff for D73891: [RISCV] Support experimental/unratified extensions.

Add support for Z extensions also under this scheme.

Feb 7 2020, 5:08 PM · Restricted Project
simoncook planned changes to D73891: [RISCV] Support experimental/unratified extensions.

With the update to D69987 adding the Zvqmac predicate, it seems both the b and v extensions have Z extensions that also need supporting using this method, I'll update this to also support Z shortly, but don't expect the general method to change, just adding the same version check elsewhere.

Feb 7 2020, 2:48 AM · Restricted Project

Feb 4 2020

simoncook updated the diff for D73891: [RISCV] Support experimental/unratified extensions.

Switch to using Optional for returning version numbers.

Feb 4 2020, 4:07 AM · Restricted Project
simoncook added inline comments to D73891: [RISCV] Support experimental/unratified extensions.
Feb 4 2020, 2:47 AM · Restricted Project

Feb 3 2020

simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Rebase on other bitmanip patches

Feb 3 2020, 8:28 AM · Restricted Project
simoncook updated the diff for D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

Rebase changes on top of experimental feature support (D73891)

Feb 3 2020, 8:10 AM · Restricted Project
simoncook commandeered D71553: [RISCV] Add Clang frontend support for Bitmanip extension.
Feb 3 2020, 8:10 AM · Restricted Project
simoncook updated the diff for D73891: [RISCV] Support experimental/unratified extensions.

Don't put option in m_riscv_Features_Group, we don't want it being handled like a feature.

Feb 3 2020, 8:10 AM · Restricted Project
simoncook created D73891: [RISCV] Support experimental/unratified extensions.
Feb 3 2020, 6:50 AM · Restricted Project

Jan 24 2020

simoncook created D73339: [RISCV] Compress instructions based on function features.
Jan 24 2020, 2:51 AM · Restricted Project

Dec 10 2019

simoncook committed rGa6e50e40e6dd: [RISCV] Improve assembler missing feature warnings (authored by simoncook).
[RISCV] Improve assembler missing feature warnings
Dec 10 2019, 8:53 AM
simoncook closed D69899: [RISCV] Improve assembler missing feature warnings.
Dec 10 2019, 8:53 AM · Restricted Project

Nov 18 2019

simoncook committed rGeedb9648229f: [RISCV] Add assembly mnemonic spell checking (authored by simoncook).
[RISCV] Add assembly mnemonic spell checking
Nov 18 2019, 2:59 AM
simoncook closed D69894: [RISCV] Add assembly mnemonic spell checking.
Nov 18 2019, 2:59 AM · Restricted Project
simoncook committed rGc00e5cf29d49: [RISCV] Set triple based on -march flag (authored by simoncook).
[RISCV] Set triple based on -march flag
Nov 18 2019, 2:57 AM
simoncook closed D54214: [RISCV] Set triple based on -march flag.
Nov 18 2019, 2:56 AM · Restricted Project

Nov 7 2019

simoncook updated the diff for D54214: [RISCV] Set triple based on -march flag.

@lenary Following the discussion regarding D69383, I think it's best for now to keep the logic just keeping -march directly, rather than using getRISCVArch. I think in the case of -target risc32-..... -mabi=lp64 I think it would confuse users if the tools suddenly changed to doing an rv64 compile. If we disable that, all that function would provide me is the same StringRef I'm already evaluating. I think adding any extra flag to indicate whether a rv32<->rv64 switch is acceptable would just make the code unnecessarily more messy. I think in the future if getRISCVArch evaluates more flags, then it might make sense to reconsider this.

Nov 7 2019, 9:42 AM · Restricted Project
simoncook added a comment to D69899: [RISCV] Improve assembler missing feature warnings.

This looks good to me, the only thing that I'm not sure about is the phrasing of the warnings:

"error: instruction requires the following: RV32I Base Instruction Set"

For a naive user (like me) I think the 'I' could make them focus on the extension as the problem, not the fact that's it's RV32 vs RV64.

Nov 7 2019, 3:42 AM · Restricted Project

Nov 6 2019

simoncook updated the diff for D69899: [RISCV] Improve assembler missing feature warnings.

Add diff that has useful context

Nov 6 2019, 8:45 AM · Restricted Project
simoncook created D69899: [RISCV] Improve assembler missing feature warnings.
Nov 6 2019, 8:45 AM · Restricted Project
simoncook created D69894: [RISCV] Add assembly mnemonic spell checking.
Nov 6 2019, 7:04 AM · Restricted Project

Nov 5 2019

simoncook added inline comments to D69741: [Codegen] Both sides of '&&' are same; fixed.
Nov 5 2019, 3:54 AM · Restricted Project

Oct 25 2019

simoncook added a comment to D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults.

I have a question about backwards compatibility with this patch. Clang 9 has shipped with rvXXg/etc defaulting to ilp32/lp64 ABI, and no march meaning rvXXi, with users having built objects with those defaults. When Clang 10 ships, users they now need to always use a mabi/march flag to keep the same compatibility with their Clang 9 flows, the enabled extensions and ABI will be changed under their feet without warning (or at least until they either hit a linker error in the ABI case, or potentially an invalid instruction trap in the march case).

Oct 25 2019, 1:34 AM · Restricted Project

Oct 23 2019

simoncook added a comment to D67185: [RISCV] Add support for -ffixed-xX flags.

@simoncook: your commit doesn't include handling the case of TLS lowering when -ffixed-x4 is used.

Oct 23 2019, 5:47 AM · Restricted Project, Restricted Project

Oct 22 2019

simoncook committed rGaed9d6d64a38: [RISCV] Add support for -ffixed-xX flags (authored by simoncook).
[RISCV] Add support for -ffixed-xX flags
Oct 22 2019, 1:35 PM