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simoncook (Simon Cook)
Compiler Engineer, Embecosm

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User Since
Mar 11 2015, 2:39 PM (327 w, 1 d)

Recent Activity

Sun, Jun 6

simoncook added inline comments to D103539: RISCV: adjust handling of relocation emission for RISCV.
Sun, Jun 6, 1:54 PM · Restricted Project

Apr 15 2021

simoncook accepted D100532: [RISCV] Don't emit save-restore call if function is a interrupt handler.
Apr 15 2021, 3:49 AM · Restricted Project
simoncook added a comment to D100532: [RISCV] Don't emit save-restore call if function is a interrupt handler.

This LGTM, I've left a note on a potential comment update, but otherwise looks good

Apr 15 2021, 1:27 AM · Restricted Project

Jan 25 2021

simoncook added a comment to D95302: [RISCV] Remove isel patterns for Zbs *W instructions..

Is there value in still having most of these tests without the pattern? Some of these now look like tests just of andn, and in others now that enabling b or zbs has no effect on code generation. I wonder if this change should instead just completely remove the edited tests. If future additions make them relevant again they could later be readded.

Jan 25 2021, 4:07 AM · Restricted Project
simoncook committed rGa7c1239f3749: [RISCV] Add attribute support for all supported extensions (authored by simoncook).
[RISCV] Add attribute support for all supported extensions
Jan 25 2021, 12:59 AM
simoncook committed rG666815d61bc2: [RISCV] Implement new architecture extension macros (authored by simoncook).
[RISCV] Implement new architecture extension macros
Jan 25 2021, 12:59 AM
simoncook closed D94931: [RISCV] Add attribute support for all supported extensions.
Jan 25 2021, 12:59 AM · Restricted Project
simoncook closed D94403: [RISCV] Implement new architecture extension macros.
Jan 25 2021, 12:59 AM · Restricted Project

Jan 24 2021

simoncook updated the diff for D94931: [RISCV] Add attribute support for all supported extensions.

Update for bitmanip 0.93

Jan 24 2021, 2:29 PM · Restricted Project
simoncook updated the diff for D94403: [RISCV] Implement new architecture extension macros.
  • Update to bitmanip 0.93
  • Expand and support vector as per workaround in D95146
  • Add negative testing (check __riscv_b not defined for just subextension)
Jan 24 2021, 2:28 PM · Restricted Project
simoncook committed rGafd483e57d16: [RISCV] Add support for Zvamo/Zvlsseg to driver (authored by simoncook).
[RISCV] Add support for Zvamo/Zvlsseg to driver
Jan 24 2021, 2:27 PM
simoncook closed D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver.
Jan 24 2021, 2:26 PM · Restricted Project
simoncook planned changes to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.
Jan 24 2021, 2:10 PM · Restricted Project
simoncook committed rGf3f3c9c2549a: [RISCV] Fix name of Zba extension (NFC) (authored by simoncook).
[RISCV] Fix name of Zba extension (NFC)
Jan 24 2021, 1:03 PM

Jan 22 2021

simoncook updated the diff for D94931: [RISCV] Add attribute support for all supported extensions.
  • Emit extensions in canonical order
  • Update V tests to match current compiler support
  • Add tests for canonical order/parsing multiletter with version numbers
  • Fix parsing issue found by updated tests
Jan 22 2021, 10:09 AM · Restricted Project
simoncook added a comment to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.

So how about GCC/binutils, GNU toolchain using a weird work-around here, v implied zvamo and zvlsseg, and zvamo/zvlsseg/zvqmacc implied v...

Jan 22 2021, 1:07 AM · Restricted Project

Jan 21 2021

simoncook added a comment to D95146: [RISCV] Make v extension imply zvamo, zvlsseg.

Doesn't this mean that if you only enable zvlsseg, you'll be able to use the instruction in that extension but not the vsetvli instruction that you need to program the VL register?

Jan 21 2021, 10:33 AM · Restricted Project
simoncook requested review of D95146: [RISCV] Make v extension imply zvamo, zvlsseg.
Jan 21 2021, 9:19 AM · Restricted Project
simoncook added inline comments to D94931: [RISCV] Add attribute support for all supported extensions.
Jan 21 2021, 8:16 AM · Restricted Project

Jan 19 2021

simoncook updated the diff for D94403: [RISCV] Implement new architecture extension macros.

Have 'b'/'v' features imply subfeatures

Jan 19 2021, 8:49 AM · Restricted Project
simoncook added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

I think maybe we could extract the arch parser from driver[1] to llvm/lib/Support, so that we could just maintain one parser for driver and assembler, and there is also other potential user for that, like the C front-end for the target attribute, e.g. __attribute__ ((target ("arch=rv64gcv"))), and the linker can re-use that to read/merge/write the attribute too.

[1] https://github.com/llvm/llvm-project/blob/main/clang/lib/Driver/ToolChains/Arch/RISCV.cpp#L171

Jan 19 2021, 1:30 AM · Restricted Project
simoncook updated the diff for D94931: [RISCV] Add attribute support for all supported extensions.

Add support to llvm/lib/Object/ELFObjectFile.cpp

Jan 19 2021, 1:12 AM · Restricted Project
simoncook added a comment to D94931: [RISCV] Add attribute support for all supported extensions.

Do you consider to modify ELFObjectFileBase::getRISCVFeatures() in llvm/lib/Object/ELFObjectFile.cpp?

Jan 19 2021, 12:53 AM · Restricted Project

Jan 18 2021

simoncook added inline comments to D94931: [RISCV] Add attribute support for all supported extensions.
Jan 18 2021, 2:24 PM · Restricted Project
simoncook requested review of D94931: [RISCV] Add attribute support for all supported extensions.
Jan 18 2021, 12:32 PM · Restricted Project
simoncook updated the diff for D94403: [RISCV] Implement new architecture extension macros.

Rebase on D94930 to show updated version

Jan 18 2021, 12:29 PM · Restricted Project
simoncook requested review of D94930: [RISCV] Add support for Zvamo/Zvlsseg to driver.
Jan 18 2021, 12:28 PM · Restricted Project
simoncook added a comment to D94403: [RISCV] Implement new architecture extension macros.

Thanks you implement that on clang, I think it's really great to included that in LLVM 12 release.

I would like to define marco for sub-extension too, I know that's my fault, I didn't specify the behavior of sub-extension clearly on the spec, but I think it would be great if we also define sub-extension marcos, since it would be easier to check when some core only implement sub-extension, and the code can just check the sub-extensio rather than check both.

Jan 18 2021, 10:09 AM · Restricted Project

Jan 13 2021

simoncook added a comment to D94568: [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec..

RVB 0.93 is an awkward version to me, there is mnemonic conflict which is not resolved during release process since it's kind of too rush, the conflict one is bext in zbe and zbs...

However it's also a milestone for B-ext, since this version claim zba, zbb and zbc is frozen, maybe those 3 sub-ext. could be removed from the umbrella of -menable-experimental-extension ?

@asb What do you think about this?

Jan 13 2021, 2:41 AM · Restricted Project

Jan 11 2021

simoncook updated the diff for D94403: [RISCV] Implement new architecture extension macros.

Correct constant used in macros, 2.0 should be 2000000 not 20000000

Jan 11 2021, 7:33 AM · Restricted Project
simoncook requested review of D94403: [RISCV] Implement new architecture extension macros.
Jan 11 2021, 4:50 AM · Restricted Project

Dec 18 2020

simoncook committed rG698ae90f3062: [RegisterScavenging] Fix assert in scavengeRegisterBackwards (authored by craigblackmore).
[RegisterScavenging] Fix assert in scavengeRegisterBackwards
Dec 18 2020, 8:57 AM
simoncook closed D92104: [RegisterScavenging] Fix assert in scavengeRegisterBackwards.
Dec 18 2020, 8:57 AM · Restricted Project

Nov 23 2020

simoncook added a comment to D91717: [RISCV][compiler-rt] Add support for save-restore.

It seems a bit excessive to me to coalesce the entry points into bundles of 4. Do you have any particular benchmarking data or reasoning that supports choosing that threshold?
Also, shouldn't this implementation include CFI directives?

I used bundles of 4 just to follow the behaviour I saw in libgcc, and the grouping of 2 for rv64 seemed a bit too fine-grained. I'm not sure what the original justification for the coalescing into groups of 2/4 was in libgcc.

I'll update to account for other suggested changes and see if I can find any benchmarks which show the tradeoff for the grouping threshold

Nov 23 2020, 6:44 AM · Restricted Project

Oct 1 2020

simoncook added a comment to D80367: [RISCV][MC] Print absolute targets of branch instructions.

Thanks for reviewing. I'll rebase and add this shortly.

Oct 1 2020, 9:54 AM · Restricted Project

Aug 20 2020

simoncook updated the diff for D62732: [RISCV] Add SystemV ABI.

Rebase

Aug 20 2020, 2:21 AM · Restricted Project

Aug 4 2020

simoncook added a comment to D62732: [RISCV] Add SystemV ABI.

Thanks for looking at this @luismarques We had planned to put more effort into this patch, but time got in the way for quite a lot, but I'm glad it's working; thanks for the rebase I'll update this to match shortly. And it's good that it looks like it's mostly working. I'm curious about your backtrace showing one frame, is that something without debug information, since the example I was using when writing this did show a backtrace back to main? It would be good to understand why that disn't produce the expected output.

Aug 4 2020, 9:42 AM · Restricted Project

Jul 16 2020

simoncook added a comment to D80802: [RISCV] Upgrade RVV MC to v0.9..

The modification is put in D81213.

Jul 16 2020, 11:33 AM · Restricted Project, Restricted Project
simoncook added a comment to D80802: [RISCV] Upgrade RVV MC to v0.9..

Since this patch replaces 0.8 support with 0.9, it should include an update to the version check in clang/lib/Driver/ToolChains/Arch/RISCV.cpp to match.

Jul 16 2020, 4:30 AM · Restricted Project, Restricted Project

Jul 15 2020

simoncook added a comment to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

It's a shame this just missed the creation of the llvm 11.0 branch, do we think it's worth trying to get this backported since it only just missed?

Jul 15 2020, 9:26 AM · Restricted Project
simoncook committed rGde7bf722c23a: [RISCV] Add error checking for extensions missing separating underscores (authored by simoncook).
[RISCV] Add error checking for extensions missing separating underscores
Jul 15 2020, 1:25 AM
simoncook closed D83819: [RISCV] Add error checking for extensions missing separating underscores.
Jul 15 2020, 1:25 AM · Restricted Project
simoncook added a comment to D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions.

I'm not familiar with the vector extension, but given the title of the patch, I have an integration question: It looks like this is enabled by use of the vector target feature, but the name 'Zvlsseg' suggests it's something optional/extra. If the intent to have this enabled unconditionally with 'v', or does it make sense to add features like what was done for bitmanip, where each 'Zb*' part can be enabled/disabled indepenently?

Jul 15 2020, 12:56 AM · Restricted Project

Jul 14 2020

Herald added a project to D83819: [RISCV] Add error checking for extensions missing separating underscores: Restricted Project.
Jul 14 2020, 2:55 PM · Restricted Project

Jun 18 2020

simoncook added a comment to D81946: [WIP][RISCV] Enable multilib support even without a detected GCC install.

Thanks for this Ed. I've tried building a toolchain with it and noticed a couple of things:

Jun 18 2020, 2:41 AM · Restricted Project

May 21 2020

simoncook added a comment to D80367: [RISCV][MC] Print absolute targets of branch instructions.

Why does RISC-V need PrintRequiresAddr?

May 21 2020, 9:41 AM · Restricted Project
simoncook created D80367: [RISCV][MC] Print absolute targets of branch instructions.
May 21 2020, 1:04 AM · Restricted Project

Apr 30 2020

simoncook added a comment to D78702: [RFC][RISCV][MC/Objdump] Extend llvm-objdump output to support more instruction patterns.

Simon can you please rebase, it seems D78776 got merged and now conflicts. Thank you.

Apr 30 2020, 3:01 AM · Restricted Project

Apr 23 2020

simoncook created D78702: [RFC][RISCV][MC/Objdump] Extend llvm-objdump output to support more instruction patterns.
Apr 23 2020, 4:49 AM · Restricted Project

Apr 21 2020

simoncook added a reviewer for D69987: [RISCV] Assemble/Disassemble v-ext instructions.: simoncook.

This is looking good, overall the patch is nicely laid out which has made it easy to compare against the spec.

Apr 21 2020, 2:39 AM · Restricted Project, Restricted Project

Apr 14 2020

simoncook added inline comments to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..
Apr 14 2020, 10:10 AM · Restricted Project

Apr 13 2020

simoncook added inline comments to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..
Apr 13 2020, 8:01 AM · Restricted Project
simoncook added a comment to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Looking at the structure this is looking good, it's probably worth renaming the codegen tests to match what I did with the MC patch before commiting ('Z'->'z') but other than a few formatting changes, this seems good. I haven't yet read through all the patterns, I'll add more comments as I go through it.

Apr 13 2020, 3:44 AM · Restricted Project

Apr 10 2020

simoncook committed rG562bc307c03d: [Driver] Improve help message for -ffixed-xX flags (authored by simoncook).
[Driver] Improve help message for -ffixed-xX flags
Apr 10 2020, 3:44 AM

Apr 9 2020

simoncook committed rG61ff29637501: [RISCV] Add Clang frontend support for Bitmanip extension (authored by s.egerton).
[RISCV] Add Clang frontend support for Bitmanip extension
Apr 9 2020, 1:14 PM
simoncook closed D71553: [RISCV] Add Clang frontend support for Bitmanip extension.
Apr 9 2020, 1:14 PM · Restricted Project
simoncook committed rGdd1ee6dc076f: [RISCV] Support experimental/unratified extensions (authored by simoncook).
[RISCV] Support experimental/unratified extensions
Apr 9 2020, 1:13 PM
simoncook closed D73891: [RISCV] Support experimental/unratified extensions.
Apr 9 2020, 1:13 PM · Restricted Project
simoncook committed rGfae40bd5a1d4: [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0. (authored by PaoloS).
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.
Apr 9 2020, 1:13 PM
simoncook closed D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
Apr 9 2020, 1:13 PM · Restricted Project
simoncook committed rG2df6a02fd75f: [RISCV] Implement evaluateBranch (authored by simoncook).
[RISCV] Implement evaluateBranch
Apr 9 2020, 7:35 AM
simoncook closed D77567: [RISCV] Implement evaluateBranch.
Apr 9 2020, 7:35 AM · Restricted Project
simoncook added a comment to D76767: [RISCV] Support negative constants in CompressInstEmitter.

To clarify, we were not missing in compressed instructions before, this change is for the future compressed instructions to be added, confirmed? Otherwise I need to check why we missed it with the fuzzer.

Apr 9 2020, 2:08 AM · Restricted Project
simoncook added a comment to D77567: [RISCV] Implement evaluateBranch.

Thanks, Simon for pushing this patch, it does help when debugging code and removes the dependence on binutils.

In the future patch for other instructionsm are you including lui/addi combo and addi with gp?

Apr 9 2020, 2:08 AM · Restricted Project

Apr 7 2020

simoncook updated the summary of D77567: [RISCV] Implement evaluateBranch.
Apr 7 2020, 2:40 AM · Restricted Project

Apr 6 2020

simoncook updated the diff for D77567: [RISCV] Implement evaluateBranch.

Resolve issue found by clang-tidy

Apr 6 2020, 10:51 AM · Restricted Project
simoncook created D77567: [RISCV] Implement evaluateBranch.
Apr 6 2020, 9:44 AM · Restricted Project

Apr 1 2020

simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Rebase on updated MC patch

Apr 1 2020, 9:00 AM · Restricted Project

Mar 26 2020

simoncook committed rG1e303962232d: [RISCV] Support negative constants in CompressInstEmitter (authored by simoncook).
[RISCV] Support negative constants in CompressInstEmitter
Mar 26 2020, 8:39 AM
simoncook closed D76767: [RISCV] Support negative constants in CompressInstEmitter.
Mar 26 2020, 8:39 AM · Restricted Project
simoncook added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
In D65649#1943742, @asb wrote:

I'm reviewing this with an eye to merging it, but one big thing that comes to mind is the compressed instructions. The draft bitmanip spec describes these under "Future compressed instructions" and says "It presumably would make sense for a future revision of the “C” extension to include compressed opcodes for those instructions." My reading is that this is more of a sketch of potential encodings and a less firm proposal than the 32-bit encodings described elsewhere in the spec. Do you disagree with that assessment?

Mar 26 2020, 8:38 AM · Restricted Project
simoncook updated the summary of D76767: [RISCV] Support negative constants in CompressInstEmitter.
Mar 26 2020, 7:00 AM · Restricted Project
simoncook updated the diff for D76767: [RISCV] Support negative constants in CompressInstEmitter.

Actually solve the underlying problem.

Mar 26 2020, 7:00 AM · Restricted Project

Mar 25 2020

simoncook added a comment to D76767: [RISCV] Support negative constants in CompressInstEmitter.

Context for this patch: it's needed for CompressPats for bitmanip - since one of the compressed instructions should match against -1

Mar 25 2020, 5:23 AM · Restricted Project
simoncook created D76767: [RISCV] Support negative constants in CompressInstEmitter.
Mar 25 2020, 5:22 AM · Restricted Project

Mar 19 2020

simoncook added inline comments to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..
Mar 19 2020, 4:49 AM · Restricted Project
simoncook added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

This is starting to look good. I've checked all the encodings, and other than c.zext.w having the wrong value all the encodings are right.

Mar 19 2020, 4:49 AM · Restricted Project

Mar 18 2020

simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

Address own feedback on RISCV.td and cpp files

Mar 18 2020, 1:04 AM · Restricted Project

Mar 17 2020

simoncook updated the diff for D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

Address feedback

Mar 17 2020, 12:57 PM · Restricted Project
simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

Address review comments and clang-format changes

Mar 17 2020, 12:56 PM · Restricted Project
simoncook updated the diff for D71553: [RISCV] Add Clang frontend support for Bitmanip extension.

Rebase on new dependencies

Mar 17 2020, 7:57 AM · Restricted Project
simoncook updated the diff for D73891: [RISCV] Support experimental/unratified extensions.
  • Update to match latest dependencies
  • Handle adding "experimental-" to SubtargetFeatures for experimental features
Mar 17 2020, 7:57 AM · Restricted Project
simoncook updated the diff for D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

Rebase on updated D65649

Mar 17 2020, 7:57 AM · Restricted Project
simoncook updated the diff for D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.
  • Update patch now AssemblerPredicate update has landed
  • Add "experimental-" to all bitmanip SubtargetFeatures
Mar 17 2020, 7:57 AM · Restricted Project

Mar 13 2020

simoncook added inline comments to D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.
Mar 13 2020, 4:13 PM · Restricted Project
simoncook accepted D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Patch makes sense, and looking at the newly generated XRegisterBank.inc files, all LGTM

Mar 13 2020, 3:40 PM · Restricted Project
simoncook committed rGa26bd4ec1652: [TableGen] Support combining AssemblerPredicates with ORs (authored by simoncook).
[TableGen] Support combining AssemblerPredicates with ORs
Mar 13 2020, 10:45 AM
simoncook closed D74338: [TableGen] Support combining AssemblerPredicates with ORs.
Mar 13 2020, 10:45 AM · Restricted Project
simoncook retitled D74338: [TableGen] Support combining AssemblerPredicates with ORs from [RFC][TableGen] Support combining AssemblerPredicates with ORs to [TableGen] Support combining AssemblerPredicates with ORs.
Mar 13 2020, 8:33 AM · Restricted Project
simoncook added a comment to D74338: [TableGen] Support combining AssemblerPredicates with ORs.

It'd be nice if a single predicate wouldn't need all_of, but I don't feel strongly about it.

Mar 13 2020, 5:46 AM · Restricted Project

Feb 28 2020

simoncook committed rGca950a6bb197: [RISCV] Compress instructions based on function features (authored by simoncook).
[RISCV] Compress instructions based on function features
Feb 28 2020, 4:13 AM
simoncook closed D73339: [RISCV] Compress instructions based on function features.
Feb 28 2020, 4:13 AM · Restricted Project
simoncook added inline comments to D73339: [RISCV] Compress instructions based on function features.
Feb 28 2020, 2:08 AM · Restricted Project

Feb 27 2020

simoncook added reviewers for D74338: [TableGen] Support combining AssemblerPredicates with ORs: ostannard, nhaehnle.
Feb 27 2020, 8:53 AM · Restricted Project

Feb 24 2020

simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Following feedback from @nhaehnle (http://lists.llvm.org/pipermail/llvm-dev/2020-February/139186.html) I have re-designed this to look more TableGen like (i.e. using DAGs instead of strings to describe the predicate). I have declared two operators any_of and all_of which I think read better than and and or in these cases when just looking at the target files.

Feb 24 2020, 3:24 AM · Restricted Project

Feb 13 2020

simoncook added a comment to D74338: [TableGen] Support combining AssemblerPredicates with ORs.

It's a logical addition to the semantics of features. Though at the moment RV is probably the only user of this addition, the eventual patch implementing it should not include the RV specific changes, which would be better in a separate patch.

Feb 13 2020, 1:11 PM · Restricted Project
simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Add test for RISCV Instruction Compression, so now all uses of AssemblerCondString are covered by this patch.

Feb 13 2020, 9:47 AM · Restricted Project
simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Add AsmWriter test

Feb 13 2020, 7:56 AM · Restricted Project
simoncook updated the diff for D74338: [TableGen] Support combining AssemblerPredicates with ORs.

Incorporate feedback, add test of disassembler and assembly matching test (asmwriter test is WIP)

Feb 13 2020, 5:50 AM · Restricted Project
simoncook updated the diff for D73339: [RISCV] Compress instructions based on function features.

Add floating point test, combine compress tests into single test file.

Feb 13 2020, 4:15 AM · Restricted Project