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lewis-revill (Lewis Revill)
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User Since
Jul 31 2018, 10:55 AM (204 w, 1 d)

Recent Activity

May 25 2022

lewis-revill committed rG29a5a7c6d47a: [RISCV] Add pre-emit pass to make more instructions compressible (authored by lewis-revill).
[RISCV] Add pre-emit pass to make more instructions compressible
May 25 2022, 1:27 AM · Restricted Project, Restricted Project
lewis-revill closed D92105: [RISCV] Add pre-emit pass to make more instructions compressible.
May 25 2022, 1:27 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D92105: [RISCV] Add pre-emit pass to make more instructions compressible.

Rebased prior to commit

May 25 2022, 12:58 AM · Restricted Project, Restricted Project

Apr 28 2022

lewis-revill added a comment to D92105: [RISCV] Add pre-emit pass to make more instructions compressible.

Drive by review. I'm mostly using this as an exercise to get familiar with the code and the target, so please don't consider any of my comments blocking.

Apr 28 2022, 5:48 AM · Restricted Project, Restricted Project

Apr 25 2022

lewis-revill updated the diff for D92105: [RISCV] Add pre-emit pass to make more instructions compressible.

Rebased including an update from using isShiftedUIntN to the templated replacement isShiftedUInt<N, S>. Addressed the issue of inserting incorrect instructions to copy FP registers to compressible FP registers by using FSGNJ_S and FSGNJ_D instead. We note that we can't have an additional offset to adjust the resulting register by if it is an FP register.

Apr 25 2022, 5:17 AM · Restricted Project, Restricted Project
lewis-revill commandeered D92105: [RISCV] Add pre-emit pass to make more instructions compressible.
Apr 25 2022, 5:13 AM · Restricted Project, Restricted Project

Apr 7 2022

Herald added a project to D76445: [RISCV][GlobalISel] Select ALU GPR instructions: Restricted Project.
Apr 7 2022, 5:32 AM · Restricted Project, Restricted Project

Mar 29 2022

lewis-revill added inline comments to D76354: [RISCV][GlobalISel] Legalize types for ALU operations.
Mar 29 2022, 9:10 AM · Restricted Project, Restricted Project
lewis-revill added a comment to D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Register banks do not have sizes. A register bank mapping is a bank plus a size/offset that you can change based on the target's size, not part of the bank itself.

Right. But before this patch there was a max size associated to the bank itself, which is queried by the verifier. And if we want to keep that concept of a maximum size surely we should have it be accurate? So for different hardware modes it should be possible for it to be different.

Why is there a maximum size concept? What is it used for? I haven't noticed thisb efore

Mar 29 2022, 9:08 AM · Restricted Project, Restricted Project
lewis-revill added a comment to D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Register banks do not have sizes. A register bank mapping is a bank plus a size/offset that you can change based on the target's size, not part of the bank itself.

Right. But before this patch there was a max size associated to the bank itself, which is queried by the verifier. And if we want to keep that concept of a maximum size surely we should have it be accurate? So for different hardware modes it should be possible for it to be different.

Why is there a maximum size concept? What is it used for? I haven't noticed thisb efore

If it is a maximum, why can't you set to the maximum possible size?

Mar 29 2022, 9:04 AM · Restricted Project, Restricted Project

Mar 16 2022

lewis-revill added inline comments to D76354: [RISCV][GlobalISel] Legalize types for ALU operations.
Mar 16 2022, 10:06 AM · Restricted Project, Restricted Project

Mar 15 2022

lewis-revill added inline comments to D76354: [RISCV][GlobalISel] Legalize types for ALU operations.
Mar 15 2022, 3:59 AM · Restricted Project, Restricted Project

Mar 14 2022

Herald added a project to D76354: [RISCV][GlobalISel] Legalize types for ALU operations: Restricted Project.
Mar 14 2022, 9:03 AM · Restricted Project, Restricted Project

Feb 16 2022

lewis-revill added inline comments to D76354: [RISCV][GlobalISel] Legalize types for ALU operations.
Feb 16 2022, 5:54 AM · Restricted Project, Restricted Project

Feb 15 2022

lewis-revill added a comment to D118766: [CodeGen] Use the non-pointer LLT equivalent to check regclass type.

Can you add a verifier test for this?

The bridging between LLT and MVT is increasingly painful, we should probably start putting in the effort to move more infrastructure to directly using LLT

Feb 15 2022, 2:23 AM · Restricted Project

Feb 10 2022

lewis-revill added a comment to D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Register banks do not have sizes. A register bank mapping is a bank plus a size/offset that you can change based on the target's size, not part of the bank itself.

Feb 10 2022, 3:20 AM · Restricted Project, Restricted Project

Feb 9 2022

lewis-revill retitled D117318: [RISCV][GlobalISel] Add lowerReturn for calling conv from [WIP][RISCV][GlobalISel] Add lowerReturn for calling conv to [RISCV][GlobalISel] Add lowerReturn for calling conv.
Feb 9 2022, 3:14 AM · Restricted Project
lewis-revill retitled D76445: [RISCV][GlobalISel] Select ALU GPR instructions from [WIP][RISCV][GlobalISel] Select ALU GPR instructions to [RISCV][GlobalISel] Select ALU GPR instructions.
Feb 9 2022, 3:14 AM · Restricted Project, Restricted Project
lewis-revill retitled D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions from [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions to [RISCV][GlobalISel] Select register banks for GPR ALU instructions.
Feb 9 2022, 3:14 AM · Restricted Project
lewis-revill retitled D76354: [RISCV][GlobalISel] Legalize types for ALU operations from [WIP][RISCV][GlobalISel] Legalize types for ALU operations to [RISCV][GlobalISel] Legalize types for ALU operations.
Feb 9 2022, 3:14 AM · Restricted Project, Restricted Project
lewis-revill retitled D75023: [RISCV][GlobalISel] Add lowerCall for calling convention from [WIP][RISCV][GlobalISel] Add lowerCall for calling convention to [RISCV][GlobalISel] Add lowerCall for calling convention.
Feb 9 2022, 3:13 AM · Restricted Project
lewis-revill retitled D74977: [RISCV][GlobalISel] Add lowerFormalArguments for calling convention from [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention to [RISCV][GlobalISel] Add lowerFormalArguments for calling convention.
Feb 9 2022, 3:12 AM · Restricted Project
lewis-revill added a comment to D118766: [CodeGen] Use the non-pointer LLT equivalent to check regclass type.

Bump - is anyone able to review this?

Feb 9 2022, 3:10 AM · Restricted Project
lewis-revill added a comment to D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Bump - is anyone able to review this?

Feb 9 2022, 3:10 AM · Restricted Project, Restricted Project
lewis-revill retitled D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes from [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes to [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.
Feb 9 2022, 3:09 AM · Restricted Project, Restricted Project

Feb 2 2022

lewis-revill abandoned D118233: [MachineVerifier] Report allocatable classes for physical register copies.

Abandoned in favour of D118766

Feb 2 2022, 2:40 AM · Restricted Project
lewis-revill requested review of D118766: [CodeGen] Use the non-pointer LLT equivalent to check regclass type.
Feb 2 2022, 2:39 AM · Restricted Project
lewis-revill added inline comments to D118233: [MachineVerifier] Report allocatable classes for physical register copies.
Feb 2 2022, 2:26 AM · Restricted Project

Feb 1 2022

lewis-revill added inline comments to D118233: [MachineVerifier] Report allocatable classes for physical register copies.
Feb 1 2022, 8:25 AM · Restricted Project
lewis-revill added a comment to D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

I'm not sure I understand why the RegisterBankInfo needs to be aware of the hwmode. HWmode changes the size of the classes during selection, but the registerbankinfo just needs to assign sizes to banks. The concrete classes don't matter so much

Feb 1 2022, 8:00 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Restructure slightly, add more cases for selectCopy along with tests, add selection patterns for RV64 W instructions.

Feb 1 2022, 7:23 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Remove unnecessary loop checking legality

Feb 1 2022, 7:18 AM · Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Address review comments; primarily avoid selecting directly until the instruction selector.

Feb 1 2022, 7:13 AM · Restricted Project, Restricted Project
lewis-revill requested review of D118702: [GlobalISel] Allow handling G_MUL with libcalls in LegalizerHelper.
Feb 1 2022, 7:11 AM · Restricted Project

Jan 26 2022

lewis-revill updated the diff for D75023: [RISCV][GlobalISel] Add lowerCall for calling convention.

Use ValueAssigners to avoid rewriting generic infrastructure and use determineAndHandleAssignments instead.

Jan 26 2022, 4:23 AM · Restricted Project
lewis-revill updated the diff for D74977: [RISCV][GlobalISel] Add lowerFormalArguments for calling convention.

Introduce an IncomingValueAssigner to allow us to call determineAndHandleAssignments.

Jan 26 2022, 4:01 AM · Restricted Project
lewis-revill updated the diff for D117318: [RISCV][GlobalISel] Add lowerReturn for calling conv.

Don't reinvent existing generic functions; instead introduce an OutgoingValueAssigner to allow us to call determineAndHandleAssignments.

Jan 26 2022, 3:54 AM · Restricted Project
lewis-revill requested review of D118233: [MachineVerifier] Report allocatable classes for physical register copies.
Jan 26 2022, 3:50 AM · Restricted Project

Jan 14 2022

lewis-revill abandoned D75683: [NFC][RISCV][GlobalISel] Move test file into irtranslator subdirectory.
Jan 14 2022, 8:23 AM · Restricted Project
lewis-revill planned changes to D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Still need to address testing permutations of copying virtual/physical registers.

Jan 14 2022, 7:52 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Rebased. Added the first GIComplexPatternEquiv definition in order to handle the operands to shifts, which are now covered by a ComplexPattern in SelectionDAG. Updated the tests to match the output of the regbank selector.

Jan 14 2022, 7:49 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Rebased. Updated tests to match the output of the legalizer.

Jan 14 2022, 7:43 AM · Restricted Project
lewis-revill updated the diff for D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Rebased.

Jan 14 2022, 7:40 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Rebased.

Jan 14 2022, 7:38 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D75023: [RISCV][GlobalISel] Add lowerCall for calling convention.

Rebased, and updated where appropriate to continue to build correctly.

Jan 14 2022, 7:36 AM · Restricted Project
lewis-revill updated the diff for D74977: [RISCV][GlobalISel] Add lowerFormalArguments for calling convention.

Rebased, and updated where appropriate to continue to build correctly.

Jan 14 2022, 7:29 AM · Restricted Project
lewis-revill requested review of D117318: [RISCV][GlobalISel] Add lowerReturn for calling conv.
Jan 14 2022, 7:26 AM · Restricted Project

Nov 23 2020

lewis-revill added a comment to D91931: [RISCV][GlobalISel] Select add i32, i32.

There's already a series of patches to add more GlobalISel support for RISCV. For example, https://reviews.llvm.org/D76445. The others can be found in the stack of patches attached to that one.

I noticed that these patches have been silent for several months, how can I promote this?

Nov 23 2020, 1:39 AM · Restricted Project

Aug 21 2020

lewis-revill committed rG9e6c09c0d995: [RISCV] Fix inaccurate annotations on PseudoBRIND (authored by lewis-revill).
[RISCV] Fix inaccurate annotations on PseudoBRIND
Aug 21 2020, 3:39 AM
lewis-revill closed D86286: [RISCV] Fix inaccurate annotations on PseudoBRIND.
Aug 21 2020, 3:39 AM · Restricted Project

Aug 20 2020

lewis-revill requested review of D86286: [RISCV] Fix inaccurate annotations on PseudoBRIND.
Aug 20 2020, 6:34 AM · Restricted Project

Jul 15 2020

lewis-revill committed rGc9c955ada8e6: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm…
Jul 15 2020, 4:21 AM
lewis-revill committed rGd4be33374c07: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm…
Jul 15 2020, 4:20 AM
lewis-revill committed rG6144f0a1e52e: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm…
Jul 15 2020, 4:20 AM
lewis-revill committed rG31b52b4345e3: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm…
Jul 15 2020, 4:20 AM
lewis-revill closed D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill committed rGe2692f0ee7f3: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm…
Jul 15 2020, 4:20 AM
lewis-revill closed D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill closed D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill closed D79871: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill closed D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill added a comment to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

Sure I'll land these apologies for the delay..

Jul 15 2020, 3:40 AM · Restricted Project

Jul 14 2020

lewis-revill accepted D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions.

See nitpick, otherwise LGTM

Jul 14 2020, 8:11 AM · Restricted Project
lewis-revill accepted D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions.

LGTM

Jul 14 2020, 8:10 AM · Restricted Project
lewis-revill accepted D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.

See nitpicks, otherwise LGTM

Jul 14 2020, 8:10 AM · Restricted Project
lewis-revill accepted D79871: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions.

LGTM

Jul 14 2020, 8:09 AM · Restricted Project
lewis-revill accepted D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

Thanks Paolo, tests are all passing and apart from the nitpicks this is a green light from me, as with the rest in this series.

Jul 14 2020, 8:09 AM · Restricted Project
lewis-revill added inline comments to D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions.
Jul 14 2020, 8:05 AM · Restricted Project
lewis-revill added inline comments to D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.
Jul 14 2020, 8:04 AM · Restricted Project
lewis-revill added inline comments to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.
Jul 14 2020, 8:04 AM · Restricted Project

Jul 9 2020

lewis-revill added inline comments to D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions.
Jul 9 2020, 7:46 AM · Restricted Project
lewis-revill added inline comments to D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.
Jul 9 2020, 7:39 AM · Restricted Project
lewis-revill added inline comments to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.
Jul 9 2020, 6:51 AM · Restricted Project

Jun 28 2020

lewis-revill added a comment to D77443: [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos.

Bumping this patch - Looking at the output of the riscv-expand-pseudos pass I'd say these values are accurate. I'd say comments here, and in the functions which expand the instructions to ensure things don't get changed - seems to me like tests would be a little tricky so perhaps omitting that would be fine just to get this landed.

Jun 28 2020, 1:59 PM · Restricted Project

Apr 18 2020

lewis-revill updated the diff for D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Bug fix - ensure selectConstant produces copies with fully constrained registers.

Apr 18 2020, 12:22 PM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Bug fix - don't try to access the size of a $noreg register.

Apr 18 2020, 3:45 AM · Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Add target flags to calls in tests.

Apr 18 2020, 3:45 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D75023: [RISCV][GlobalISel] Add lowerCall for calling convention.

Bug fix - add target flags to call instruction.

Apr 18 2020, 3:45 AM · Restricted Project

Apr 17 2020

lewis-revill updated the diff for D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Add custom selection for copies and for constants. Significantly expand tests over more types.

Apr 17 2020, 2:40 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Add more operand mappings and expand tests over more types.

Apr 17 2020, 2:40 AM · Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Tweak test order

Apr 17 2020, 2:40 AM · Restricted Project, Restricted Project

Apr 16 2020

lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Add testing for shifts. Include a version of handling single word operations on RV64 involving directly lowering to the final opcode.

Apr 16 2020, 11:41 AM · Restricted Project, Restricted Project
lewis-revill added inline comments to D76354: [RISCV][GlobalISel] Legalize types for ALU operations.
Apr 16 2020, 9:27 AM · Restricted Project, Restricted Project

Apr 13 2020

lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Expand patch to include operations for other types as introduced by the legalizer.

Apr 13 2020, 3:44 AM · Restricted Project

Apr 12 2020

lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Expand patch to correctly cover more methods of types being legalized - IE: single word instructions on RV64, split operations (add with carry etc.) and libcalls up to s128.

Apr 12 2020, 12:16 PM · Restricted Project, Restricted Project

Apr 10 2020

lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Use utils/update_mir_test_checks.py

Apr 10 2020, 2:40 AM · Restricted Project
lewis-revill updated the diff for D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Use utils/update_mir_test_checks.py

Apr 10 2020, 2:40 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Use utils/update_mir_test_checks.py

Apr 10 2020, 2:40 AM · Restricted Project, Restricted Project
lewis-revill added inline comments to D76354: [RISCV][GlobalISel] Legalize types for ALU operations.
Apr 10 2020, 1:35 AM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Removed unnecessary line

Apr 10 2020, 1:35 AM · Restricted Project, Restricted Project

Apr 7 2020

lewis-revill updated the diff for D76445: [RISCV][GlobalISel] Select ALU GPR instructions.

Add tests for AND/OR/XOR.

Apr 7 2020, 12:31 PM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76354: [RISCV][GlobalISel] Legalize types for ALU operations.

Support AND/OR/XOR.

Apr 7 2020, 12:31 PM · Restricted Project, Restricted Project
lewis-revill updated the diff for D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Support AND/OR/XOR.

Apr 7 2020, 12:31 PM · Restricted Project
lewis-revill updated the diff for D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Rebased.

Apr 7 2020, 12:31 PM · Restricted Project, Restricted Project

Apr 1 2020

lewis-revill updated the diff for D74977: [RISCV][GlobalISel] Add lowerFormalArguments for calling convention.
Apr 1 2020, 3:18 AM · Restricted Project

Mar 30 2020

lewis-revill updated the diff for D74977: [RISCV][GlobalISel] Add lowerFormalArguments for calling convention.

Address comments relating to supported types.

Mar 30 2020, 5:55 AM · Restricted Project

Mar 29 2020

lewis-revill updated the diff for D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Rewrote the global RegBanks array to be constant. Instead of modifying RegisterBanks after construction, provide HwMode to the constructor of RegisterBankInfo and move size calculation logic for RegisterBanks to that class.

Mar 29 2020, 1:55 PM · Restricted Project, Restricted Project

Mar 26 2020

lewis-revill added a reviewer for D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes: bkramer.
Mar 26 2020, 11:59 AM · Restricted Project, Restricted Project
lewis-revill added a comment to D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

I'm lacking an understanding of how concurrency is expected to work within LLVM, but since there is only one RegisterBankInfo constructed per subtarget I don't see how there is a problem with updating the global RegBanks array? Likewise the HwMode is constant for the subtarget, so the write will be of the same value.

Mar 26 2020, 11:59 AM · Restricted Project, Restricted Project

Mar 23 2020

lewis-revill reopened D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.
Mar 23 2020, 9:48 AM · Restricted Project, Restricted Project