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lewis-revill (Lewis Revill)
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User Since
Jul 31 2018, 10:55 AM (112 w, 2 d)

Recent Activity

Aug 21 2020

lewis-revill committed rG9e6c09c0d995: [RISCV] Fix inaccurate annotations on PseudoBRIND (authored by lewis-revill).
[RISCV] Fix inaccurate annotations on PseudoBRIND
Aug 21 2020, 3:39 AM
lewis-revill closed D86286: [RISCV] Fix inaccurate annotations on PseudoBRIND.
Aug 21 2020, 3:39 AM · Restricted Project

Aug 20 2020

lewis-revill requested review of D86286: [RISCV] Fix inaccurate annotations on PseudoBRIND.
Aug 20 2020, 6:34 AM · Restricted Project

Jul 15 2020

lewis-revill committed rGc9c955ada8e6: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm…
Jul 15 2020, 4:21 AM
lewis-revill committed rGd4be33374c07: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm…
Jul 15 2020, 4:20 AM
lewis-revill committed rG6144f0a1e52e: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm…
Jul 15 2020, 4:20 AM
lewis-revill committed rG31b52b4345e3: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm…
Jul 15 2020, 4:20 AM
lewis-revill closed D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill committed rGe2692f0ee7f3: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm… (authored by lewis-revill).
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm…
Jul 15 2020, 4:20 AM
lewis-revill closed D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill closed D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill closed D79871: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill closed D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.
Jul 15 2020, 4:20 AM · Restricted Project
lewis-revill added a comment to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

Sure I'll land these apologies for the delay..

Jul 15 2020, 3:40 AM · Restricted Project

Jul 14 2020

lewis-revill accepted D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions.

See nitpick, otherwise LGTM

Jul 14 2020, 8:11 AM · Restricted Project
lewis-revill accepted D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions.

LGTM

Jul 14 2020, 8:10 AM · Restricted Project
lewis-revill accepted D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.

See nitpicks, otherwise LGTM

Jul 14 2020, 8:10 AM · Restricted Project
lewis-revill accepted D79871: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions.

LGTM

Jul 14 2020, 8:09 AM · Restricted Project
lewis-revill accepted D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.

Thanks Paolo, tests are all passing and apart from the nitpicks this is a green light from me, as with the rest in this series.

Jul 14 2020, 8:09 AM · Restricted Project
lewis-revill added inline comments to D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions.
Jul 14 2020, 8:05 AM · Restricted Project
lewis-revill added inline comments to D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.
Jul 14 2020, 8:04 AM · Restricted Project
lewis-revill added inline comments to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.
Jul 14 2020, 8:04 AM · Restricted Project

Jul 9 2020

lewis-revill added inline comments to D79874: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions.
Jul 9 2020, 7:46 AM · Restricted Project
lewis-revill added inline comments to D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions.
Jul 9 2020, 7:39 AM · Restricted Project
lewis-revill added inline comments to D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions.
Jul 9 2020, 6:51 AM · Restricted Project

Jun 28 2020

lewis-revill added a comment to D77443: [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos.

Bumping this patch - Looking at the output of the riscv-expand-pseudos pass I'd say these values are accurate. I'd say comments here, and in the functions which expand the instructions to ensure things don't get changed - seems to me like tests would be a little tricky so perhaps omitting that would be fine just to get this landed.

Jun 28 2020, 1:59 PM · Restricted Project

Apr 18 2020

lewis-revill updated the diff for D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions.

Bug fix - ensure selectConstant produces copies with fully constrained registers.

Apr 18 2020, 12:22 PM · Restricted Project
lewis-revill updated the diff for D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Bug fix - don't try to access the size of a $noreg register.

Apr 18 2020, 3:45 AM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Add target flags to calls in tests.

Apr 18 2020, 3:45 AM · Restricted Project
lewis-revill updated the diff for D75023: [WIP][RISCV][GlobalISel] Add lowerCall for calling convention.

Bug fix - add target flags to call instruction.

Apr 18 2020, 3:45 AM · Restricted Project

Apr 17 2020

lewis-revill updated the diff for D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions.

Add custom selection for copies and for constants. Significantly expand tests over more types.

Apr 17 2020, 2:40 AM · Restricted Project
lewis-revill updated the diff for D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Add more operand mappings and expand tests over more types.

Apr 17 2020, 2:40 AM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Tweak test order

Apr 17 2020, 2:40 AM · Restricted Project

Apr 16 2020

lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Add testing for shifts. Include a version of handling single word operations on RV64 involving directly lowering to the final opcode.

Apr 16 2020, 11:41 AM · Restricted Project
lewis-revill added inline comments to D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.
Apr 16 2020, 9:27 AM · Restricted Project

Apr 13 2020

lewis-revill updated the diff for D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Expand patch to include operations for other types as introduced by the legalizer.

Apr 13 2020, 3:44 AM · Restricted Project

Apr 12 2020

lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Expand patch to correctly cover more methods of types being legalized - IE: single word instructions on RV64, split operations (add with carry etc.) and libcalls up to s128.

Apr 12 2020, 12:16 PM · Restricted Project

Apr 10 2020

lewis-revill updated the diff for D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Use utils/update_mir_test_checks.py

Apr 10 2020, 2:40 AM · Restricted Project
lewis-revill updated the diff for D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions.

Use utils/update_mir_test_checks.py

Apr 10 2020, 2:40 AM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Use utils/update_mir_test_checks.py

Apr 10 2020, 2:40 AM · Restricted Project
lewis-revill added inline comments to D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.
Apr 10 2020, 1:35 AM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Removed unnecessary line

Apr 10 2020, 1:35 AM · Restricted Project

Apr 7 2020

lewis-revill updated the diff for D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions.

Add tests for AND/OR/XOR.

Apr 7 2020, 12:31 PM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Support AND/OR/XOR.

Apr 7 2020, 12:31 PM · Restricted Project
lewis-revill updated the diff for D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Support AND/OR/XOR.

Apr 7 2020, 12:31 PM · Restricted Project
lewis-revill updated the diff for D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Rebased.

Apr 7 2020, 12:31 PM · Restricted Project

Apr 1 2020

lewis-revill updated the diff for D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention.
Apr 1 2020, 3:18 AM · Restricted Project

Mar 30 2020

lewis-revill updated the diff for D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention.

Address comments relating to supported types.

Mar 30 2020, 5:55 AM · Restricted Project

Mar 29 2020

lewis-revill updated the diff for D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

Rewrote the global RegBanks array to be constant. Instead of modifying RegisterBanks after construction, provide HwMode to the constructor of RegisterBankInfo and move size calculation logic for RegisterBanks to that class.

Mar 29 2020, 1:55 PM · Restricted Project

Mar 26 2020

lewis-revill added a reviewer for D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes: bkramer.
Mar 26 2020, 11:59 AM · Restricted Project
lewis-revill added a comment to D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

I'm lacking an understanding of how concurrency is expected to work within LLVM, but since there is only one RegisterBankInfo constructed per subtarget I don't see how there is a problem with updating the global RegBanks array? Likewise the HwMode is constant for the subtarget, so the write will be of the same value.

Mar 26 2020, 11:59 AM · Restricted Project

Mar 23 2020

lewis-revill reopened D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.
Mar 23 2020, 9:48 AM · Restricted Project
lewis-revill added a comment to D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

My initial thoughts are that this may only be an issue if there can be potentially more than one instance of RegisterBankInfo? And indeed, if it is possible for each of these to have been constructed with differing HwModes? I'll try and look into it in more detail and find out.

Mar 23 2020, 9:48 AM · Restricted Project

Mar 19 2020

lewis-revill created D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions.
Mar 19 2020, 12:32 PM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Add XLenLLT, take into account M extension.

Mar 19 2020, 12:32 PM · Restricted Project

Mar 18 2020

lewis-revill abandoned D61907: [RISCV] Leave pcrel_hi/pcrel_lo fixup pairs unresolved.
Mar 18 2020, 1:35 PM · Restricted Project
lewis-revill committed rGe9f22fd4293a: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes (authored by lewis-revill).
[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
Mar 18 2020, 1:03 PM
lewis-revill committed rGe225e770f7e9: [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness. (authored by lewis-revill).
[TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.
Mar 18 2020, 1:03 PM
lewis-revill closed D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.
Mar 18 2020, 1:02 PM · Restricted Project
lewis-revill closed D76006: [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.
Mar 18 2020, 1:02 PM · Restricted Project
lewis-revill updated the diff for D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.

Address comments

Mar 18 2020, 10:20 AM · Restricted Project
lewis-revill added a reviewer for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations: Joe.
Mar 18 2020, 10:20 AM · Restricted Project
lewis-revill added a reviewer for D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention: Joe.
Mar 18 2020, 10:20 AM · Restricted Project
lewis-revill added a reviewer for D75023: [WIP][RISCV][GlobalISel] Add lowerCall for calling convention: Joe.
Mar 18 2020, 10:20 AM · Restricted Project
lewis-revill updated the diff for D75023: [WIP][RISCV][GlobalISel] Add lowerCall for calling convention.

Add test for pointer return type

Mar 18 2020, 10:20 AM · Restricted Project
lewis-revill retitled D75683: [NFC][RISCV][GlobalISel] Move test file into irtranslator subdirectory from [RISCV][GlobalISel] Move test file into irtranslator subdirectory to [NFC][RISCV][GlobalISel] Move test file into irtranslator subdirectory.
Mar 18 2020, 10:20 AM · Restricted Project
lewis-revill updated the diff for D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.

Fix copy/paste mistakes in check lines

Mar 18 2020, 4:51 AM · Restricted Project
lewis-revill created D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations.
Mar 18 2020, 4:51 AM · Restricted Project
lewis-revill added a comment to D67348: [RISCV] Add codegen pattern matching for bit manipulation assembly instructions..

All looks good apart from some test nitpicks. Also add more reviewers

Mar 18 2020, 3:13 AM · Restricted Project
lewis-revill added a comment to D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension.

This looks good to me, as long as it covers the spec. Can you add more reviewers though?

Mar 18 2020, 2:41 AM · Restricted Project
lewis-revill accepted D73891: [RISCV] Support experimental/unratified extensions.

Thanks, this is looking in good shape now. As long as everyone agrees on this scheme I think the implementation is good to go (pending the bitmanip extension support).

Mar 18 2020, 2:41 AM · Restricted Project

Mar 12 2020

lewis-revill added a reviewer for D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes: arsenm.
Mar 12 2020, 3:03 AM · Restricted Project
lewis-revill created D76051: [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.
Mar 12 2020, 3:03 AM · Restricted Project

Mar 11 2020

lewis-revill updated the diff for D76006: [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.

Clang format

Mar 11 2020, 11:19 AM · Restricted Project
lewis-revill created D76007: [WIP][TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.
Mar 11 2020, 10:45 AM · Restricted Project
lewis-revill created D76006: [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.
Mar 11 2020, 10:13 AM · Restricted Project

Mar 5 2020

lewis-revill updated the diff for D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention.

Rebase, update test structure.

Mar 5 2020, 8:13 AM · Restricted Project
lewis-revill updated the diff for D75023: [WIP][RISCV][GlobalISel] Add lowerCall for calling convention.

Rebase, update test structure. Correct missing defs by adding CallReturnHandler.

Mar 5 2020, 8:13 AM · Restricted Project
lewis-revill created D75683: [NFC][RISCV][GlobalISel] Move test file into irtranslator subdirectory.
Mar 5 2020, 8:13 AM · Restricted Project

Feb 23 2020

lewis-revill created D75023: [WIP][RISCV][GlobalISel] Add lowerCall for calling convention.
Feb 23 2020, 11:13 AM · Restricted Project
lewis-revill updated the diff for D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention.
Feb 23 2020, 11:09 AM · Restricted Project

Feb 22 2020

lewis-revill updated the diff for D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention.
Feb 22 2020, 2:53 AM · Restricted Project

Feb 21 2020

lewis-revill created D74977: [WIP][RISCV][GlobalISel] Add lowerFormalArguments for calling convention.
Feb 21 2020, 11:36 AM · Restricted Project

Feb 12 2020

lewis-revill added a comment to D74338: [TableGen] Support combining AssemblerPredicates with ORs.

I can't see any issues with the logic of this implementation. It doesn't lend itself well to adapting it in the future if we want to be able to combine the operators, but I'd expect that would require a more disruptive rewrite so I'm not too concerned about that right now. See comments though.

Feb 12 2020, 6:40 AM · Restricted Project

Feb 11 2020

lewis-revill committed rGa6bd1256ce8a: [DebugInfo] Call site entries cannot be generated for FrameSetup calls (authored by lewis-revill).
[DebugInfo] Call site entries cannot be generated for FrameSetup calls
Feb 11 2020, 1:28 PM
lewis-revill committed rG07f7c00208b3: [RISCV] Add support for save/restore of callee-saved registers via libcalls (authored by lewis-revill).
[RISCV] Add support for save/restore of callee-saved registers via libcalls
Feb 11 2020, 1:28 PM
lewis-revill closed D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.
Feb 11 2020, 1:28 PM · debug-info, Restricted Project
lewis-revill closed D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.
Feb 11 2020, 1:27 PM · Restricted Project, Restricted Project
lewis-revill added a comment to D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.

Since the DebugInfo fix has been accepted, I'm looking to get this patch and that fix committed shortly if there are no problems caused by rebasing.

Feb 11 2020, 3:34 AM · Restricted Project, Restricted Project

Feb 8 2020

lewis-revill added inline comments to D73891: [RISCV] Support experimental/unratified extensions.
Feb 8 2020, 4:50 AM · Restricted Project

Feb 5 2020

lewis-revill updated the diff for D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.

Updated comment and added brief testcase, which now depends on D62686

Feb 5 2020, 12:10 PM · debug-info, Restricted Project
lewis-revill updated the diff for D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.

Rebased

Feb 5 2020, 12:10 PM · Restricted Project, Restricted Project

Feb 4 2020

lewis-revill added a comment to D71593: [DebugInfo] Call site entries cannot be generated for FrameSetup calls.

Thanks all for the feedback, I'll make this patch depend upon the save/restore feature so that I can add a testcase.

Feb 4 2020, 7:45 AM · debug-info, Restricted Project
lewis-revill added a comment to D71774: [RISCV] Optimize seteq/setne pattern expansions for better code size.

This seems like a fun issue:

  • addi is compressible
  • xor is almost certainly easier to analyse (from the view of KnownBits and the like).

Have you seen any regressions in code generation from this change?

Feb 4 2020, 5:01 AM · Restricted Project
lewis-revill added a comment to D69808: [RISCV GlobalISel] Add lowerReturn for calling conv..

Thanks for addressing the comments, I'd like some input from others before saying this looks good.

Feb 4 2020, 5:01 AM · Restricted Project
lewis-revill added a comment to D71774: [RISCV] Optimize seteq/setne pattern expansions for better code size.

Well spotted, this seems like a good change to me. I wonder if there are other optimization opportunities to use this NegImm/simm12_plus1 pattern in further patches?

Feb 4 2020, 4:52 AM · Restricted Project
lewis-revill added a comment to D73699: [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization.

Thanks, this seems like a good change. I haven't checked the source, but I wonder is it ever possible this hook triggers duplication of the returns but the tail calls don't get emitted for whatever reason? Other than that and the comment above I'd be happy with this.

Feb 4 2020, 4:43 AM · Restricted Project

Jan 15 2020

lewis-revill added a comment to D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls.

Lewis, your latest patch looks good, we just had another run with no new failures. But we know it will have issues with -g. So I think we should not merge it yet. Do you have a version of the patch that creates the labels for the compiler-generated save/restore lib calls, so that this optimization does not depend on D71593? We could merge that version then, and when D71593 is accepted, you just have to rework/remove the label generation part of the patch.

Jan 15 2020, 1:05 AM · Restricted Project, Restricted Project

Jan 14 2020

lewis-revill committed rGcd800f3b226b: [RISCV] Allow shrink wrapping for RISC-V (authored by lewis-revill).
[RISCV] Allow shrink wrapping for RISC-V
Jan 14 2020, 11:03 AM
lewis-revill closed D62190: [RISCV] Allow shrink wrapping for RISC-V.
Jan 14 2020, 11:03 AM · Restricted Project