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[WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions
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Authored by lewis-revill on Mar 12 2020, 2:23 AM.

Details

Summary

This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions, and the associated operations introduced by the legalizer.

Diff Detail

Event Timeline

lewis-revill created this revision.Mar 12 2020, 2:23 AM
simoncook added inline comments.Mar 13 2020, 4:02 PM
llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
15

This looks strange this way round, does this still build if you swap lines 14 and 15?

98

reigsters -> registers, nitpick: RV32

lewis-revill retitled this revision from [RISCV][GlobalISel] Select register banks for GPR ALU instructions to [WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions.
lewis-revill added a reviewer: Joe.

Address comments

Support AND/OR/XOR.

Use utils/update_mir_test_checks.py

lewis-revill edited the summary of this revision. (Show Details)

Expand patch to include operations for other types as introduced by the legalizer.

Add more operand mappings and expand tests over more types.

Bug fix - don't try to access the size of a $noreg register.

lenary resigned from this revision.Thu, Jan 14, 10:10 AM
rkruppe removed a subscriber: rkruppe.Thu, Jan 14, 10:20 AM