[RISCV][GlobalISel] Select register banks for GPR ALU instructions

[lewis-revill]

Summary

This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions, and the associated operations introduced by the legalizer.

[simoncook]

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp

15

This looks strange this way round, does this still build if you swap lines 14 and 15?

98

reigsters -> registers, nitpick: RV32

[lewis-revill]

Address comments

[lewis-revill]

Support AND/OR/XOR.

[lewis-revill]

Use utils/update_mir_test_checks.py

[lewis-revill]

Expand patch to include operations for other types as introduced by the legalizer.

[lewis-revill]

Add more operand mappings and expand tests over more types.

[lewis-revill]

Bug fix - don't try to access the size of a $noreg register.

[lewis-revill]

Rebased. Updated tests to match the output of the legalizer.

[arsenm]

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp

95

I'd recommend keeping the subtarget cached in the class

99

I don't see the point of this loop. It seems like you're just doing a rough legality check, but the function is already required (and enforced by the verifier) to be legal at this point

102

You shouldn't see noreg on a generic instruction so I'm not sure what you're addressing here

llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu32.mir

8

You can drop the IR section

[lewis-revill]

Remove unnecessary loop checking legality