[WIP][RISCV][GlobalISel] Select register banks for GPR ALU instructions

[lewis-revill]

Summary

This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions, and the associated operations introduced by the legalizer.

[simoncook]

llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp

15

This looks strange this way round, does this still build if you swap lines 14 and 15?

98

reigsters -> registers, nitpick: RV32

[lewis-revill]

Address comments

[lewis-revill]

Support AND/OR/XOR.

[lewis-revill]

Use utils/update_mir_test_checks.py

[lewis-revill]

Expand patch to include operations for other types as introduced by the legalizer.

[lewis-revill]

Add more operand mappings and expand tests over more types.

[lewis-revill]

Bug fix - don't try to access the size of a $noreg register.