Support the global instruction selection of add i32, i32.
This patch is minimal support. And this patch referenced ARM and AArch64's GlobalISel implementation.
I use the tablegen to generate the CCAssignFn. And the generated function just support the current requirement of
select add i32, i32. The reason for using the generated function is the globalisel infrastructure handleAssignments function
needs the CCAssignFn as one of the parameters. However, The RISCV backend handwriting the CC_RISCV function to deal
with calling conventions. But this function was not matched the CCAssignFn format. So I have to use the tablegen to generate the CCAssignFn.
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llvm/lib/Target/RISCV/RISCVCallingConv.td | ||
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66–79 | RISC-V calling conventions are implemented in C++ and that was a deliberate choice. Please do not duplicate what is already there (which is a huge nuisance for downstream forks like ours) and instead reuse the perfectly-good well-tested CC_RISCV that already exists. Also TableGen calling conventions are far too opaque to have any hope of actually convincing yourself they're correct in all the subtle edge-cases, whereas imperative code is clear and unambiguous. |
There's already a series of patches to add more GlobalISel support for RISCV. For example, https://reviews.llvm.org/D76445. The others can be found in the stack of patches attached to that one.
I noticed that these patches have been silent for several months, how can I promote this?
I've not been able to work on those patches for some time but if someone might commandeer them to rebase them and work on top of them I think that would be a good starting point and I would happily take a look at the changes. Otherwise I may get some time to update them myself within a month or two.
Thank you. I am very willing to work based on your patches. And I will start to do recently!
clang-format: please reformat the code