Some instruction selection patterns required for ALU GPR instructions have already been automatically imported from existing TableGen descriptions - this patch simply adds testing for them. Logic for selecting constants and copies has been added, along with the first of the GIComplexPatternEquiv definitions required to select the shiftMaskXLen ComplexPattern. New patterns have been added to directly select RV64 W instructions from gMIR rather than using custom gMIR operations earlier in the pipeline. In future this could also support the checks present in the DAGToDAGISel for finding ops whose users only require the lower 32 bits.
Diff Detail
Diff Detail
- Repository
- rG LLVM Github Monorepo
| Time | Test | |
|---|---|---|
| 5,560 ms | LLVM.CodeGen/RISCV/GlobalISel/instruction-select::Unknown Unit Message (" ") Script:
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: 'RUN: at line 1'; /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/llc -march=riscv32 -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir | /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/FileCheck -check-prefix=RV32I /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir
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| 5,400 ms | LLVM.CodeGen/RISCV/GlobalISel/instruction-select::Unknown Unit Message (" ") Script:
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: 'RUN: at line 1'; /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/llc -march=riscv32 -mattr=+m -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir | /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/FileCheck -check-prefix=RV32I /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir
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| 5,520 ms | LLVM.CodeGen/RISCV/GlobalISel/instruction-select::Unknown Unit Message (" ") Script:
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: 'RUN: at line 1'; /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/llc -march=riscv64 -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir | /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/FileCheck -check-prefix=RV64I /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir
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| 5,470 ms | LLVM.CodeGen/RISCV/GlobalISel/instruction-select::Unknown Unit Message (" ") Script:
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: 'RUN: at line 1'; /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/llc -march=riscv64 -mattr=+m -x mir -run-pass=instruction-select -simplify-mir -verify-machineinstrs < /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir | /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/build/bin/FileCheck -check-prefix=RV64I /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir
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Event Timeline
Comment Actions
Add custom selection for copies and for constants. Significantly expand tests over more types.
Comment Actions
Missing copy tests for all permutations of virtual and physical registers
| llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp | ||
|---|---|---|
| 114–115 ↗ | (On Diff #258538) | This can't early return, it still needs to constrain a virtual source |
Comment Actions
Rebased. Added the first GIComplexPatternEquiv definition in order to handle the operands to shifts, which are now covered by a ComplexPattern in SelectionDAG. Updated the tests to match the output of the regbank selector.
| llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp | ||
|---|---|---|
| 97–108 ↗ | (On Diff #400005) | This function name is misleading. Can you restructure to use something more like getRegClassForTypeOnBank (which AArch64 has a FIXME to make a generic TargetRegisterInfo method) |
Comment Actions
Restructure slightly, add more cases for selectCopy along with tests, add selection patterns for RV64 W instructions.
| llvm/lib/Target/RISCV/RISCVGISel.td | ||
|---|---|---|
| 30 ↗ | (On Diff #404931) | Should sext_inreg be legal? |
| llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp | ||
| 46 ↗ | (On Diff #404931) | What is this parameter? |
| 109 ↗ | (On Diff #404931) | SrcReg.isPhysical() |
| 120 ↗ | (On Diff #404931) | Why not just print the whole instruction? |
| 145 ↗ | (On Diff #404931) | Should not construct one off MachineIRBuilders. The selector usually just directly uses BuildMI |
| 171 ↗ | (On Diff #404931) | Didn't erase the instruction |
| llvm/lib/Target/RISCV/RISCVGISel.td | ||
|---|---|---|
| 30 ↗ | (On Diff #404931) | This is what I'm stuck on right now. It really should to match the SelectionDAG code, at least for i32 -> i64. However there is no way to map G_SEXT_INREG to sext_inreg because sext_inreg uses a value type as a DAG operand, whereas G_SEXT_INREG uses a constant which indicates the size of the original type. So no patterns defined which use sext_inreg will work for GlobalISel. I think my only option left is to do custom selection code. |
| llvm/lib/Target/RISCV/RISCVGISel.td | ||
|---|---|---|
| 30 ↗ | (On Diff #404931) | You can either do custom selection code, or you could add support for sext_inreg in GlobalISelEmitter. It's a special case so it requires special support |