Backend for NEC SX-Aurora

[simoll]

Summary

This patch registers the 've' target: the NEC SX-Aurora TSUBASA Vector Engine.

This follows up on the announcement on llvm-dev: https://lists.llvm.org/pipermail/llvm-dev/2019-April/131580.html
We have a poster & lightning talk at the upcoming DevMtg: http://llvm.org/devmtg/2019-10/talk-abstracts.html#lit6

• Public documentation (architecture, encodings, instructions)
  • ISA manual: https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf
  • Up-to-date documentation on architecture and tools: https://www.hpc.nec/documents/

• Reference implementation
  • github: https://github.com/sx-aurora-dev/llvm-project
  • Status: full scalar instruction support, clang toolchain integration, vector support through intrinsics.

• Testing
  • Reference implementation is tested continuously at NEC.
  • We are planning to setup a buildslave reporting to LLVM buildmaster.

• Code owner of the VE target
  • Simon Moll

A rough roadmap:

1. Registers, encodings, scalar instructions, clang tooling, ..
2. Vector instruction support through target-specific intrinsics.
3. Support for LLVM-VP as it becomes available in LLVM upstream.

[bcain]

Shouldn't the first patch add to LLVM_TARGETS_TO_BUILD or LLVM_EXPERIMENTAL_TARGETS_TO_BUILD?

llvm/test/CodeGen/VE/target_support.ll

1

not not can't be right, can it? Just run llc directly.

[simoll]

In D69103#1714433, @bcain wrote:

Shouldn't the first patch add to LLVM_TARGETS_TO_BUILD or LLVM_EXPERIMENTAL_TARGETS_TO_BUILD?

This patch adds VE as an experimental target, which is not build by default. If users want VE support, they add it to LLVM_EXPERIMENTAL_TARGETS_TO_BUILD when they configure the build.

llvm/test/CodeGen/VE/target_support.ll

1

The 'not not' makes sure the test does not crash when 'llc' crashes (which is anticipated in a successful run). We need this because if the tests succeeds, the 'llc' call crashes trying to create initialize VE codegen. The test fails when 'llc' reports that 've' is not a valid target.

[asl]

llvm/test/CodeGen/VE/target_support.ll

1

Can't you just check the output of llc --version then? Expecting llc to crash is quite ugly...

[simoll]

Thanks for your feedback! Fixes in this update:

• Using llc --version in the target test.
• comment cleanup.

[rengolin]

This plan has all the requirements for adding a new target (http://llvm.org/docs/DeveloperPolicy.html#new-targets), mainly: ISA document, current implementation, code owner, buildbots. You just need to make sure it's marked as *experimental*, as stated in the policy.

The Github repo mentioned (branch develop) is a bit hard to make out what are the changes necessary, as it has only merges from other branches. Given that we'll have to judge what the next series of patches will be, and that you'll have to upstream them in order, it would be good if they were more or less organised in the way they will be upstreamed in the source. This will also help you rebase changes that are requested in the reviews, which weren't originally in your repo, and test them before continuing the upstreaming process.

Other than that, it would be nice if other code owners could review and approve.

[arsenm]

Could use some unit tests in TripleTest

llvm/lib/Target/LLVMBuild.txt

39

Targets usually start out as experimental targets, not added to the default build list (although IMO this is more trouble than it's worth in practice)

llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h

17–19

Unnecessary includes? Although I guess this is just a stub

[craig.topper]

llvm/lib/Support/Triple.cpp

1474

It looks like this list was supposed to be alphabetized, but then renderscript32/64 was added out of order? Should we just put this back in order?

1566

Same here

[simoll]

In D69103#1722713, @arsenm wrote:

Could use some unit tests in TripleTest

Ok. Skimming through the tests there, it seems one parser test for a ve-X-Y triple should be enough, right?

llvm/lib/Support/Triple.cpp

1474

I guess the order of backend names is not a critical issue. I'd bring the target lists back into alphabetical order in a quick follow-up after this patch.

llvm/lib/Target/LLVMBuild.txt

39

It is my understanding that a target is experimental, if it is not added by default to LLVM_TARGETS_TO_BUILD (it is not in LLVM_ALL_TARGETS of `llvm/CMakeLists.txt).

If this line is removed the cmake configure step crashes when the target is added to LLVM_EXPERIMENTAL_TARGETS_TO_BUILD.

llvm-build: error: invalid target to enable: 'VE' (not in project)

llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h

17–19

Yep. You are looking at a close-to-minimal slice of the current backend source on github. Should i strip these includes? (to add them later?)

[simoll]

Thanks for your comments!

Added the suggested TripleTest.

[simoll]

In D69103#1722659, @rengolin wrote:

This plan has all the requirements for adding a new target (http://llvm.org/docs/DeveloperPolicy.html#new-targets), mainly: ISA document, current implementation, code owner, buildbots. You just need to make sure it's marked as *experimental*, as stated in the policy.

Great! How do we mark the target to make it clear it's experimental?

The Github repo mentioned (branch develop) is a bit hard to make out what are the changes necessary, as it has only merges from other branches. Given that we'll have to judge what the next series of patches will be, and that you'll have to upstream them in order, it would be good if they were more or less organised in the way they will be upstreamed in the source. This will also help you rebase changes that are requested in the reviews, which weren't originally in your repo, and test them before continuing the upstreaming process.

That's a good point. We probably won't stick to the existing commits but repackage the github code into a linear sequence of testable patches for review. We will go for instruction encodings, register decl and scalar codegen first, then extend to vector intrinsics and finally to LLVM-VP.

How much of that do you need to see before this patch here can be approved? I am asking because as we are refactoring the out-of-tree patches for upstreaming, it'd ease the pain of rebasing if some of the changes outside of lib/Target/VE could already go in. Beyond this patch, the critical changes are:

• TableGen:
  • IntrinsicEmitter (Additional IIT_Info enum entries).
  • CodeGenTarget (MVT enum entries).
• Clang: VE toolchain.

Later, we will add target-specific vector intrinsics to Clang and LLVM.

Other than that, it would be nice if other code owners could review and approve.

Thanks! :)

[rengolin]

In D69103#1723824, @simoll wrote:

Great! How do we mark the target to make it clear it's experimental?

There used to be different registers in CMake and some structs, I can't remember. There are some comments in here that may help, but ultimately, you want to make sure that your target is only built if explicitly named, so we don't break bots.

How much of that do you need to see before this patch here can be approved? I am asking because as we are refactoring the out-of-tree patches for upstreaming, it'd ease the pain of rebasing if some of the changes outside of lib/Target/VE could already go in.

Ideally you'd like to at least show the next steps (in the order you named). This could be a tentative Phab review, or a branch on your Github repo that shows it, but it would have to end up in Phab in a way that can be merged pretty soon.

What we're trying to avoid here is to have a long period (potentially across releases) with just the stub in and no real code. The current patch is just a marker and it would be good to see you're on the right path early on, so make any strong refactory before starting the patch set.

Beyond this patch, the critical changes are:

• TableGen:
  • IntrinsicEmitter (Additional IIT_Info enum entries).
  • CodeGenTarget (MVT enum entries).
• Clang: VE toolchain.

Later, we will add target-specific vector intrinsics to Clang and LLVM.

I'm also interested in how you're going to connect to the rest of the toolchain. Are you emitting direct binaries (are they ELF-like?) or assembly that gets lowered by a proprietary tool (like NVidia)?

Also, what is the subset of IR that can work in your target (if any) and will Clang be responsible for filtering it or do we barf in the middle-end?

I'm expecting the loop vectoriser to be of interest, because if all we have is intrinsics, than it's easier to write assembly directly. :)

--renato

[simoll]

In D69103#1723851, @rengolin wrote:

In D69103#1723824, @simoll wrote:

Great! How do we mark the target to make it clear it's experimental?

There used to be different registers in CMake and some structs, I can't remember. There are some comments in here that may help, but ultimately, you want to make sure that your target is only built if explicitly named, so we don't break bots.

Okay. I'll double check cmake only configures the build with the target when its explicitly added to LLVM_EXPERIMENTAl_TARGETS_TO_BUILD. Some pointers to the structs in question would be very helpful.

How much of that do you need to see before this patch here can be approved? I am asking because as we are refactoring the out-of-tree patches for upstreaming, it'd ease the pain of rebasing if some of the changes outside of lib/Target/VE could already go in.

Ideally you'd like to at least show the next steps (in the order you named). This could be a tentative Phab review, or a branch on your Github repo that shows it, but it would have to end up in Phab in a way that can be merged pretty soon.

What we're trying to avoid here is to have a long period (potentially across releases) with just the stub in and no real code. The current patch is just a marker and it would be good to see you're on the right path early on, so make any strong refactory before starting the patch set.

I understand. We will repackage the github code into digestible commits and put them on phab. I'll get back to you when the patch sets leading up to full scalar codegen are ready.

Beyond this patch, the critical changes are:

• TableGen:
  • IntrinsicEmitter (Additional IIT_Info enum entries).
  • CodeGenTarget (MVT enum entries).
• Clang: VE toolchain.

Later, we will add target-specific vector intrinsics to Clang and LLVM.

I'm also interested in how you're going to connect to the rest of the toolchain. Are you emitting direct binaries (are they ELF-like?) or assembly that gets lowered by a proprietary tool (like NVidia)?

Also, what is the subset of IR that can work in your target (if any) and will Clang be responsible for filtering it or do we barf in the middle-end?

Any code that would run on your CPU really :) The full application binary (ELF, btw) runs on the card by default and dispatches systemcalls to a proxy process on the host. The github code already implements full scalar instruction codegen (and there are VE implementations for libcxx/libcxxabi/libunwind, ..).

I'm expecting the loop vectoriser to be of interest, because if all we have is intrinsics, than it's easier to write assembly directly. :)

Well, we already use the target-specific intrinsics for hand-written Tensorflow kernels. However, we are planning to implement standard vector instructions and LLVM-VP once its available upstream. The Region Vectorizer is already capable of emitting VP intrinsics. The current loop vectorizer would need to be extended to support tail loop predication through setting the active vector length to be useful for the VE (Otw, eg for packed f32 mode, there would be up to 511 scalarized remainder iterations, ..).

[rengolin]

In D69103#1724045, @simoll wrote:

I understand. We will repackage the github code into digestible commits and put them on phab. I'll get back to you when the patch sets leading up to full scalar codegen are ready.

Thanks!

Any code that would run on your CPU really :) The full application binary (ELF, btw) runs on the card by default and dispatches systemcalls to a proxy process on the host. The github code already implements full scalar instruction codegen (and there are VE implementations for libcxx/libcxxabi/libunwind, ..).

Awesome! Hopefully the callbacks into CPU are rare enough in optimised code that it doesn't get to be a bottleneck.

Well, we already use the target-specific intrinsics for hand-written Tensorflow kernels. However, we are planning to implement standard vector instructions and LLVM-VP once its available upstream. The Region Vectorizer is already capable of emitting VP intrinsics. The current loop vectorizer would need to be extended to support tail loop predication through setting the active vector length to be useful for the VE (Otw, eg for packed f32 mode, there would be up to 511 scalarized remainder iterations, ..).

Interesting. I'm guessing VPlan would be a must-have to get decent performance in this target.

[simoll]

• removed vector types from DataLayout

[simoll]

We've sliced up the backend into 5 different patches. The first three patches leave you with functional scalar code generation for the VE target:

1. VE,#0 64bit data for SjLj - is a preparatory patch for exception handling.
2. VE,#1 Scalar code generation - full scalar code generation.
3. VE,#2 Clang toolchain for SX-Aurora - makes the VE target available in Clang.
4. VE,#3 Runtime libraries - basic adaptations of the libcxx, libcxxabi,libunwind, compiler-rt, openmp runtime libraries.
5. VE,#4 Target vector intrinsics - Target-specific vector intrinsics.

I am currently preparing a patch to register our staging buildbot.
As announced on llvm-dev there are some more patches for the test-suite in the pipe to set it up for the VE target.

[arsenm]

llvm/include/llvm/ADT/Triple.h

481

Stray change?

[simoll]

llvm/include/llvm/ADT/Triple.h

481

Not sure what you mean, there is no change in this line?

[simoll]

The buildbot is setup. This is the llvm-zorg patch to add it.

[simoll]

The child patches show the next steps and attach a staging buildbot for the VE target as requested.
Please let us know how to proceed from here.

[arsenm]

LGTM

llvm/lib/Target/VE/VETargetMachine.cpp

31

I think just having a single string would be better unless you're planning on adding checks to control these, but it's not important

[simoll]

Thanks for the review. This patch has been simmering for a while. I'll wait until Thursday to commit this to allow others to chime in.

llvm/lib/Target/VE/VETargetMachine.cpp

31

We will add vector type alignments in the forthcoming patches. With the DL string spread out over multiple lines those appear more cleanly in the diff.

[simoll]

Rebased

[fhahn]

I think this breaks http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/425/steps/build%20stage%201/logs/stdio

[RKSimon]

In D69103#1811693, @fhahn wrote:

I think this breaks http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/425/steps/build%20stage%201/logs/stdio

I just got burnt by this so pushed a fix: rG0d5407987a36

[simoll]

In D69103#1811701, @RKSimon wrote:

In D69103#1811693, @fhahn wrote:

I think this breaks http://lab.llvm.org:8011/builders/clang-ppc64le-rhel/builds/425/steps/build%20stage%201/logs/stdio

I just got burnt by this so pushed a fix: rG0d5407987a36

Thanks! Sorry for the collateral damage.

llvm/CODE_OWNERS.TXT

 N: David Majnemer
 E: [e-mail]
 D: IR Constant Folder, InstCombine
 
 N: Dylan McKay
 E: [e-mail]
 D: AVR Backend
 
+N: Simon Moll
+E: [e-mail]
+D: VE Backend
+
 N: Tim Northover
 E: [e-mail]
 D: AArch64 backend, misc ARM backend
 
 N: Diego Novillo
 E: [e-mail]
 D: SampleProfile and related parts of ProfileData
 

llvm/include/llvm/ADT/Triple.h

enum ArchType {
     spir64,         // SPIR: standard portable IR for OpenCL 64-bit version
     kalimba,        // Kalimba: generic kalimba
     shave,          // SHAVE: Movidius vector VLIW processors
     lanai,          // Lanai: Lanai 32-bit
     wasm32,         // WebAssembly with 32-bit pointers
     wasm64,         // WebAssembly with 64-bit pointers
     renderscript32, // 32-bit RenderScript
     renderscript64, // 64-bit RenderScript
-    LastArchType = renderscript64
+    ve,             // NEC SX-Aurora Vector Engine
+    LastArchType = ve
   };
   enum SubArchType {
     NoSubArch,
 
     ARMSubArch_v8_5a,
     ARMSubArch_v8_4a,
     ARMSubArch_v8_3a,
     ARMSubArch_v8_2a,
public:
   bool isWatchOS() const {
     return getOS() == Triple::WatchOS;
   }
 
   bool isWatchABI() const {
     return getSubArch() == Triple::ARMSubArch_v7k;
   }
 
   /// isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
   bool isOSDarwin() const {
     return isMacOSX() || isiOS() || isWatchOS();
   }
 
   bool isSimulatorEnvironment() const {
     return getEnvironment() == Triple::Simulator;
   }
 
bool isPPC64() const {
     return getArch() == Triple::ppc64 || getArch() == Triple::ppc64le;
   }
 
   /// Tests whether the target is RISC-V (32- and 64-bit).
   bool isRISCV() const {
     return getArch() == Triple::riscv32 || getArch() == Triple::riscv64;
   }
 
+  /// Tests whether the target is VE
+  bool isVE() const {
+    return getArch() == Triple::ve;
+  }
+
   /// Tests whether the target supports comdat
   bool supportsCOMDAT() const {
     return !isOSBinFormatMachO();
   }
 
   /// Tests whether the target uses emulated TLS as default.
   bool hasDefaultEmulatedTLS() const {
     return isAndroid() || isOSOpenBSD() || isWindowsCygwinEnvironment();

llvm/lib/Support/Triple.cpp

StringRef Triple::getArchTypeName(ArchType Kind) {
   case spir64:         return "spir64";
   case kalimba:        return "kalimba";
   case lanai:          return "lanai";
   case shave:          return "shave";
   case wasm32:         return "wasm32";
   case wasm64:         return "wasm64";
   case renderscript32: return "renderscript32";
   case renderscript64: return "renderscript64";
+  case ve:             return "ve";
   }
 
   llvm_unreachable("Invalid ArchType!");
 }
 
 StringRef Triple::getArchTypePrefix(ArchType Kind) {
   switch (Kind) {
   default:
StringRef Triple::getArchTypePrefix(ArchType Kind) {
   case kalimba:     return "kalimba";
   case lanai:       return "lanai";
   case shave:       return "shave";
   case wasm32:
   case wasm64:      return "wasm";
 
   case riscv32:
   case riscv64:     return "riscv";
+
+  case ve:          return "ve";
   }
 }
 
 StringRef Triple::getVendorTypeName(VendorType Kind) {
   switch (Kind) {
   case UnknownVendor: return "unknown";
 
   case Apple: return "apple";
return StringSwitch<Triple::ArchType>(Name)
     .Case("spir64", spir64)
     .Case("kalimba", kalimba)
     .Case("lanai", lanai)
     .Case("shave", shave)
     .Case("wasm32", wasm32)
     .Case("wasm64", wasm64)
     .Case("renderscript32", renderscript32)
     .Case("renderscript64", renderscript64)
+    .Case("ve", ve)
     .Default(UnknownArch);
 }
 
 static Triple::ArchType parseARMArch(StringRef ArchName) {
   ARM::ISAKind ISA = ARM::parseArchISA(ArchName);
   ARM::EndianKind ENDIAN = ARM::parseArchEndian(ArchName);
 
   Triple::ArchType arch = Triple::UnknownArch;
auto AT = StringSwitch<Triple::ArchType>(ArchName)
     .Case("spir64", Triple::spir64)
     .StartsWith("kalimba", Triple::kalimba)
     .Case("lanai", Triple::lanai)
     .Case("shave", Triple::shave)
     .Case("wasm32", Triple::wasm32)
     .Case("wasm64", Triple::wasm64)
     .Case("renderscript32", Triple::renderscript32)
     .Case("renderscript64", Triple::renderscript64)
+    .Case("ve", Triple::ve)
     .Default(Triple::UnknownArch);
 
   // Some architectures require special parsing logic just to compute the
   // ArchType result.
   if (AT == Triple::UnknownArch) {
     if (ArchName.startswith("arm") || ArchName.startswith("thumb") ||
         ArchName.startswith("aarch64"))
       return parseARMArch(ArchName);
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::sparcv9:
   case Triple::spir:
   case Triple::spir64:
   case Triple::systemz:
   case Triple::tce:
   case Triple::tcele:
   case Triple::thumbeb:
   case Triple::xcore:
+  case Triple::ve:
     return Triple::ELF;
 
   case Triple::ppc:
   case Triple::ppc64:
     if (T.isOSDarwin())
       return Triple::MachO;
     else if (T.isOSAIX())
       return Triple::XCOFF;
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::sparcv9:
   case llvm::Triple::systemz:
   case llvm::Triple::x86_64:
   case llvm::Triple::amdil64:
   case llvm::Triple::hsail64:
   case llvm::Triple::spir64:
   case llvm::Triple::wasm64:
   case llvm::Triple::renderscript64:
+  case llvm::Triple::ve:
     return 64;
   }
   llvm_unreachable("Invalid architecture value");
 }
 
 bool Triple::isArch64Bit() const {
   return getArchPointerBitWidth(getArch()) == 64;
 }
Triple Triple::get32BitArchVariant() const {
   case Triple::UnknownArch:
   case Triple::amdgcn:
   case Triple::avr:
   case Triple::bpfel:
   case Triple::bpfeb:
   case Triple::msp430:
   case Triple::systemz:
   case Triple::ppc64le:
+  case Triple::ve:
     T.setArch(UnknownArch);
     break;
 
   case Triple::aarch64_32:
   case Triple::amdil:
   case Triple::hsail:
   case Triple::spir:
   case Triple::arc:
Triple Triple::get64BitArchVariant() const {
   case Triple::ppc64:
   case Triple::ppc64le:
   case Triple::riscv64:
   case Triple::sparcv9:
   case Triple::systemz:
   case Triple::x86_64:
   case Triple::wasm64:
   case Triple::renderscript64:
+  case Triple::ve:
     // Already 64-bit.
     break;
 
   case Triple::aarch64_32:      T.setArch(Triple::aarch64);    break;
   case Triple::arm:             T.setArch(Triple::aarch64);    break;
   case Triple::armeb:           T.setArch(Triple::aarch64_be); break;
   case Triple::le32:            T.setArch(Triple::le64);       break;
   case Triple::mips:            T.setArch(Triple::mips64);     break;
Triple Triple::getBigEndianArchVariant() const {
   case Triple::spir:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
   case Triple::xcore:
   case Triple::renderscript32:
   case Triple::renderscript64:
+  case Triple::ve:
 
   // ARM is intentionally unsupported here, changing the architecture would
   // drop any arch suffixes.
   case Triple::arm:
   case Triple::thumb:
     T.setArch(UnknownArch);
     break;
 
bool Triple::isLittleEndian() const {
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
   case Triple::xcore:
   case Triple::tcele:
   case Triple::renderscript32:
   case Triple::renderscript64:
+  case Triple::ve:
     return true;
   default:
     return false;
   }
 }
 
 bool Triple::isCompatibleWith(const Triple &Other) const {
   // ARM and Thumb triples are compatible, if subarch, vendor and OS match.

llvm/lib/Target/LLVMBuild.txt

  Mips
  PowerPC
  RISCV
  Sparc
  SystemZ
  WebAssembly
  X86
  XCore
+ VE
 
 ; This is a special group whose required libraries are extended (by llvm-build)
 ; with the best execution engine (the native JIT, if available, or the
 ; interpreter).
 [component_0]
 type = LibraryGroup
 name = Engine
 parent = Libraries

llvm/lib/Target/VE/CMakeLists.txt

+set(LLVM_TARGET_DEFINITIONS VE.td)
+
+add_llvm_target(VECodeGen
+  VETargetMachine.cpp
+  )
+
+add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)

llvm/lib/Target/VE/LLVMBuild.txt

+;===- ./lib/Target/VE/LLVMBuild.txt ----------------------------*- Conf -*--===;
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[common]
+subdirectories = MCTargetDesc TargetInfo
+
+[component_0]
+type = TargetGroup
+name = VE
+parent = Target
+has_asmparser = 0
+has_asmprinter = 0
+
+[component_1]
+type = Library
+name = VECodeGen
+parent = VE
+required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG 
+                     VEDesc VEInfo Support Target
+add_to_library_groups = VE

llvm/lib/Target/VE/MCTargetDesc/CMakeLists.txt

+add_llvm_library(LLVMVEDesc
+  VEMCTargetDesc.cpp
+  )

llvm/lib/Target/VE/MCTargetDesc/LLVMBuild.txt

+;===- ./lib/Target/VE/MCTargetDesc/LLVMBuild.txt ---------------*- Conf -*--===;
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = VEDesc
+parent = VE
+required_libraries = MC VEInfo Support
+add_to_library_groups = VE

llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h

+//===-- VEMCTargetDesc.h - VE Target Descriptions ---------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides VE specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_VE_MCTARGETDESC_VEMCTARGETDESC_H
+#define LLVM_LIB_TARGET_VE_MCTARGETDESC_VEMCTARGETDESC_H
+
+#include "llvm/Support/DataTypes.h"
+
+#include <memory>
+
+namespace llvm {
+
+class Target;
+Target &getTheVETarget();
+
+} // End llvm namespace
+
+#endif

llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp

+//===-- VEMCTargetDesc.cpp - VE Target Descriptions -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides VE specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#include "VEMCTargetDesc.h"
+
+using namespace llvm;
+
+extern "C" void LLVMInitializeVETargetMC() {
+  // TODO
+}

llvm/lib/Target/VE/TargetInfo/CMakeLists.txt

+add_llvm_library(LLVMVEInfo
+  VETargetInfo.cpp
+  )

llvm/lib/Target/VE/TargetInfo/LLVMBuild.txt

+;===- ./lib/Target/VE/TargetInfo/LLVMBuild.txt -----------------*- Conf -*--===;
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = VEInfo
+parent = VE
+required_libraries = Support
+add_to_library_groups = VE

llvm/lib/Target/VE/TargetInfo/VETargetInfo.cpp

+//===-- VETargetInfo.cpp - VE Target Implementation -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "VE.h"
+#include "llvm/IR/Module.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+Target &llvm::getTheVETarget() {
+  static Target TheVETarget;
+  return TheVETarget;
+}
+
+extern "C" void LLVMInitializeVETargetInfo() {
+  RegisterTarget<Triple::ve, /*HasJIT=*/false> X(getTheVETarget(), "ve",
+                                                 "VE", "VE");
+}

llvm/lib/Target/VE/VE.h

+//===-- VE.h - Top-level interface for VE representation --------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// VE back-end.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_VE_VE_H
+#define LLVM_LIB_TARGET_VE_VE_H
+
+#include "MCTargetDesc/VEMCTargetDesc.h"
+
+#endif

llvm/lib/Target/VE/VETargetMachine.h

+//===-- VETargetMachine.h - Define TargetMachine for VE ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the VE specific subclass of TargetMachine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_VE_VETARGETMACHINE_H
+#define LLVM_LIB_TARGET_VE_VETARGETMACHINE_H
+
+#include "llvm/Target/TargetMachine.h"
+
+namespace llvm {
+
+class VETargetMachine : public LLVMTargetMachine {
+public:
+  VETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
+                  StringRef FS, const TargetOptions &Options,
+                  Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
+                  CodeGenOpt::Level OL, bool JIT);
+  ~VETargetMachine() override;
+};
+
+} // end namespace llvm
+
+#endif

llvm/lib/Target/VE/VETargetMachine.cpp

+//===-- VETargetMachine.cpp - Define TargetMachine for VE -----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+#include "VETargetMachine.h"
+#include "VE.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ve"
+
+extern "C" void LLVMInitializeVETarget() {
+  // Register the target.
+  RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
+}
+
+static std::string computeDataLayout(const Triple &T) {
+  // Aurora VE is little endian
+  std::string Ret = "e";
+
+  // Use ELF mangling
+  Ret += "-m:e";
+
+  // Alignments for 64 bit integers.
+  Ret += "-i64:64";
+
+  // VE supports 32 bit and 64 bits integer on registers
+  Ret += "-n32:64";
+
+  // Stack alignment is 64 bits
+  Ret += "-S64";
+
+  // Vector alignments are 64 bits
+  // Need to define all of them.  Otherwise, each alignment becomes
+  // the size of each data by default.
+  Ret += "-v64:64:64";          // for v2f32
+  Ret += "-v128:64:64";
+  Ret += "-v256:64:64";
+  Ret += "-v512:64:64";
+  Ret += "-v1024:64:64";
+  Ret += "-v2048:64:64";
+  Ret += "-v4096:64:64";
+  Ret += "-v8192:64:64";
+  Ret += "-v16384:64:64";       // for v256f64
+
+  return Ret;
+}
+
+static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
+  if (!RM.hasValue())
+    return Reloc::Static;
+  return *RM;
+}
+
+/// Create an Aurora VE architecture model
+VETargetMachine::VETargetMachine(
+    const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
+    const TargetOptions &Options, Optional<Reloc::Model> RM,
+    Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
+    : LLVMTargetMachine(
+          T, computeDataLayout(TT), TT, CPU, FS, Options,
+          getEffectiveRelocModel(RM),
+          getEffectiveCodeModel(CM, CodeModel::Small),
+          OL)
+{}
+
+VETargetMachine::~VETargetMachine() {}

llvm/test/CodeGen/VE/lit.local.cfg

+if not 'VE' in config.root.targets:
+    config.unsupported = True

llvm/test/CodeGen/VE/target_support.ll

+; RUN: not not llc < %s -asm-verbose=false -march=ve 2>&1 | FileCheck %s --check-prefix=ARCH
+; RUN: not not llc < %s -asm-verbose=false -mtriple=ve 2>&1 | FileCheck %s --check-prefix=TRIPLE
+
+; ARCH-NOT: invalid target
+; TRIPLE-NOT: unable to get target
+
+define i32 @f(i32 %i) {
+  ret i32 %i
+}