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Differential D73540

[VE] fp32/64 fadd/fsub/fdiv/fmul isel patterns
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Authored by simoll on Jan 28 2020, 3:46 AM.

Details

Reviewers
arsenm
craig.topper
rengolin
k-ishizaka
Commits
rGf6bb58542aca: [VE] fp32/64 fadd/fsub/fdiv/fmul isel patterns
Summary

fp32/64 fadd/fsub/fdiv/fmul isel patterns and tests.

Diff Detail

Event Timeline

simoll created this revision.Jan 28 2020, 3:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 28 2020, 3:46 AM
Herald added subscribers: llvm-commits, hiraditya, wdng. · View Herald Transcript
simoll added a parent revision: D71338: [VE,#1] Scalar code generation.Jan 28 2020, 3:48 AM
merge_guards_bot added a subscriber: merge_guards_bot.Jan 28 2020, 4:12 AM

Unit tests: fail. 62254 tests passed, 1 failed and 831 were skipped.

failed: lld.ELF/undef.s

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

Harbormaster failed remote builds in B45112: Diff 240830!Jan 28 2020, 4:14 AM
simoll updated this revision to Diff 241067.Jan 29 2020, 1:36 AM
  • rebased
merge_guards_bot added a comment.Jan 29 2020, 1:59 AM

Unit tests: pass. 62283 tests passed, 0 failed and 831 were skipped.

clang-tidy: pass.

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

Harbormaster completed remote builds in B45213: Diff 241067.Jan 29 2020, 2:03 AM
This revision was not accepted when it landed; it landed in state Needs Review.Jan 29 2020, 2:03 AM
Closed by commit rGf6bb58542aca: [VE] fp32/64 fadd/fsub/fdiv/fmul isel patterns (authored by kaz7, committed by simoll). · Explain Why
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
32 lines
test/
CodeGen/
VE/
63 lines
63 lines
63 lines
63 lines

Diff 241072

llvm/lib/Target/VE/VEInstrInfo.td

Show First 20 Lines • Show All 362 Lines • ▼ Show 20 Linesmulticlass RRNCm<string opcStr, bits<8>opc,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2, RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2,
SDPatternOperator OpNode=null_frag> : SDPatternOperator OpNode=null_frag> :
RRmrr<opcStr, opc, RC, Ty, RC, Ty, OpNode>, RRmrr<opcStr, opc, RC, Ty, RC, Ty, OpNode>,
RRmir<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>, RRmir<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>,
RRmiz<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>, RRmiz<opcStr, opc, RC, Ty, RC, Ty, immOp, OpNode>,
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>, RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>; RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
// Used by fadd, fsub, and similar floating point instructions
// The order of operands are "$sx, $sy, $sz"
multiclass RRFm<string opcStr, bits<8>opc,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2,
SDPatternOperator OpNode=null_frag> :
RRmrr<opcStr, opc, RC, Ty, RC, Ty, OpNode>,
RRmir<opcStr, opc, RC, Ty, RC, Ty, immOp, null_frag>,
RRmiz<opcStr, opc, RC, Ty, RC, Ty, immOp, null_frag>,
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
// Multiclass for RR type instructions // Multiclass for RR type instructions
// Used by sra, sla, sll, and similar instructions // Used by sra, sla, sll, and similar instructions
// The order of operands are "$sx, $sz, $sy" // The order of operands are "$sx, $sz, $sy"
multiclass RRIm<string opcStr, bits<8>opc, multiclass RRIm<string opcStr, bits<8>opc,
RegisterClass RC, ValueType Ty, RegisterClass RC, ValueType Ty,
Operand immOp, Operand immOp2, Operand immOp, Operand immOp2,
SDPatternOperator OpNode=null_frag> { SDPatternOperator OpNode=null_frag> {
▲ Show 20 Lines • Show All 283 Lines • ▼ Show 20 Lines
def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))), def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))),
(EXTRACT_SUBREG (SRLri (ANDrm0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (EXTRACT_SUBREG (SRLri (ANDrm0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
$src, sub_i32), 32), imm:$val), sub_i32)>; $src, sub_i32), 32), imm:$val), sub_i32)>;
def : Pat<(i32 (srl i32:$src, i32:$val)), def : Pat<(i32 (srl i32:$src, i32:$val)),
(EXTRACT_SUBREG (SRLrr (ANDrm0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (EXTRACT_SUBREG (SRLrr (ANDrm0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
$src, sub_i32), 32), $val), sub_i32)>; $src, sub_i32), 32), $val), sub_i32)>;
// 5.3.2.5. Floating-point Arithmetic Operation Instructions // 5.3.2.5. Floating-point Arithmetic Operation Instructions
let cx = 0 in
defm FAD : RRFm<"fadd.d", 0x4C, I64, f64, simm7Op64, uimm6Op64, fadd>;
let cx = 1 in
defm FADS : RRFm<"fadd.s", 0x4C, F32, f32, simm7Op32, uimm6Op32, fadd>;
let cx = 0 in
defm FSB : RRFm<"fsub.d", 0x5C, I64, f64, simm7Op64, uimm6Op64, fsub>;
let cx = 1 in
defm FSBS : RRFm<"fsub.s", 0x5C, F32, f32, simm7Op32, uimm6Op32, fsub>;
let cx = 0 in
defm FMP : RRFm<"fmul.d", 0x4D, I64, f64, simm7Op64, uimm6Op64, fmul>;
let cx = 1 in
defm FMPS : RRFm<"fmul.s", 0x4D, F32, f32, simm7Op32, uimm6Op32, fmul>;
let cx = 0 in
defm FDV : RRFm<"fdiv.d", 0x5D, I64, f64, simm7Op64, uimm6Op64, fdiv>;
let cx = 1 in
defm FDVS : RRFm<"fdiv.s", 0x5D, F32, f32, simm7Op32, uimm6Op32, fdiv>;
// FCP instruction // FCP instruction
let cx = 0 in let cx = 0 in
defm FCP : RRm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>; defm FCP : RRm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>;
let cx = 1 in let cx = 1 in
defm FCPS : RRm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>; defm FCPS : RRm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>;
// FCM // FCM
let cw = 0 in { let cw = 0 in {
▲ Show 20 Lines • Show All 524 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/fp_add.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd double %a, %b
ret double %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd float %a, 5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd double %a, 5.000000e+00
ret double %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd float %a, 0x47EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(%s1)
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd double %a, 0x7FEFFFFFFFFFFFFF
ret double %r
}

llvm/test/CodeGen/VE/fp_div.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv double %a, %b
ret double %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv float %a, 5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv double %a, 5.000000e+00
ret double %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fdiv.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv float %a, 0x47EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(%s1)
; CHECK-NEXT: fdiv.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fdiv double %a, 0x7FEFFFFFFFFFFFFF
ret double %r
}

llvm/test/CodeGen/VE/fp_mul.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fmul float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fmul double %a, %b
ret double %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 1084227584
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fmul float %a, 5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 1075052544
; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fmul double %a, 5.000000e+00
ret double %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 2139095039
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fmul.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fmul float %a, 0x47EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, 2146435071(%s1)
; CHECK-NEXT: fmul.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fmul double %a, 0x7FEFFFFFFFFFFFFF
ret double %r
}

llvm/test/CodeGen/VE/fp_sub.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define float @func1(float %a, float %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fsub.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fsub float %a, %b
ret float %r
}
define double @func2(double %a, double %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fsub.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fsub double %a, %b
ret double %r
}
define float @func4(float %a) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, -1063256064
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd float %a, -5.000000e+00
ret float %r
}
define double @func5(double %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, -1072431104
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd double %a, -5.000000e+00
ret double %r
}
define float @func7(float %a) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, -8388609
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fadd.s %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd float %a, 0xC7EFFFFFE0000000
ret float %r
}
define double @func8(double %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea %s1, -1
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, -1048577(%s1)
; CHECK-NEXT: fadd.d %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = fadd double %a, 0xFFEFFFFFFFFFFFFF
ret double %r
}