This patch registers the 've' target: the NEC SX-Aurora TSUBASA Vector Engine.
This follows up on the announcement on llvm-dev: https://lists.llvm.org/pipermail/llvm-dev/2019-April/131580.html
We have a poster & lightning talk at the upcoming DevMtg: http://llvm.org/devmtg/2019-10/talk-abstracts.html#lit6
- Public documentation (architecture, encodings, instructions)
- ISA manual: https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf
- Up-to-date documentation on architecture and tools: https://www.hpc.nec/documents/
- Reference implementation
- github: https://github.com/sx-aurora-dev/llvm-project
- Status: full scalar instruction support, clang toolchain integration, vector support through intrinsics.
- Reference implementation is tested continuously at NEC.
- We are planning to setup a buildslave reporting to LLVM buildmaster.
- Code owner of the VE target
- Simon Moll
A rough roadmap:
- Registers, encodings, scalar instructions, clang tooling, ..
- Vector instruction support through target-specific intrinsics.
- Support for LLVM-VP as it becomes available in LLVM upstream.